mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-10 12:57:06 +09:00
mfd:rk616:add clk common init,add debug interface
This commit is contained in:
yxj
@@ -4,11 +4,16 @@
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#include <linux/delay.h>
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#include <linux/mfd/core.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#include <linux/mfd/rk616.h>
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#include <linux/clk.h>
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#include <mach/iomux.h>
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#include <linux/err.h>
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#include <linux/uaccess.h>
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#if defined(CONFIG_DEBUG_FS)
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#include <linux/fs.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#endif
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static struct mfd_cell rk616_devs[] = {
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@@ -89,8 +94,85 @@ static int rk616_i2c_write_reg(struct mfd_rk616 *rk616, u16 reg,u32 *pval)
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}
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static int rk616_clk_route_init(struct mfd_rk616 *rk616)
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#if defined(CONFIG_DEBUG_FS)
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static int rk616_reg_show(struct seq_file *s, void *v)
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{
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int i = 0;
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u32 val = 0;
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struct mfd_rk616 *rk616 = s->private;
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if(!rk616)
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{
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dev_err(rk616->dev,"no mfd rk616!\n");
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return 0;
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}
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for(i=0;i<= CRU_CFGMISC_CON;i+=4)
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{
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rk616->read_dev(rk616,i,&val);
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seq_printf(s,"0x%04x>>0x%08x\n",i,val);
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}
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return 0;
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}
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static ssize_t rk616_reg_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos)
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{
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struct mfd_rk616 *rk616 = file->f_path.dentry->d_inode->i_private;
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u32 reg;
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u32 val;
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char kbuf[25];
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if (copy_from_user(kbuf, buf, count))
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return -EFAULT;
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sscanf(kbuf, "%x%x", ®,&val);
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dev_dbg(rk616->dev,"%s:reg:0x%04x val:0x%08x\n",__func__,reg,val);
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rk616->write_dev(rk616,reg,&val);
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return count;
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}
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static int rk616_reg_open(struct inode *inode, struct file *file)
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{
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struct mfd_rk616 *rk616 = inode->i_private;
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return single_open(file,rk616_reg_show,rk616);
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}
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static const struct file_operations rk616_reg_fops = {
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.owner = THIS_MODULE,
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.open = rk616_reg_open,
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.read = seq_read,
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.write = rk616_reg_write,
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.llseek = seq_lseek,
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.release = single_release,
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};
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#endif
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/***********************************
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default clk patch settiing:
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CLKIN-------->CODEC
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LCD_DCLK0--->PLL0--->Dither--->LVDS/MIPI
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LCD_DCLK1--->PLL1--->HDMI
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************************************/
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static int rk616_clk_common_init(struct mfd_rk616 *rk616)
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{
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u32 val = 0;
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int ret;
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val = PLL1_CLK_SEL(1) | PLL0_CLK_SEL(0) | LCD1_CLK_DIV(0) | LCD0_CLK_DIV(0) |
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PLL1_CLK_SEL_MASK | PLL0_CLK_SEL_MASK | LCD1_CLK_DIV_MASK |
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LCD0_CLK_DIV_MASK; //pll1 clk from lcdc1_dclk,pll0 clk from lcdc0_dclk,mux_lcdx = lcdx_clk
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ret = rk616->write_dev(rk616,CRU_CLKSEL0_CON,&val);
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val = CODEC_MCLK_SEL(2) | CODEC_MCLK_SEL_MASK; //codec mclk from clkin
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ret = rk616->write_dev(rk616,CRU_CLKSEL1_CON,&val);
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val = 0; //codec mck = clkin
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ret = rk616->write_dev(rk616,CRU_CODEC_DIV,&val);
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val = (PLL0_BYPASS) | (PLL0_BYPASS << 16); //bypass pll0
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ret = rk616->write_dev(rk616,CRU_PLL0_CON0,&val);
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val = (PLL1_BYPASS) | (PLL1_BYPASS << 16);
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ret = rk616->write_dev(rk616,CRU_PLL1_CON0,&val);
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return 0;
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}
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@@ -146,6 +228,10 @@ static int rk616_i2c_probe(struct i2c_client *client,const struct i2c_device_id
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}
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rk616->read_dev = rk616_i2c_read_reg;
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rk616->write_dev = rk616_i2c_write_reg;
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#if defined(CONFIG_DEBUG_FS)
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debugfs_create_file("rk616-reg", S_IRUSR,NULL,rk616,&rk616_reg_fops);
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#endif
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rk616_clk_common_init(rk616);
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ret = mfd_add_devices(rk616->dev, -1,
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rk616_devs, ARRAY_SIZE(rk616_devs),
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NULL, rk616->irq_base);
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@@ -116,7 +116,6 @@ static int rk616_display_router_cfg(struct mfd_rk616 *rk616)
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(route->vif0_bypass<<1) ;
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ret = rk616->write_dev(rk616,CRU_CLKSE2_CON,&val);
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val = 0;
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val = (LVDS_CH0TTL_DISABLE) | (LVDS_CH1TTL_DISABLE) | (LVDS_CH0_PWR_EN) |
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(LVDS_CBG_PWR_EN) | (LVDS_CH0TTL_DISABLE << 16) | (LVDS_CH1TTL_DISABLE << 16) |
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(LVDS_CH0_PWR_EN << 16) | (LVDS_CBG_PWR_EN << 16);
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@@ -11,122 +11,128 @@
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#define VIF0_DDR_MODE_EN (1<<1)
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#define VIF0_EN (1<<0)
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#define VIF0_REG1 0x0004
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#define VIF0_REG2 0x0008
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#define VIF0_REG3 0x000C
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#define VIF0_REG4 0x0010
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#define VIF0_REG5 0x0014
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#define VIF1_REG0 0x0018
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#define VIF1_REG1 0x001C
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#define VIF1_REG2 0x0020
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#define VIF1_REG3 0x0024
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#define VIF1_REG4 0x0028
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#define VIF1_REG5 0x002C
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#define SCL_REG0 0x0030
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#define SCL_EN (1<<0)
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#define VIF0_REG1 0x0004
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#define VIF0_REG2 0x0008
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#define VIF0_REG3 0x000C
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#define VIF0_REG4 0x0010
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#define VIF0_REG5 0x0014
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#define VIF1_REG0 0x0018
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#define VIF1_REG1 0x001C
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#define VIF1_REG2 0x0020
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#define VIF1_REG3 0x0024
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#define VIF1_REG4 0x0028
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#define VIF1_REG5 0x002C
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#define SCL_REG0 0x0030
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#define SCL_EN (1<<0)
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#define SCL_REG1 0x0034
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#define SCL_REG2 0x0038
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#define SCL_REG3 0x003C
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#define SCL_REG4 0x0040
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#define SCL_REG5 0x0044
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#define SCL_REG6 0x0048
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#define SCL_REG7 0x004C
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#define SCL_REG8 0x0050
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#define FRC_REG 0x0054
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#define SCL_REG1 0x0034
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#define SCL_REG2 0x0038
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#define SCL_REG3 0x003C
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#define SCL_REG4 0x0040
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#define SCL_REG5 0x0044
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#define SCL_REG6 0x0048
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#define SCL_REG7 0x004C
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#define SCL_REG8 0x0050
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#define FRC_REG 0x0054
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#define CRU_CLKSEL0_CON 0x0058
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#define PLL1_IN_SEL(x) (((x)&3)<<8)
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#define PLL0_IN_SEL(x) (((x)&3)<<6)
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#define LCD1_CLK_DIV(x) (((x)&7)<<3)
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#define LCD0_CLK_DIV(x) (((x)&7)<<0)
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#define CRU_CLKSEL0_CON 0x0058
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#define PLL1_CLK_SEL_MASK (0x3<<24)
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#define PLL0_CLK_SEL_MASK (0x3<<22)
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#define LCD1_CLK_DIV_MASK (0x7<<19)
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#define LCD0_CLK_DIV_MASK (0x7<<16)
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#define PLL1_CLK_SEL(x) (((x)&3)<<8)
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#define PLL0_CLK_SEL(x) (((x)&3)<<6)
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#define LCD1_CLK_DIV(x) (((x)&7)<<3)
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#define LCD0_CLK_DIV(x) (((x)&7)<<0)
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#define CRU_CLKSEL1_CON 0x005C
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#define LCDC_CLK_GATE (1<<12)
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#define LCDC1_CLK_GATE (1<<11)
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#define MIPI_CLK_GATE (1<<10)
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#define LVDS_CLK_GATE (1<<9)
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#define HDMI_CLK_GATE (1<<8)
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#define SCL_CLK_DIV (((x)&7)<<5)
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#define SCL_CLK_GATE (1<<4)
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#define SCL_CLK_IN_SEL (1<<3)
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#define CODEC_CLK_GATE (1<<2)
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#define CODEC_CLK_IN_SEL(x) (((x)&3)<<0)
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#define CRU_CODEC_DIV 0x0060
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#define CRU_CLKSEL1_CON 0x005C
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#define CODEC_MCLK_SEL_MASK (3<<16)
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#define LCDC_CLK_GATE (1<<12)
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#define LCDC1_CLK_GATE (1<<11)
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#define MIPI_CLK_GATE (1<<10)
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#define LVDS_CLK_GATE (1<<9)
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#define HDMI_CLK_GATE (1<<8)
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#define SCL_CLK_DIV(x) (((x)&7)<<5)
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#define SCL_CLK_GATE (1<<4)
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#define SCL_CLK_IN_SEL (1<<3)
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#define CODEC_CLK_GATE (1<<2)
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#define CODEC_MCLK_SEL(x) (((x)&3)<<0)
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#define CRU_CLKSE2_CON 0x0064
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#define SCLIN_CLK_SEL (1<<15)
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#define DITHER_CLK_SEL (1<<14)
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#define HDMI_CLK_SEL(x) (((x)&3)<<12)
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#define VIF1_CLK_DIV(x) (((x)&7)<<9)
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#define VIF1_CLK_GATE (1<<8)
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#define VIF1_CLK_BYPASS (1<<7)
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#define VIF1_CLK_SEL (1<<6)
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#define VIF0_CLK_DIV(x) (((x)&7)<<3)
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#define VIF0_CLK_GATE (1<<2)
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#define VIF0_CLK_BYPASS (1<<1)
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#define VIF0_CLK_SEL (1<<0)
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#define CRU_CODEC_DIV 0x0060
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#define CRU_PLL0_CON0 0x0068
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#define PLL0_BYPASS (1<<15)
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#define PLL0_POSTDIV1(x) (((x)&7)<<12)
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#define PLL0_FBDIV(x) (((x)&0xfff)<<0)
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#define CRU_CLKSE2_CON 0x0064
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#define SCLIN_CLK_SEL (1<<15)
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#define DITHER_CLK_SEL (1<<14)
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#define HDMI_CLK_SEL(x) (((x)&3)<<12)
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#define VIF1_CLK_DIV(x) (((x)&7)<<9)
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#define VIF1_CLK_GATE (1<<8)
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#define VIF1_CLK_BYPASS (1<<7)
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#define VIF1_CLK_SEL (1<<6)
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#define VIF0_CLK_DIV(x) (((x)&7)<<3)
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#define VIF0_CLK_GATE (1<<2)
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#define VIF0_CLK_BYPASS (1<<1)
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#define VIF0_CLK_SEL (1<<0)
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#define CRU_PLL0_CON1 0x006C
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#define PLL0_PWR_DN (1<<10)
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#define PLL0_DIV_MODE (1<<9)
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#define PLL0_POSTDIV2(x)(((x)&7)<<6)
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#define PLL0_REFDIV(x) (((x)&0x3f)<<0)
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#define CRU_PLL0_CON0 0x0068
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#define PLL0_BYPASS (1<<15)
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#define PLL0_POSTDIV1(x) (((x)&7)<<12)
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#define PLL0_FBDIV(x) (((x)&0xfff)<<0)
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#define CRU_PLL0_CON2 0x0070
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#define CRU_PLL0_CON1 0x006C
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#define PLL0_PWR_DN (1<<10)
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#define PLL0_DIV_MODE (1<<9)
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#define PLL0_POSTDIV2(x) (((x)&7)<<6)
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#define PLL0_REFDIV(x) (((x)&0x3f)<<0)
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#define CRU_PLL0_CON2 0x0070
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#define PLL0_FOUT4_PWR_DN (1<<27)
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#define PLL0_FOUTVCO_PWR_DN (1<<26)
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#define PLL0_POSTDIV_PWR_DN (1<<25)
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#define PLL0_DAC_PWR_DN (1<<24)
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#define PLL0_FRAC(x) (((x)&0xffffff)<0)
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#define CRU_PLL1_CON0 0x0074
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#define PLL1_BYPASS (1<<15)
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#define PLL1_POSTDIV1(x) (((x)&7)<<12)
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#define PLL1_FBDIV(x) (((x)&0xfff)<<0)
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#define CRU_PLL1_CON0 0x0074
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#define PLL1_BYPASS (1<<15)
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#define PLL1_POSTDIV1(x) (((x)&7)<<12)
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#define PLL1_FBDIV(x) (((x)&0xfff)<<0)
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#define CRU_PLL1_CON1 0x0078
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#define PLL1_PWR_DN (1<<10)
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#define PLL1_DIV_MODE (1<<9)
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#define PLL1_POSTDIV2(x)(((x)&7)<<6)
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#define PLL1_REFDIV(x) (((x)&0x3f)<<0)
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#define CRU_PLL1_CON1 0x0078
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#define PLL1_PWR_DN (1<<10)
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#define PLL1_DIV_MODE (1<<9)
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#define PLL1_POSTDIV2(x) (((x)&7)<<6)
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#define PLL1_REFDIV(x) (((x)&0x3f)<<0)
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#define CRU_PLL1_CON2 0x007C
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#define CRU_PLL1_CON2 0x007C
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#define PLL1_FOUT4_PWR_DN (1<<27)
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#define PLL1_FOUTVCO_PWR_DN (1<<26)
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#define PLL1_POSTDIV_PWR_DN (1<<25)
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#define PLL1_DAC_PWR_DN (1<<24)
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#define PLL1_FRAC(x) (((x)&0xffffff)<0)
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#define CRU_I2C_CON0 0x0080
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#define CRU_I2C_CON0 0x0080
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#define CRU_LVDS_CON0 0x0084
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#define LVDS_CON_ST_PHASE (1<<14)
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#define LVDS_DCLK_INV (1<<13)
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#define LVDS_CH1_LOAD (1<<12)
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#define LVDS_CH0_LOAD (1<<11)
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#define LVDS_CH1TTL_DISABLE (1<<10)
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#define LVDS_CH0TTL_DISABLE (1<<9)
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#define LVDS_CH1_PWR_EN (1<<8)
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#define LVDS_CH0_PWR_EN (1<<7)
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#define LVDS_CBG_PWR_EN (1<<6)
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#define LVDS_PLL_PWR_DN (1<<5)
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#define LVDS_START_CH_SEL (1<<4)
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#define LVDS_CH_SEL (1<<3)
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#define LVDS_MSB_SEL (1<<2)
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#define LVDS_OUT_FORMAT (1<<0)
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#define CRU_LVDS_CON0 0x0084
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#define LVDS_CON_ST_PHASE (1<<14)
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#define LVDS_DCLK_INV (1<<13)
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#define LVDS_CH1_LOAD (1<<12)
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#define LVDS_CH0_LOAD (1<<11)
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#define LVDS_CH1TTL_DISABLE (1<<10)
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#define LVDS_CH0TTL_DISABLE (1<<9)
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#define LVDS_CH1_PWR_EN (1<<8)
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#define LVDS_CH0_PWR_EN (1<<7)
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#define LVDS_CBG_PWR_EN (1<<6)
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#define LVDS_PLL_PWR_DN (1<<5)
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#define LVDS_START_CH_SEL (1<<4)
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#define LVDS_CH_SEL (1<<3)
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#define LVDS_MSB_SEL (1<<2)
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#define LVDS_OUT_FORMAT (1<<0)
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#define CRU_IO_CON0 0x0088
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#define I2S1_OUT_EN (1<<13)
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#define I2S0_OUT_EN (1<<12)
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#define LVDS_OUT_EN (1<<11)
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#define LCD1_INPUT_EN (1<<10)
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#define CRU_IO_CON0 0x0088
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#define I2S1_OUT_EN (1<<13)
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#define I2S0_OUT_EN (1<<12)
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#define LVDS_OUT_EN (1<<11)
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#define LCD1_INPUT_EN (1<<10)
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#define LVDS_RGBIO_PD_DISABLE (1<<9)
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#define LCD1_IO_PD_DISABLE (1<<8)
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#define LCD0_IO_PD_DISABLE (1<<7)
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@@ -158,17 +164,6 @@
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struct rk616_platform_data {
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int (*power_init)(void);
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int scl_rate;
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@@ -195,7 +190,7 @@ struct mfd_rk616 {
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struct rk616_platform_data *pdata;
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struct rk616_route *route; //display path router
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struct i2c_client *client;
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int (*read_dev)(struct mfd_rk616 *rk616, u16 reg,u32 *pval);
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int (*read_dev)(struct mfd_rk616 *rk616,u16 reg,u32 *pval);
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int (*write_dev)(struct mfd_rk616 *rk616,u16 reg,u32 *pval);
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};
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