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phy: rockchip: naneng-combphy: Add RMJ control for PCIe

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Change-Id: Iaf2d8fab379aa77dc127778b3943000b0e4bf2a6
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
This commit is contained in:
Shawn Lin
2020-11-18 10:27:08 +08:00
parent dc3e6cd531
commit 266ef3dda3
1 changed files with 11 additions and 0 deletions
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11
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -296,6 +296,7 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
struct clk *refclk = NULL;
unsigned long rate;
int i;
u32 val;
/* Configure PHY reference clock frequency */
for (i = 0; i < priv->num_clks; i++) {
@@ -337,6 +338,16 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
/* Enable controlling random jitter, aka RMJ */
val = readl(priv->mmio + (0xa << 2));
val &= ~(0x77);
val |= 0x3 << 4;
writel(val, priv->mmio + (0xa << 2));
val = readl(priv->mmio + (0x20 << 2));
val &= ~(0x1c);
val |= 0x5 << 2;
writel(val, priv->mmio + (0x20 << 2));
break;
case PHY_TYPE_USB3:
/* Set ssc downward spread spectrum */