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drm/rockchip: vop2: add config ports background color

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before this commit, the bt1120/bt656/hdmi yuv output will display green
screen at power on state.

Change-Id: I21ee96f0883e0edc5f3a4cec1bf7bac25d15c775
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This commit is contained in:
Sandy Huang
2020-11-23 15:01:21 +08:00
committed by Tao Huang
parent 39e25c9a06
commit 26965a0de4
4 changed files with 13 additions and 0 deletions
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1
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
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@@ -505,6 +505,7 @@ struct vop2_win_regs {
struct vop2_video_port_regs {
struct vop_reg cfg_done;
struct vop_reg overlay_mode;
struct vop_reg dsp_background;
struct vop_reg port_mux;
struct vop_reg out_mode;
struct vop_reg standby;

6
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -2857,6 +2857,12 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000);
if (is_yuv_output(vcstate->bus_format))
val = 0x20010200;
else
val = 0;
VOP_MODULE_SET(vop2, vp, dsp_background, val);
vop2_cfg_done(crtc);
drm_crtc_vblank_on(crtc);

3
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -350,6 +350,7 @@ static const struct vop_intr rk3568_vp2_intr = {
static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
.dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0x3fffffff, 0),
.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 0),
.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
.standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
@@ -407,6 +408,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1),
.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 1),
.dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0x3fffffff, 0),
.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 4),
.out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
@@ -439,6 +441,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
static const struct vop2_video_port_regs rk3568_vop_vp2_regs = {
.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 2),
.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 2),
.dsp_background = VOP_REG(RK3568_VP2_DSP_BG, 0x3fffffff, 0),
.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 8),
.out_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0xf, 0),
.standby = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31),

3
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -1077,6 +1077,7 @@
#define RK3568_VP0_DSP_CTRL 0xC00
#define RK3568_VP0_MIPI_CTRL 0xC04
#define RK3568_VP0_COLOR_BAR_CTRL 0xC08
#define RK3568_VP0_DSP_BG 0xC2C
#define RK3568_VP0_PRE_SCAN_HTIMING 0xC30
#define RK3568_VP0_POST_DSP_HACT_INFO 0xC34
#define RK3568_VP0_POST_DSP_VACT_INFO 0xC38
@@ -1093,6 +1094,7 @@
#define RK3568_VP1_DSP_CTRL 0xD00
#define RK3568_VP1_MIPI_CTRL 0xD04
#define RK3568_VP1_COLOR_BAR_CTRL 0xD08
#define RK3568_VP1_DSP_BG 0xD2C
#define RK3568_VP1_PRE_SCAN_HTIMING 0xD30
#define RK3568_VP1_POST_DSP_HACT_INFO 0xD34
#define RK3568_VP1_POST_DSP_VACT_INFO 0xD38
@@ -1111,6 +1113,7 @@
#define RK3568_VP2_DSP_CTRL 0xE00
#define RK3568_VP2_MIPI_CTRL 0xE04
#define RK3568_VP2_COLOR_BAR_CTRL 0xE08
#define RK3568_VP2_DSP_BG 0xE2C
#define RK3568_VP2_PRE_SCAN_HTIMING 0xE30
#define RK3568_VP2_POST_DSP_HACT_INFO 0xE34
#define RK3568_VP2_POST_DSP_VACT_INFO 0xE38