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PCI: cadence: Write MSI data with 32bits

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[ Upstream commit e81e36a96b ]

According to the PCIe specification, although the MSI data is only
16bits, the upper 16bits should be written as 0. Use writel
instead of writew when writing the MSI data to the host.

Fixes: 37dddf14f1 ("PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller")
Signed-off-by: Alan Douglas <adouglas@cadence.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Alan Douglas
2018-10-11 17:15:54 +01:00
committed by Greg Kroah-Hartman
parent ca71f9c8ad
commit 26a4c6a562
1 changed files with 1 additions and 1 deletions
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2
drivers/pci/controller/pcie-cadence-ep.c
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@@ -355,7 +355,7 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
ep->irq_pci_fn = fn;
}
writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
return 0;
}