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ASoC: rockchip: i2s: add pcm transfer mode support.
usage: add i2s dts property "rockchip,xfer-mode" rockchip,xfer-mode = <0>: i2s transfer mode. rockchip,xfer-mode = <1>: pcm transfer mode. if not define, use i2s transfer mode default. pcm transfer mode is usually used for bt/modem voice. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
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@@ -6,6 +6,7 @@ Required SoC Specific Properties:
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- reg: physical base address of the controller and length of memory mapped
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region.
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- i2s-id: i2s controller id,
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- rockchip,xfer-mode: transfer mode select, 0:i2s, 1: pcm.
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- clocks: must include clock specifiers corresponding to entries in the
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clock-names property.
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- clocks-names: list of clock names sorted in the same order as the clocks
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@@ -63,6 +63,7 @@ struct rk_i2s_dev {
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struct regmap *regmap;
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bool tx_start;
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bool rx_start;
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int xfer_mode; /* 0: i2s, 1: pcm */
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#ifdef CLK_SET_LATER
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struct delayed_work clk_delayed_work;
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#endif
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@@ -709,6 +710,19 @@ static int rockchip_i2s_probe(struct platform_device *pdev)
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goto err_unregister_component;
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}
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ret = of_property_read_u32(node, "rockchip,xfer-mode", &i2s->xfer_mode);
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if (ret < 0)
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i2s->xfer_mode = I2S_XFER_MODE;
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if (PCM_XFER_MODE == i2s->xfer_mode) {
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regmap_update_bits(i2s->regmap, I2S_TXCR,
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I2S_TXCR_TFS_MASK,
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I2S_TXCR_TFS_PCM);
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regmap_update_bits(i2s->regmap, I2S_RXCR,
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I2S_RXCR_TFS_MASK,
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I2S_RXCR_TFS_PCM);
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}
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rockchip_snd_txctrl(i2s, 0);
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rockchip_snd_rxctrl(i2s, 0);
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@@ -774,6 +788,15 @@ static int rockchip_i2s_resume(struct device *dev)
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return ret;
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ret = regmap_reinit_cache(i2s->regmap, &rockchip_i2s_regmap_config);
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if (PCM_XFER_MODE == i2s->xfer_mode) {
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regmap_update_bits(i2s->regmap, I2S_TXCR,
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I2S_TXCR_TFS_MASK,
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I2S_TXCR_TFS_PCM);
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regmap_update_bits(i2s->regmap, I2S_RXCR,
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I2S_RXCR_TFS_MASK,
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I2S_RXCR_TFS_PCM);
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}
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pm_runtime_put(dev);
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dev_dbg(i2s->dev, "%s\n", __func__);
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@@ -48,6 +48,7 @@
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#define I2S_TXCR_TFS_SHIFT 5
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#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
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#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
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#define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT)
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#define I2S_TXCR_VDW_SHIFT 0
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#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
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#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
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@@ -74,6 +75,7 @@
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#define I2S_RXCR_TFS_SHIFT 5
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#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
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#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
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#define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT)
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#define I2S_RXCR_VDW_SHIFT 0
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#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
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#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
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@@ -223,4 +225,7 @@
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#define I2S_CHANNEL_4 4
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#define I2S_CHANNEL_2 2
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#define I2S_XFER_MODE 0
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#define PCM_XFER_MODE 1
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#endif /* __RK_I2S_H__ */
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