ASoC: rockchip: i2s: add pcm transfer mode support.

usage: add i2s dts property "rockchip,xfer-mode"

rockchip,xfer-mode = <0>: i2s transfer mode.
rockchip,xfer-mode = <1>: pcm transfer mode.

if not define, use i2s transfer mode default.
pcm transfer mode is usually used for bt/modem voice.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This commit is contained in:
Sugar Zhang
2015-07-24 18:04:31 +08:00
parent b245ea6eb5
commit 26ea8b87f0
3 changed files with 29 additions and 0 deletions

View File

@@ -6,6 +6,7 @@ Required SoC Specific Properties:
- reg: physical base address of the controller and length of memory mapped
region.
- i2s-id: i2s controller id,
- rockchip,xfer-mode: transfer mode select, 0:i2s, 1: pcm.
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clocks-names: list of clock names sorted in the same order as the clocks

View File

@@ -63,6 +63,7 @@ struct rk_i2s_dev {
struct regmap *regmap;
bool tx_start;
bool rx_start;
int xfer_mode; /* 0: i2s, 1: pcm */
#ifdef CLK_SET_LATER
struct delayed_work clk_delayed_work;
#endif
@@ -709,6 +710,19 @@ static int rockchip_i2s_probe(struct platform_device *pdev)
goto err_unregister_component;
}
ret = of_property_read_u32(node, "rockchip,xfer-mode", &i2s->xfer_mode);
if (ret < 0)
i2s->xfer_mode = I2S_XFER_MODE;
if (PCM_XFER_MODE == i2s->xfer_mode) {
regmap_update_bits(i2s->regmap, I2S_TXCR,
I2S_TXCR_TFS_MASK,
I2S_TXCR_TFS_PCM);
regmap_update_bits(i2s->regmap, I2S_RXCR,
I2S_RXCR_TFS_MASK,
I2S_RXCR_TFS_PCM);
}
rockchip_snd_txctrl(i2s, 0);
rockchip_snd_rxctrl(i2s, 0);
@@ -774,6 +788,15 @@ static int rockchip_i2s_resume(struct device *dev)
return ret;
ret = regmap_reinit_cache(i2s->regmap, &rockchip_i2s_regmap_config);
if (PCM_XFER_MODE == i2s->xfer_mode) {
regmap_update_bits(i2s->regmap, I2S_TXCR,
I2S_TXCR_TFS_MASK,
I2S_TXCR_TFS_PCM);
regmap_update_bits(i2s->regmap, I2S_RXCR,
I2S_RXCR_TFS_MASK,
I2S_RXCR_TFS_PCM);
}
pm_runtime_put(dev);
dev_dbg(i2s->dev, "%s\n", __func__);

View File

@@ -48,6 +48,7 @@
#define I2S_TXCR_TFS_SHIFT 5
#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
#define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT)
#define I2S_TXCR_VDW_SHIFT 0
#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
@@ -74,6 +75,7 @@
#define I2S_RXCR_TFS_SHIFT 5
#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
#define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT)
#define I2S_RXCR_VDW_SHIFT 0
#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
@@ -223,4 +225,7 @@
#define I2S_CHANNEL_4 4
#define I2S_CHANNEL_2 2
#define I2S_XFER_MODE 0
#define PCM_XFER_MODE 1
#endif /* __RK_I2S_H__ */