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hdmirx: Chromecast box force to OESS mode [1/1]

Browse Source 
PD#SWPL-4325

Problem:
it took long time to show image when connect with Google Chromecast box

Solution:
1. add specific dev detection by cec osd name & vendor ID
2. chromecast box force OESS

Verify:
verify by marconi

Change-Id: I56d247da1d1b1e28b60bb439f5173cb6fbecfdf9
Signed-off-by: Lei Yang <lei.yang@amlogic.com>

hdmirx: Chromecast box force to OESS mode [1/1] (Partial)

PD#SWPL-4325

Problem:
it took long time to show image when connect with Google Chromecast box

Solution:
1. add specific dev detection by cec osd name & vendor ID
2. chromecast box force OESS

Verify:
verify by marconi

Change-Id: I56d247da1d1b1e28b60bb439f5173cb6fbecfdf9
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
This commit is contained in:
Lei Yang
2019-01-17 19:59:32 +08:00
committed by Luke Go
parent 48742517b9
commit 26fc6ff81d
5 changed files with 18 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/amlogic/cec/hdmi_ao_cec.h
View File

@@ -534,7 +534,8 @@ extern uint32_t hdmirx_rd_dwc(uint16_t addr);
extern void hdmirx_wr_dwc(uint16_t addr, uint32_t data);
extern unsigned int rd_reg_hhi(unsigned int offset);
extern void wr_reg_hhi(unsigned int offset, unsigned int val);
extern int cec_set_dev_info(uint8_t dev_idx);
int __attribute__((weak))cec_set_dev_info(uint8_t dev_idx);
#else
static inline unsigned long hdmirx_rd_top(unsigned long addr)
{

4
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
View File

@@ -41,7 +41,7 @@
*
*
*/
#define RX_VER1 "ver.2019/01/08"
#define RX_VER1 "ver.2019/01/28"
/*
*
*
@@ -476,7 +476,7 @@ extern struct reg_map reg_maps[MAP_ADDR_MODULE_NUM];
extern bool downstream_repeat_support;
extern void rx_tasklet_handler(unsigned long arg);
extern void skip_frame(unsigned int cnt);
extern int cec_set_dev_info(uint8_t dev_idx);
/* reg */

5
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c
View File

@@ -64,9 +64,8 @@ static DEFINE_SPINLOCK(reg_rw_lock);
static bool phy_fast_switching;
static bool phy_fsm_enhancement = true;
/*unsigned int last_clk_rate;*/
static uint32_t modet_clk = 24000;
int hdcp_enc_mode;
/* top_irq_en bit[16:13] hdcp_sts */
int top_intr_maskn_value = 1;
bool hdcp_enable = 1;
@@ -1425,7 +1424,7 @@ static int DWC_init(void)
/* 1: force OESS */
/* 2: force EESS */
/* 3: auto mode,check CTL[3:0]=d9/d8 during WOO */
data32 |= (0 << 2);
data32 |= (hdcp_enc_mode << 2);
data32 |= (0 << 0);
hdmirx_wr_dwc(DWC_HDMI_MODE_RECOVER, data32);

1
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h
View File

@@ -1091,6 +1091,7 @@ extern unsigned int hdmirx_addr_port;
extern unsigned int hdmirx_data_port;
extern unsigned int hdmirx_ctrl_port;
extern int acr_mode;
extern int hdcp_enc_mode;
extern int force_clk_rate;
extern int auto_aclk_mute;
extern int aud_avmute_en;

11
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
View File

@@ -236,6 +236,17 @@ void rx_hpd_to_esm_handle(struct work_struct *work)
rx_pr("esm_hpd-1\n");
}
int cec_set_dev_info(uint8_t dev_idx)
{
cec_dev_info |= 1 << dev_idx;
if (dev_idx == 1)
hdcp_enc_mode = 1;
return 0;
}
EXPORT_SYMBOL(cec_set_dev_info);
/*
*func: irq tasklet
*param: flag: