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media: i2c: imx415: add 720P config
Change-Id: I2af6b9677ecaf0356f12cbd8e15592d26da134e3 Signed-off-by: Lan Honglin <helin.lan@rock-chips.com>
This commit is contained in:
Lan Honglin
@@ -60,6 +60,7 @@
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#define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
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#endif
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#define MIPI_FREQ_1188M 1188000000
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#define MIPI_FREQ_891M 891000000
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#define MIPI_FREQ_446M 446000000
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#define MIPI_FREQ_743M 743000000
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@@ -897,6 +898,167 @@ static __maybe_unused const struct regval imx415_linear_12bit_3864x2192_891M_reg
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{REG_NULL, 0x00},
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};
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/*
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* Xclk 27Mhz
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* 90.059fps
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* CSI-2_2lane
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* AD:10bit Output:12bit
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* 2376Mbps
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* Master Mode
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* Time 9.999ms Gain:6dB
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* 2568x1440 2/2-line binning & Window cropping
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*/
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static __maybe_unused const struct regval imx415_linear_12bit_1284x720_2376M_regs_2lane[] = {
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{0x3008, 0x5D},
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{0x300A, 0x42},
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{0x301C, 0x04},
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{0x3020, 0x01},
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{0x3021, 0x01},
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{0x3022, 0x01},
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{0x3024, 0xAB},
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{0x3025, 0x07},
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{0x3028, 0xA4},
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{0x3029, 0x01},
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{0x3031, 0x00},
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{0x3033, 0x00},
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{0x3040, 0x88},
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{0x3041, 0x02},
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{0x3042, 0x08},
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{0x3043, 0x0A},
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{0x3044, 0xF0},
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{0x3045, 0x02},
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{0x3046, 0x40},
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{0x3047, 0x0B},
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{0x3050, 0xC4},
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{0x3090, 0x14},
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{0x30C1, 0x00},
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{0x30D9, 0x02},
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{0x30DA, 0x01},
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{0x3116, 0x23},
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{0x3118, 0x08},
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{0x3119, 0x01},
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{0x311A, 0xE7},
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{0x311E, 0x23},
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{0x32D4, 0x21},
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{0x32EC, 0xA1},
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{0x344C, 0x2B},
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{0x344D, 0x01},
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{0x344E, 0xED},
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{0x344F, 0x01},
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{0x3450, 0xF6},
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{0x3451, 0x02},
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{0x3452, 0x7F},
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{0x3453, 0x03},
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{0x358A, 0x04},
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{0x35A1, 0x02},
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{0x35EC, 0x27},
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{0x35EE, 0x8D},
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{0x35F0, 0x8D},
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{0x35F2, 0x29},
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{0x36BC, 0x0C},
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{0x36CC, 0x53},
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{0x36CD, 0x00},
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{0x36CE, 0x3C},
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{0x36D0, 0x8C},
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{0x36D1, 0x00},
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{0x36D2, 0x71},
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{0x36D4, 0x3C},
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{0x36D6, 0x53},
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{0x36D7, 0x00},
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{0x36D8, 0x71},
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{0x36DA, 0x8C},
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{0x36DB, 0x00},
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{0x3701, 0x00},
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{0x3720, 0x00},
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{0x3724, 0x02},
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{0x3726, 0x02},
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{0x3732, 0x02},
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{0x3734, 0x03},
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{0x3736, 0x03},
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{0x3742, 0x03},
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{0x3862, 0xE0},
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{0x38CC, 0x30},
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{0x38CD, 0x2F},
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{0x395C, 0x0C},
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{0x39A4, 0x07},
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{0x39A8, 0x32},
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{0x39AA, 0x32},
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{0x39AC, 0x32},
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{0x39AE, 0x32},
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{0x39B0, 0x32},
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{0x39B2, 0x2F},
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{0x39B4, 0x2D},
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{0x39B6, 0x28},
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{0x39B8, 0x30},
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{0x39BA, 0x30},
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{0x39BC, 0x30},
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{0x39BE, 0x30},
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{0x39C0, 0x30},
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{0x39C2, 0x2E},
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{0x39C4, 0x2B},
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{0x39C6, 0x25},
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{0x3A42, 0xD1},
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{0x3A4C, 0x77},
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{0x3AE0, 0x02},
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{0x3AEC, 0x0C},
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{0x3B00, 0x2E},
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{0x3B06, 0x29},
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{0x3B98, 0x25},
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{0x3B99, 0x21},
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{0x3B9B, 0x13},
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{0x3B9C, 0x13},
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{0x3B9D, 0x13},
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{0x3B9E, 0x13},
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{0x3BA1, 0x00},
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{0x3BA2, 0x06},
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{0x3BA3, 0x0B},
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{0x3BA4, 0x10},
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{0x3BA5, 0x14},
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{0x3BA6, 0x18},
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{0x3BA7, 0x1A},
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{0x3BA8, 0x1A},
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{0x3BA9, 0x1A},
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{0x3BAC, 0xED},
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{0x3BAD, 0x01},
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{0x3BAE, 0xF6},
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{0x3BAF, 0x02},
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{0x3BB0, 0xA2},
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{0x3BB1, 0x03},
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{0x3BB2, 0xE0},
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{0x3BB3, 0x03},
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{0x3BB4, 0xE0},
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{0x3BB5, 0x03},
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{0x3BB6, 0xE0},
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{0x3BB7, 0x03},
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{0x3BB8, 0xE0},
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{0x3BBA, 0xE0},
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{0x3BBC, 0xDA},
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{0x3BBE, 0x88},
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{0x3BC0, 0x44},
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{0x3BC2, 0x7B},
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{0x3BC4, 0xA2},
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{0x3BC8, 0xBD},
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{0x3BCA, 0xBD},
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{0x4001, 0x01},
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{0x4004, 0xC0},
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{0x4005, 0x06},
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{0x4018, 0xE7},
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{0x401A, 0x8F},
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{0x401C, 0x8F},
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{0x401E, 0x7F},
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{0x401F, 0x02},
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{0x4020, 0x97},
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{0x4022, 0x0F},
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{0x4023, 0x01},
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{0x4024, 0x97},
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{0x4026, 0xF7},
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{0x4028, 0x7F},
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{0x3002, 0x00},
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//{0x3000, 0x00},
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{REG_DELAY, 0x1E},//wait_ms(30)
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{REG_NULL, 0x00},
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};
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/*
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* The width and height must be configured to be
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* the same as the current output resolution of the sensor.
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@@ -1151,6 +1313,26 @@ static const struct imx415_mode supported_modes_2lane[] = {
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.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
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.xvclk = IMX415_XVCLK_FREQ_27M,
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},
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{
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/* 1H period = (1100 clock) = (1100 * 1 / 74.25MHz) */
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.bus_fmt = MEDIA_BUS_FMT_SGBRG12_1X12,
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.width = 1284,
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.height = 720,
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.max_fps = {
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.numerator = 10000,
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.denominator = 900000,
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},
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.exp_def = 0x07AB-8,
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.hts_def = 0x01A4 * IMX415_2LANES * 2,
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.vts_def = 0x07AB,
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.global_reg_list = NULL,
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.reg_list = imx415_linear_12bit_1284x720_2376M_regs_2lane,
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.hdr_mode = NO_HDR,
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.mipi_freq_idx = 4,
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.bpp = 12,
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.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
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.xvclk = IMX415_XVCLK_FREQ_27M,
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},
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};
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static const s64 link_freq_items[] = {
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@@ -1158,6 +1340,7 @@ static const s64 link_freq_items[] = {
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MIPI_FREQ_446M,
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MIPI_FREQ_743M,
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MIPI_FREQ_891M,
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MIPI_FREQ_1188M,
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};
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/* Write registers up to 4 at a time */
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@@ -2619,7 +2802,7 @@ static int imx415_initialize_controls(struct imx415 *imx415)
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/* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
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pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * lanes;
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max_pixel_rate = MIPI_FREQ_891M / mode->bpp * 2 * lanes;
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max_pixel_rate = MIPI_FREQ_1188M / mode->bpp * 2 * lanes;
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imx415->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
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V4L2_CID_PIXEL_RATE, 0, max_pixel_rate,
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1, pixel_rate);
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