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clk: rockchip: rk3308: Add rate table for dpll

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DPLL isn't the parent clock of ddr, we may need to change dpll rate for
other devices.

Change-Id: I2b41ccf6df78803980be08e4b82cbfb5c7718b69
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-06-07 10:47:25 +08:00
committed by Tao Huang
parent 0c406a7db0
commit 270ef04c65
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3308.c
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@@ -195,7 +195,7 @@ static struct rockchip_pll_clock rk3308_pll_clks[] __initdata = {
RK3308_MODE_CON, 0, 0, 0, rk3308_pll_rates),
[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
0, RK3308_PLL_CON(8),
RK3308_MODE_CON, 2, 1, 0, NULL),
RK3308_MODE_CON, 2, 1, 0, rk3308_pll_rates),
[vpll0] = PLL(pll_rk3328, PLL_VPLL0, "vpll0", mux_pll_p,
0, RK3308_PLL_CON(16),
RK3308_MODE_CON, 4, 2, 0, rk3308_pll_rates),