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drivers/realtek: update rtl8812au driver

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This commit is contained in:
Mauro (mdrjr) Ribeiro
2019-02-02 13:26:09 -02:00
parent ba9a75f196
commit 273104dca4
430 changed files with 200627 additions and 173752 deletions
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2
arch/arm/configs/odroidxu3_defconfig
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@@ -1,6 +1,6 @@
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm 3.10.105 Kernel Configuration
# Linux/arm 3.10.106 Kernel Configuration
#
CONFIG_ARM=y
CONFIG_ARM_HAS_SG_CHAIN=y

34
backports/drivers/realtek/rtl8812au/CONTRIBUTORS.md Normal file
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## Contributors
<!-- DO NOT EDIT - CONTRIBUTORS.md is autogenerated from git commit log by contributors.sh script. -->
- Anand Babu (AB) Periasamy
- Andreas Hofmann
- Andrew Mann
- AndyPi
- Anton
- archshift
- bits3rpent
- Chen Minqiang
- Daiki Tamada
- Fjodor42
- gremsto
- HackDefendr
- Harshavardhana
- jjones-jr
- Joe
- Joe Acosta
- John Lenz
- Jos Dehaes
- Karl-Philipp Richter
- Marco Milanesi
- Mauro Ribeiro
- Maximilian Schwerin
- mpoly
- Nick Bartos
- Peter H. Li
- pgroenbech
- scrivy
- Taehan Stott
- Vicent Llongo
- Victor Azizi
- 赵迤晨 (Zhao, Yichen)

0
backports/drivers/realtek/rtl8812au/Kconfig Executable file → Normal file
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339
backports/drivers/realtek/rtl8812au/LICENSE Normal file
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@@ -0,0 +1,339 @@
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
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rtl8812AU_8821AU linux kernel driver for AC1200 (801.11ac) Wireless Dual-Band USB Adapter
Copyright (C) 2013 Anand Babu (AB) Periasamy
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
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Also add information on how to contact you by electronic and paper mail.
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This General Public License does not permit incorporating your program into
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Public License instead of this License.

575
backports/drivers/realtek/rtl8812au/Makefile Executable file → Normal file
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27
backports/drivers/realtek/rtl8812au/Makefile.dkms Normal file
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modname := rtl8812au
DKMS := dkms
modver := 4.3.14
# directory in which generated files are stored
DKMS_DEST := /usr/src/$(modname)-$(modver)
all: install
src_install:
make clean
mkdir -p '$(DKMS_DEST)'
cp -r dkms.conf Kconfig Makefile.dkms Makefile platform core hal include os_dep '$(DKMS_DEST)'
cp Makefile '$(DKMS_DEST)/Makefile'
sed 's/#MODULE_VERSION#/$(modver)/' dkms.conf > '$(DKMS_DEST)/dkms.conf'
build: src_install
$(DKMS) add -m $(modname) -v $(modver) 2>/dev/null || true
$(DKMS) build -m $(modname) -v $(modver)
install: build
$(DKMS) install -m $(modname) -v $(modver)
uninstall:
$(DKMS) remove -m $(modname) -v $(modver) --all
.PHONY: all src_install build install uninstall

127
backports/drivers/realtek/rtl8812au/README.md Normal file
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@@ -0,0 +1,127 @@
# rtl8812au
Realtek 8812AU/8821AU USB WiFi driver.
for AC1200 (801.11ac) Wireless Dual-Band USB Adapter
This code is base on version 4.3.14 from https://github.com/diederikdehaas/rtl8812AU
## Known Supported Devices:
```
* COMFAST 1200Mbps USB Wireless Adapter(Model: CF-912AC)
* TP-LINK AC1200 Wireless Dual Band USB Adapter(Model: Archer-T4U)
```
## Compiling with DKMS
```sh
# sudo make -f Makefile.dkms install
```
### Compiling for Raspberry Pi
Install kernel headers and other dependencies.
```sh
# sudo apt-get install linux-image-rpi-rpfv linux-headers-rpi-rpfv dkms build-essential bc
```
Append following at the end of your ``/boot/config.txt``, reboot your Pi
```sh
kernel=vmlinuz-3.10-3-rpi
initramfs initrd.img-3.10-3-rpi followkernel
```
Edit Makefile and turn on ``CONFIG_PLATFORM_ARM_RPI``, turn off ``CONFIG_PLATFORM_I386_PC``
```sh
CONFIG_PLATFORM_I386_PC = n
CONFIG_PLATFORM_ARM_RPI = y
```
```sh
# cd /usr/src/rtl8812au
# sudo make clean
# sudo make
# sudo make install
# sudo modprobe -a rtl8812au
```
### Compiling for Ubuntu (16.04)
Download archive into temp directory
```sh
# mkdir -p /tmp/t4u
# cd /tmp/t4u
# wget https://github.com/abperiasamy/rtl8812AU_8821AU_linux/archive/master.zip
```
Unzip
```sh
# unzip master.zip
# cd rtl8812AU_8821AU_linux-master
```
Compile and install from source
```sh
# make
# sudo make install
```
Load module
```sh
# sudo modprobe -a rtl8812au
```
Setup DKMS
```sh
# sudo apt-get update
# sudo apt-get install dkms
# cd /tmp/t4u/rtl8812AU_8821AU_linux-master/
# sudo cp -R . /usr/src/rtl8812AU_8821AU_linux-1.0
# sudo dkms add -m rtl8812AU_8821AU_linux -v 1.0
# sudo dkms build -m rtl8812AU_8821AU_linux -v 1.0
# sudo dkms install -m rtl8812AU_8821AU_linux -v 1.0
```
## Contributors
<!-- DO NOT EDIT - CONTRIBUTORS.md is autogenerated from git commit log by contributors.sh script. -->
- Anand Babu (AB) Periasamy
- Andreas Hofmann
- Andrew Mann
- AndyPi
- Anton
- archshift
- bits3rpent
- Chen Minqiang
- Daiki Tamada
- Fjodor42
- gremsto
- HackDefendr
- Harshavardhana
- jjones-jr
- Joe
- Joe Acosta
- John Lenz
- Jos Dehaes
- Karl-Philipp Richter
- Marco Milanesi
- Mauro Ribeiro
- Maximilian Schwerin
- mpoly
- Nick Bartos
- Peter H. Li
- pgroenbech
- scrivy
- Taehan Stott
- Vicent Llongo
- Victor Azizi
- 赵迤晨 (Zhao, Yichen)

0
backports/drivers/realtek/rtl8812au/clean Executable file → Normal file
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38
backports/drivers/realtek/rtl8812au/contrib/auto-install.sh Normal file
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#!/bin/bash
##
## Automated setup for Netgear A6100 AC600 usb wifi adapter drivers
## Designed for Ubuntu Xenial 16.04 LTS (and Debian distros generally)
##
## This is a simple bash script to automate the installation of the latest rtl8812AU linux drivers for
## the NETGEAR A6100 AC600 usb wifi dongle from https://github.com/abperiasamy/rtl8812AU_8821AU_linux .
## This script was created specifically for Ubuntu Xenial 16.04 LTS, but should work as is, or with
## minor modifications, on any Debian based linux distribution.
##
## This script:
## (1) installs git to pull the repository and gcc (and associated build tools)
## (2) compiles the driver binary and installs it to the system
## (3) creates a udev rule to rename the interface to "wlan0" (optional)
## (4) loads the driver and adds a modprobe rule to do this at boot
##
## Install Dependencies
apt update
apt install -y git build-essential make autoconf libtool gcc gettext
## Clone latest github repository
cd /var/lib/git
git clone https://github.com/abperiasamy/rtl8812AU_8821AU_linux.git
## Compile and install driver binary
cd rtl8812AU_8821AU_linux
make
make install
## Make udev rule (you can omit this line to have the system automatically name the device, or change NAME="wlan0" to a diffrent device name)
echo 'SUBSYSTEM=="net", ACTION=="add", DRIVERS=="rtl8812au", ATTR{type}=="1", NAME="wlan0"' >> /lib/udev/rules.d/70-persistent-network.rules
## Load driver module
modprobe rtl8812au
## Add module at boot (file may be /etc/modules on other distribution)
echo -e '# Netgear A600 usb wifi dongle\nrtl8812au' > /etc/modules-load.d/rtl8812au.conf

15
backports/drivers/realtek/rtl8812au/contributors.sh Executable file
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@@ -0,0 +1,15 @@
#!/bin/bash
set -e
cd "$(dirname "$(readlink -f "$BASH_SOURCE")")"
# see also ".mailmap" for how email addresses and names are deduplicated
{
cat <<-'EOH'
## Contributors
<!-- DO NOT EDIT - CONTRIBUTORS.md is autogenerated from git commit log by contributors.sh script. -->
EOH
echo
git log --format='%aN <%aE>' | LC_ALL=C.UTF-8 sort -uf | cut -f1 -d'<' | sed 's/^/- /g' | sort | uniq
} > CONTRIBUTORS.md

758
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backports/drivers/realtek/rtl8812au/core/rtw_ap.c Executable file → Normal file
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1537
backports/drivers/realtek/rtl8812au/core/rtw_beamforming.c Executable file → Normal file
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backports/drivers/realtek/rtl8812au/core/rtw_br_ext.c Executable file → Normal file
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3389
backports/drivers/realtek/rtl8812au/core/rtw_bt_mp.c Executable file → Normal file
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1488
backports/drivers/realtek/rtl8812au/core/rtw_btcoex.c Executable file → Normal file
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2201
backports/drivers/realtek/rtl8812au/core/rtw_cmd.c Executable file → Normal file
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166
backports/drivers/realtek/rtl8812au/core/rtw_eeprom.c Executable file → Normal file
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@@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -25,30 +25,30 @@
void up_clk(_adapter* padapter, u16 *x)
{
_func_enter_;
_func_enter_;
*x = *x | _EESK;
rtw_write8(padapter, EE_9346CR, (u8)*x);
rtw_udelay_os(CLOCK_RATE);
_func_exit_;
_func_exit_;
}
void down_clk(_adapter * padapter, u16 *x )
{
_func_enter_;
_func_enter_;
*x = *x & ~_EESK;
rtw_write8(padapter, EE_9346CR, (u8)*x);
rtw_udelay_os(CLOCK_RATE);
_func_exit_;
_func_exit_;
}
void shift_out_bits(_adapter * padapter, u16 data, u16 count)
{
u16 x,mask;
_func_enter_;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
if(padapter->bSurpriseRemoved==_TRUE) {
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
@@ -57,14 +57,13 @@ _func_enter_;
x &= ~(_EEDO | _EEDI);
do
{
do {
x &= ~_EEDI;
if(data & mask)
x |= _EEDI;
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
if(padapter->bSurpriseRemoved==_TRUE) {
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
rtw_write8(padapter, EE_9346CR, (u8)x);
rtw_udelay_os(CLOCK_RATE);
@@ -72,21 +71,21 @@ _func_enter_;
down_clk(padapter, &x);
mask = mask >> 1;
} while(mask);
if(padapter->bSurpriseRemoved==_TRUE){
if(padapter->bSurpriseRemoved==_TRUE) {
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x &= ~_EEDI;
rtw_write8(padapter, EE_9346CR, (u8)x);
out:
_func_exit_;
out:
_func_exit_;
}
u16 shift_in_bits (_adapter * padapter)
{
u16 x,d=0,i;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE) {
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
@@ -95,24 +94,23 @@ _func_enter_;
x &= ~( _EEDO | _EEDI);
d = 0;
for(i=0; i<16; i++)
{
for(i=0; i<16; i++) {
d = d << 1;
up_clk(padapter, &x);
if(padapter->bSurpriseRemoved==_TRUE){
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
if(padapter->bSurpriseRemoved==_TRUE) {
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x = rtw_read8(padapter, EE_9346CR);
x &= ~(_EEDI);
if(x & _EEDO)
d |= 1;
d |= 1;
down_clk(padapter, &x);
}
out:
_func_exit_;
out:
_func_exit_;
return d;
}
@@ -120,7 +118,7 @@ _func_exit_;
void standby(_adapter * padapter )
{
u8 x;
_func_enter_;
_func_enter_;
x = rtw_read8(padapter, EE_9346CR);
x &= ~(_EECS | _EESK);
@@ -130,56 +128,55 @@ _func_enter_;
x |= _EECS;
rtw_write8(padapter, EE_9346CR, x);
rtw_udelay_os(CLOCK_RATE);
_func_exit_;
_func_exit_;
}
u16 wait_eeprom_cmd_done(_adapter* padapter)
{
u8 x;
u16 i,res=_FALSE;
_func_enter_;
_func_enter_;
standby(padapter );
for (i=0; i<200; i++)
{
for (i=0; i<200; i++) {
x = rtw_read8(padapter, EE_9346CR);
if (x & _EEDO){
if (x & _EEDO) {
res=_TRUE;
goto exit;
}
}
rtw_udelay_os(CLOCK_RATE);
}
exit:
_func_exit_;
exit:
_func_exit_;
return res;
}
void eeprom_clean(_adapter * padapter)
{
u16 x;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE) {
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x = rtw_read8(padapter, EE_9346CR);
if(padapter->bSurpriseRemoved==_TRUE){
if(padapter->bSurpriseRemoved==_TRUE) {
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x &= ~(_EECS | _EEDI);
rtw_write8(padapter, EE_9346CR, (u8)x);
if(padapter->bSurpriseRemoved==_TRUE){
if(padapter->bSurpriseRemoved==_TRUE) {
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
up_clk(padapter, &x);
if(padapter->bSurpriseRemoved==_TRUE){
if(padapter->bSurpriseRemoved==_TRUE) {
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
down_clk(padapter, &x);
out:
_func_exit_;
out:
_func_exit_;
}
void eeprom_write16(_adapter * padapter, u16 reg, u16 data)
@@ -189,19 +186,19 @@ void eeprom_write16(_adapter * padapter, u16 reg, u16 data)
u8 tmp8_ori,tmp8_new,tmp8_clk_ori,tmp8_clk_new;
tmp8_ori=rtw_read8(padapter, 0x102502f1);
tmp8_new=tmp8_ori & 0xf7;
if(tmp8_ori != tmp8_new){
if(tmp8_ori != tmp8_new) {
rtw_write8(padapter, 0x102502f1, tmp8_new);
RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x102502f1=====\n"));
}
tmp8_clk_ori=rtw_read8(padapter,0x10250003);
tmp8_clk_new=tmp8_clk_ori|0x20;
if(tmp8_clk_new!=tmp8_clk_ori){
if(tmp8_clk_new!=tmp8_clk_ori) {
RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n"));
rtw_write8(padapter, 0x10250003, tmp8_clk_new);
}
}
#endif
_func_enter_;
_func_enter_;
x = rtw_read8(padapter, EE_9346CR);
x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
@@ -209,12 +206,12 @@ _func_enter_;
rtw_write8(padapter, EE_9346CR, x);
shift_out_bits(padapter, EEPROM_EWEN_OPCODE, 5);
if(padapter->EepromAddressSize==8) //CF+ and SDIO
shift_out_bits(padapter, 0, 6);
else //USB
shift_out_bits(padapter, 0, 4);
standby( padapter);
// Commented out by rcnjko, 2004.0
@@ -223,7 +220,7 @@ _func_enter_;
// shift_out_bits(Adapter, EEPROM_ERASE_OPCODE, 3);
// shift_out_bits(Adapter, reg, Adapter->EepromAddressSize);
//
// if (wait_eeprom_cmd_done(Adapter ) == FALSE)
// if (wait_eeprom_cmd_done(Adapter ) == FALSE)
// {
// return;
// }
@@ -242,8 +239,7 @@ _func_enter_;
// write the data to the selected EEPROM word.
shift_out_bits(padapter, data, 16);
if (wait_eeprom_cmd_done(padapter ) == _FALSE)
{
if (wait_eeprom_cmd_done(padapter ) == _FALSE) {
goto exit;
}
@@ -254,7 +250,7 @@ _func_enter_;
shift_out_bits(padapter, reg, 4);
eeprom_clean(padapter );
exit:
exit:
#ifdef CONFIG_RTL8712
if(tmp8_clk_new!=tmp8_clk_ori)
rtw_write8(padapter, 0x10250003, tmp8_clk_ori);
@@ -262,11 +258,11 @@ exit:
rtw_write8(padapter, 0x102502f1, tmp8_ori);
#endif
_func_exit_;
_func_exit_;
return;
}
u16 eeprom_read16(_adapter * padapter, u16 reg) //ReadEEprom
u16 eeprom_read16(_adapter * padapter, u16 reg) //ReadEEprom
{
u16 x;
@@ -275,27 +271,27 @@ u16 eeprom_read16(_adapter * padapter, u16 reg) //ReadEEprom
u8 tmp8_ori,tmp8_new,tmp8_clk_ori,tmp8_clk_new;
tmp8_ori= rtw_read8(padapter, 0x102502f1);
tmp8_new = tmp8_ori & 0xf7;
if(tmp8_ori != tmp8_new){
if(tmp8_ori != tmp8_new) {
rtw_write8(padapter, 0x102502f1, tmp8_new);
RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x102502f1=====\n"));
}
tmp8_clk_ori=rtw_read8(padapter,0x10250003);
tmp8_clk_new=tmp8_clk_ori|0x20;
if(tmp8_clk_new!=tmp8_clk_ori){
if(tmp8_clk_new!=tmp8_clk_ori) {
RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n"));
rtw_write8(padapter, 0x10250003, tmp8_clk_new);
}
}
#endif
_func_enter_;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
if(padapter->bSurpriseRemoved==_TRUE) {
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
// select EEPROM, reset bits, set _EECS
x = rtw_read8(padapter, EE_9346CR);
if(padapter->bSurpriseRemoved==_TRUE){
if(padapter->bSurpriseRemoved==_TRUE) {
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
@@ -313,7 +309,7 @@ _func_enter_;
data = shift_in_bits(padapter);
eeprom_clean(padapter);
out:
out:
#ifdef CONFIG_RTL8712
if(tmp8_clk_new!=tmp8_clk_ori)
rtw_write8(padapter, 0x10250003, tmp8_clk_ori);
@@ -321,7 +317,7 @@ out:
rtw_write8(padapter, 0x102502f1, tmp8_ori);
#endif
_func_exit_;
_func_exit_;
return data;
@@ -331,20 +327,20 @@ _func_exit_;
//From even offset
void eeprom_read_sz(_adapter * padapter, u16 reg, u8* data, u32 sz)
void eeprom_read_sz(_adapter * padapter, u16 reg, u8* data, u32 sz)
{
u16 x, data16;
u32 i;
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE){
_func_enter_;
if(padapter->bSurpriseRemoved==_TRUE) {
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
// select EEPROM, reset bits, set _EECS
x = rtw_read8(padapter, EE_9346CR);
if(padapter->bSurpriseRemoved==_TRUE){
if(padapter->bSurpriseRemoved==_TRUE) {
RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
@@ -359,16 +355,15 @@ _func_enter_;
shift_out_bits(padapter, reg, padapter->EepromAddressSize);
for(i=0; i<sz; i+=2)
{
for(i=0; i<sz; i+=2) {
data16 = shift_in_bits(padapter);
data[i] = data16 & 0xff;
data[i+1] = data16 >>8;
data[i+1] = data16 >>8;
}
eeprom_clean(padapter);
out:
_func_exit_;
out:
_func_exit_;
@@ -380,33 +375,32 @@ u8 eeprom_read(_adapter * padapter, u32 addr_off, u8 sz, u8* rbuf)
{
u8 quotient, remainder, addr_2align_odd;
u16 reg, stmp , i=0, idx = 0;
_func_enter_;
_func_enter_;
reg = (u16)(addr_off >> 1);
addr_2align_odd = (u8)(addr_off & 0x1);
if(addr_2align_odd) //read that start at high part: e.g 1,3,5,7,9,...
{
if(addr_2align_odd) { //read that start at high part: e.g 1,3,5,7,9,...
stmp = eeprom_read16(padapter, reg);
rbuf[idx++] = (u8) ((stmp>>8)&0xff); //return hogh-part of the short
reg++; sz--;
reg++;
sz--;
}
quotient = sz >> 1;
remainder = sz & 0x1;
for( i=0 ; i < quotient; i++)
{
for( i=0 ; i < quotient; i++) {
stmp = eeprom_read16(padapter, reg+i);
rbuf[idx++] = (u8) (stmp&0xff);
rbuf[idx++] = (u8) ((stmp>>8)&0xff);
}
reg = reg+i;
if(remainder){ //end of read at lower part of short : 0,2,4,6,...
if(remainder) { //end of read at lower part of short : 0,2,4,6,...
stmp = eeprom_read16(padapter, reg);
rbuf[idx] = (u8)(stmp & 0xff);
rbuf[idx] = (u8)(stmp & 0xff);
}
_func_exit_;
_func_exit_;
return _TRUE;
}
@@ -415,9 +409,9 @@ _func_exit_;
VOID read_eeprom_content(_adapter * padapter)
{
_func_enter_;
_func_enter_;
_func_exit_;
_func_exit_;
}

1124
backports/drivers/realtek/rtl8812au/core/rtw_ieee80211.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

56
backports/drivers/realtek/rtl8812au/core/rtw_io.c Executable file → Normal file
View File

@@ -126,7 +126,7 @@ int _rtw_write8(_adapter *adapter, u32 addr, u8 val)
ret = _write8(pintfhdl, addr, val);
_func_exit_;
return RTW_STATUS_CODE(ret);
}
int _rtw_write16(_adapter *adapter, u32 addr, u16 val)
@@ -154,7 +154,7 @@ int _rtw_write32(_adapter *adapter, u32 addr, u32 val)
int ret;
_func_enter_;
_write32 = pintfhdl->io_ops._write32;
val = rtw_cpu_to_le32(val);
ret = _write32(pintfhdl, addr, val);
_func_exit_;
@@ -166,7 +166,7 @@ int _rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *pdata)
{
//struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue;
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = (struct intf_hdl*)(&(pio_priv->intf));
struct intf_hdl *pintfhdl = (struct intf_hdl*)(&(pio_priv->intf));
int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr,u32 length, u8 *pdata);
int ret;
_func_enter_;
@@ -254,10 +254,9 @@ void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
_func_enter_;
if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE))
{
RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_mem:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));
return;
if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE)) {
RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_mem:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));
return;
}
_read_mem = pintfhdl->io_ops._read_mem;
@@ -294,10 +293,9 @@ void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
_func_enter_;
if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE))
{
RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_port:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));
return;
if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE)) {
RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_port:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved));
return;
}
_read_port = pintfhdl->io_ops._read_port;
@@ -316,9 +314,10 @@ void _rtw_read_port_cancel(_adapter *adapter)
_read_port_cancel = pintfhdl->io_ops._read_port_cancel;
RTW_DISABLE_FUNC(adapter, DF_RX_BIT);
if(_read_port_cancel)
_read_port_cancel(pintfhdl);
}
u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
@@ -332,10 +331,10 @@ u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
_func_enter_;
_write_port = pintfhdl->io_ops._write_port;
ret = _write_port(pintfhdl, addr, cnt, pmem);
_func_exit_;
_func_exit_;
return ret;
}
@@ -354,7 +353,7 @@ u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int
if (ret == _SUCCESS)
ret = rtw_sctx_wait(&sctx, __func__);
return ret;
return ret;
}
void _rtw_write_port_cancel(_adapter *adapter)
@@ -365,9 +364,10 @@ void _rtw_write_port_cancel(_adapter *adapter)
_write_port_cancel = pintfhdl->io_ops._write_port_cancel;
RTW_DISABLE_FUNC(adapter, DF_TX_BIT);
if(_write_port_cancel)
_write_port_cancel(pintfhdl);
}
int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter,struct _io_ops *pops))
{
@@ -380,8 +380,8 @@ int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter
piopriv->padapter = padapter;
pintf->padapter = padapter;
pintf->pintf_dev = adapter_to_dvobj(padapter);
set_intf_ops(padapter,&pintf->io_ops);
set_intf_ops(padapter,&pintf->io_ops);
return _SUCCESS;
}
@@ -409,19 +409,19 @@ int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj)
*/
void rtw_reset_continual_io_error(struct dvobj_priv *dvobj)
{
ATOMIC_SET(&dvobj->continual_io_error, 0);
ATOMIC_SET(&dvobj->continual_io_error, 0);
}
#ifdef DBG_IO
u16 read_sniff_ranges[][2] = {
//{0x520, 0x523},
};
};
u16 write_sniff_ranges[][2] = {
//{0x520, 0x523},
//{0x4c, 0x4c},
};
};
int read_sniff_num = sizeof(read_sniff_ranges)/sizeof(u16)/2;
int write_sniff_num = sizeof(write_sniff_ranges)/sizeof(u16)/2;
@@ -433,7 +433,7 @@ bool match_read_sniff_ranges(u16 addr, u16 len)
if (addr + len > read_sniff_ranges[i][0] && addr <= read_sniff_ranges[i][1])
return _TRUE;
}
return _FALSE;
}
@@ -444,7 +444,7 @@ bool match_write_sniff_ranges(u16 addr, u16 len)
if (addr + len > write_sniff_ranges[i][0] && addr <= write_sniff_ranges[i][1])
return _TRUE;
}
return _FALSE;
}
@@ -461,7 +461,7 @@ u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line
u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u16 val = _rtw_read16(adapter, addr);
if (match_read_sniff_ranges(addr, 2))
DBG_871X("DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x\n", caller, line, addr, val);
@@ -471,7 +471,7 @@ u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int li
u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line)
{
u32 val = _rtw_read32(adapter, addr);
if (match_read_sniff_ranges(addr, 4))
DBG_871X("DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x\n", caller, line, addr, val);
@@ -482,21 +482,21 @@ int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, cons
{
if (match_write_sniff_ranges(addr, 1))
DBG_871X("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x)\n", caller, line, addr, val);
return _rtw_write8(adapter, addr, val);
}
int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 2))
DBG_871X("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x)\n", caller, line, addr, val);
return _rtw_write16(adapter, addr, val);
}
int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line)
{
if (match_write_sniff_ranges(addr, 4))
DBG_871X("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x)\n", caller, line, addr, val);
return _rtw_write32(adapter, addr, val);
}
int dbg_rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line)

177
backports/drivers/realtek/rtl8812au/core/rtw_ioctl_query.c Executable file → Normal file
View File

@@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -28,28 +28,27 @@
//
u8
query_802_11_capability(
_adapter* Adapter,
u8* pucBuf,
u32 * pulOutLen
_adapter* Adapter,
u8* pucBuf,
u32 * pulOutLen
)
{
static NDIS_802_11_AUTHENTICATION_ENCRYPTION szAuthEnc[] =
{
{Ndis802_11AuthModeOpen, Ndis802_11EncryptionDisabled},
static NDIS_802_11_AUTHENTICATION_ENCRYPTION szAuthEnc[] = {
{Ndis802_11AuthModeOpen, Ndis802_11EncryptionDisabled},
{Ndis802_11AuthModeOpen, Ndis802_11Encryption1Enabled},
{Ndis802_11AuthModeShared, Ndis802_11EncryptionDisabled},
{Ndis802_11AuthModeShared, Ndis802_11EncryptionDisabled},
{Ndis802_11AuthModeShared, Ndis802_11Encryption1Enabled},
{Ndis802_11AuthModeWPA, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPA, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPA, Ndis802_11Encryption3Enabled},
{Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption3Enabled},
{Ndis802_11AuthModeWPANone, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPANone, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPANone, Ndis802_11Encryption3Enabled},
{Ndis802_11AuthModeWPA2, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPA2, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPA2, Ndis802_11Encryption3Enabled},
{Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption2Enabled},
{Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption3Enabled}
};
};
static ULONG ulNumOfPairSupported = sizeof(szAuthEnc)/sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION);
NDIS_802_11_CAPABILITY * pCap = (NDIS_802_11_CAPABILITY *)pucBuf;
u8* pucAuthEncryptionSupported = (u8*) pCap->AuthenticationEncryptionSupported;
@@ -58,19 +57,16 @@ query_802_11_capability(
pCap->Length = sizeof(NDIS_802_11_CAPABILITY);
if(ulNumOfPairSupported > 1 )
pCap->Length += (ulNumOfPairSupported-1) * sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION);
pCap->Version = 2;
pCap->NoOfPMKIDs = NUM_PMKID_CACHE;
pCap->Version = 2;
pCap->NoOfPMKIDs = NUM_PMKID_CACHE;
pCap->NoOfAuthEncryptPairsSupported = ulNumOfPairSupported;
if( sizeof (szAuthEnc) <= 240 ) // 240 = 256 - 4*4 // SecurityInfo.szCapability: only 256 bytes in size.
{
if( sizeof (szAuthEnc) <= 240 ) { // 240 = 256 - 4*4 // SecurityInfo.szCapability: only 256 bytes in size.
_rtw_memcpy( pucAuthEncryptionSupported, (u8*)szAuthEnc, sizeof (szAuthEnc) );
*pulOutLen = pCap->Length;
return _TRUE;
}
else
{
} else {
*pulOutLen = 0;
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("_query_802_11_capability(): szAuthEnc size is too large.\n"));
return _FALSE;
@@ -82,7 +78,7 @@ u8 query_802_11_association_information( _adapter *padapter,PNDIS_802_11_ASSOCIA
struct wlan_network *tgt_network;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct security_priv *psecuritypriv=&(padapter->securitypriv);
WLAN_BSSID_EX *psecnetwork=(WLAN_BSSID_EX*)&(psecuritypriv->sec_bss);
WLAN_BSSID_EX *psecnetwork=(WLAN_BSSID_EX*)&(psecuritypriv->sec_bss);
u8 * pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
unsigned char i,*auth_ie,*supp_ie;
@@ -94,97 +90,94 @@ u8 query_802_11_association_information( _adapter *padapter,PNDIS_802_11_ASSOCIA
// Association Request related information
//------------------------------------------------------
// Req_1. AvailableRequestFixedIEs
if(psecnetwork!=NULL){
pAssocInfo->AvailableRequestFixedIEs |= NDIS_802_11_AI_REQFI_CAPABILITIES|NDIS_802_11_AI_REQFI_CURRENTAPADDRESS;
pAssocInfo->RequestFixedIEs.Capabilities = (unsigned short)* & psecnetwork->IEs[10];
_rtw_memcpy(pAssocInfo->RequestFixedIEs.CurrentAPAddress,
& psecnetwork->MacAddress, 6);
if(psecnetwork!=NULL) {
pAssocInfo->OffsetRequestIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
pAssocInfo->AvailableRequestFixedIEs |= NDIS_802_11_AI_REQFI_CAPABILITIES|NDIS_802_11_AI_REQFI_CURRENTAPADDRESS;
pAssocInfo->RequestFixedIEs.Capabilities = (unsigned short)* & psecnetwork->IEs[10];
_rtw_memcpy(pAssocInfo->RequestFixedIEs.CurrentAPAddress,
& psecnetwork->MacAddress, 6);
if(check_fwstate( pmlmepriv, _FW_UNDER_LINKING|_FW_LINKED)==_TRUE)
{
if(psecuritypriv->ndisauthtype>=Ndis802_11AuthModeWPA2)
pDest[0] =48; //RSN Information Element
else
pDest[0] =221; //WPA(SSN) Information Element
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n Adapter->ndisauthtype==Ndis802_11AuthModeWPA)?0xdd:0x30 [%d]",pDest[0]));
supp_ie=&psecuritypriv->supplicant_ie[0];
for(i=0;i<supp_ie[0];i++)
{
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("IEs [%d] = 0x%x \n\n", i,supp_ie[i]));
}
pAssocInfo->OffsetRequestIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION);
i=13; //0~11 is fixed information element
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("i= %d tgt_network->network.IELength=%d\n\n", i,(int)psecnetwork->IELength));
while((i<supp_ie[0]) && (i<256)){
if((unsigned char)supp_ie[i]==pDest[0]){
_rtw_memcpy((u8 *)(pDest),
&supp_ie[i],
supp_ie[1+i]+2);
break;
if(check_fwstate( pmlmepriv, _FW_UNDER_LINKING|_FW_LINKED)==_TRUE) {
if(psecuritypriv->ndisauthtype>=Ndis802_11AuthModeWPA2)
pDest[0] =48; //RSN Information Element
else
pDest[0] =221; //WPA(SSN) Information Element
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n Adapter->ndisauthtype==Ndis802_11AuthModeWPA)?0xdd:0x30 [%d]",pDest[0]));
supp_ie=&psecuritypriv->supplicant_ie[0];
for(i=0; i<supp_ie[0]; i++) {
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("IEs [%d] = 0x%x \n\n", i,supp_ie[i]));
}
i=i+supp_ie[i+1]+2;
if(supp_ie[1+i]==0)
i=i+1;
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("iteration i=%d IEs [%d] = 0x%x \n\n", i,i,supp_ie[i+1]));
i=13; //0~11 is fixed information element
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("i= %d tgt_network->network.IELength=%d\n\n", i,(int)psecnetwork->IELength));
while((i<supp_ie[0]) && (i<256)) {
if((unsigned char)supp_ie[i]==pDest[0]) {
_rtw_memcpy((u8 *)(pDest),
&supp_ie[i],
supp_ie[1+i]+2);
break;
}
i=i+supp_ie[i+1]+2;
if(supp_ie[1+i]==0)
i=i+1;
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("iteration i=%d IEs [%d] = 0x%x \n\n", i,i,supp_ie[i+1]));
}
pAssocInfo->RequestIELength += (2 + supp_ie[1+i]);// (2 + psecnetwork->IEs[1+i]+4);
}
pAssocInfo->RequestIELength += (2 + supp_ie[1+i]);// (2 + psecnetwork->IEs[1+i]+4);
}
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n psecnetwork != NULL,fwstate==_FW_UNDER_LINKING \n"));
}
//------------------------------------------------------
// Association Response related information
//------------------------------------------------------
if(check_fwstate( pmlmepriv, _FW_LINKED)==_TRUE)
{
if(check_fwstate( pmlmepriv, _FW_LINKED)==_TRUE) {
tgt_network =&(pmlmepriv->cur_network);
if(tgt_network!=NULL){
pAssocInfo->AvailableResponseFixedIEs =
NDIS_802_11_AI_RESFI_CAPABILITIES
|NDIS_802_11_AI_RESFI_ASSOCIATIONID
;
if(tgt_network!=NULL) {
pAssocInfo->AvailableResponseFixedIEs =
NDIS_802_11_AI_RESFI_CAPABILITIES
|NDIS_802_11_AI_RESFI_ASSOCIATIONID
;
pAssocInfo->ResponseFixedIEs.Capabilities =(unsigned short)* & tgt_network->network.IEs[10];
pAssocInfo->ResponseFixedIEs.StatusCode = 0;
pAssocInfo->ResponseFixedIEs.AssociationId =(unsigned short) tgt_network->aid;
pAssocInfo->ResponseFixedIEs.Capabilities =(unsigned short)* & tgt_network->network.IEs[10];
pAssocInfo->ResponseFixedIEs.StatusCode = 0;
pAssocInfo->ResponseFixedIEs.AssociationId =(unsigned short) tgt_network->aid;
pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)+pAssocInfo->RequestIELength;
auth_ie=&psecuritypriv->authenticator_ie[0];
pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)+pAssocInfo->RequestIELength;
auth_ie=&psecuritypriv->authenticator_ie[0];
for(i=0;i<auth_ie[0];i++)
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("IEs [%d] = 0x%x \n\n", i,auth_ie[i]));
for(i=0; i<auth_ie[0]; i++)
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("IEs [%d] = 0x%x \n\n", i,auth_ie[i]));
i=auth_ie[0]-12;
if(i>0){
_rtw_memcpy((u8 *)&pDest[0],&auth_ie[1],i);
pAssocInfo->ResponseIELength =i;
i=auth_ie[0]-12;
if(i>0) {
_rtw_memcpy((u8 *)&pDest[0],&auth_ie[1],i);
pAssocInfo->ResponseIELength =i;
}
pAssocInfo->OffsetResponseIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION) + pAssocInfo->RequestIELength;
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n tgt_network != NULL,fwstate==_FW_LINKED \n"));
}
pAssocInfo->OffsetResponseIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION) + pAssocInfo->RequestIELength;
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n tgt_network != NULL,fwstate==_FW_LINKED \n"));
}
}
}
RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n exit query_802_11_association_information \n"));
_func_exit_;
_func_exit_;
return _TRUE;
}

466
backports/drivers/realtek/rtl8812au/core/rtw_ioctl_rtl.c Executable file → Normal file
View File

@@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -25,8 +25,7 @@
#include <rtw_mp_ioctl.h>
#endif
struct oid_obj_priv oid_rtl_seg_01_01[] =
{
struct oid_obj_priv oid_rtl_seg_01_01[] = {
{1, &oid_null_function}, //0x80
{1, &oid_null_function}, //0x81
{1, &oid_null_function}, //0x82
@@ -52,7 +51,7 @@ struct oid_obj_priv oid_rtl_seg_01_01[] =
{1, &oid_rt_get_preamble_mode_hdl}, //0x96
{1, &oid_null_function}, //0x97
{1, &oid_rt_get_ap_ip_hdl}, //0x98
{1, &oid_rt_get_channelplan_hdl}, //0x99
{1, &oid_rt_get_channelplan_hdl}, //0x99
{1, &oid_rt_set_preamble_mode_hdl}, //0x9A
{1, &oid_rt_set_bcn_intvl_hdl}, //0x9B
{1, &oid_null_function}, //0x9C
@@ -68,7 +67,7 @@ struct oid_obj_priv oid_rtl_seg_01_01[] =
{1, &oid_null_function}, //0xA6
{1, &oid_rt_get_total_tx_bytes_hdl}, //0xA7
{1, &oid_rt_get_total_rx_bytes_hdl}, //0xA8
{1, &oid_rt_current_tx_power_level_hdl}, //0xA9
{1, &oid_rt_current_tx_power_level_hdl}, //0xA9
{1, &oid_rt_get_enc_key_mismatch_count_hdl}, //0xAA
{1, &oid_rt_get_enc_key_match_count_hdl}, //0xAB
{1, &oid_rt_get_channel_hdl}, //0xAC
@@ -84,7 +83,7 @@ struct oid_obj_priv oid_rtl_seg_01_01[] =
{1, &oid_null_function}, //0xB6
{1, &oid_null_function}, //0xB7
{1, &oid_null_function}, //0xB8
{1, &oid_null_function}, //0xB9
{1, &oid_null_function}, //0xB9
{1, &oid_null_function}, //0xBA
{1, &oid_rt_supported_wireless_mode_hdl}, //0xBB
{1, &oid_rt_get_channel_list_hdl}, //0xBC
@@ -100,18 +99,17 @@ struct oid_obj_priv oid_rtl_seg_01_01[] =
{1, &oid_null_function}, //0xC6
{1, &oid_null_function}, //0xC7
{1, &oid_null_function}, //0xC8
{1, &oid_null_function}, //0xC9
{1, &oid_null_function}, //0xC9
{1, &oid_null_function}, //0xCA
{1, &oid_null_function}, //0xCB
{1, &oid_null_function}, //0xCC
{1, &oid_null_function}, //0xCD
{1, &oid_null_function}, //0xCE
{1, &oid_null_function}, //0xCF
};
struct oid_obj_priv oid_rtl_seg_01_03[] =
{
struct oid_obj_priv oid_rtl_seg_01_03[] = {
{1, &oid_rt_ap_get_associated_station_list_hdl}, //0x00
{1, &oid_null_function}, //0x01
{1, &oid_rt_ap_switch_into_ap_mode_hdl}, //0x02
@@ -121,9 +119,8 @@ struct oid_obj_priv oid_rtl_seg_01_03[] =
};
struct oid_obj_priv oid_rtl_seg_01_11[] =
{
{1, &oid_null_function}, //0xC0 OID_RT_PRO_RX_FILTER
struct oid_obj_priv oid_rtl_seg_01_11[] = {
{1, &oid_null_function}, //0xC0 OID_RT_PRO_RX_FILTER
{1, &oid_null_function}, //0xC1 OID_CE_USB_WRITE_REGISTRY
{1, &oid_null_function}, //0xC2 OID_CE_USB_READ_REGISTRY
{1, &oid_null_function}, //0xC3 OID_RT_PRO_SET_INITIAL_GAIN
@@ -131,25 +128,24 @@ struct oid_obj_priv oid_rtl_seg_01_11[] =
{1, &oid_null_function}, //0xC5 OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE
{1, &oid_null_function}, //0xC6 OID_RT_PRO_SET_TX_CHARGE_PUMP
{1, &oid_null_function}, //0xC7 OID_RT_PRO_SET_RX_CHARGE_PUMP
{1, &oid_rt_pro_rf_write_registry_hdl}, //0xC8
{1, &oid_rt_pro_rf_read_registry_hdl}, //0xC9
{1, &oid_rt_pro_rf_write_registry_hdl}, //0xC8
{1, &oid_rt_pro_rf_read_registry_hdl}, //0xC9
{1, &oid_null_function} //0xCA OID_RT_PRO_QUERY_RF_TYPE
};
struct oid_obj_priv oid_rtl_seg_03_00[] =
{
struct oid_obj_priv oid_rtl_seg_03_00[] = {
{1, &oid_null_function}, //0x00
{1, &oid_rt_get_connect_state_hdl}, //0x01
{1, &oid_null_function}, //0x02
{1, &oid_null_function}, //0x03
{1, &oid_rt_set_default_key_id_hdl}, //0x04
};
//************** oid_rtl_seg_01_01 section start **************
//************** oid_rtl_seg_01_01 section start **************
NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv* poid_par_priv)
{
@@ -157,28 +153,24 @@ NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv* poid_par_priv)
#if 0
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
_irqL oldirql;
_func_enter_;
if(poid_par_priv->type_of_oid != SET_OID)
{
if(poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
_irqlevel_changed_(&oldirql,LOWER);
if(poid_par_priv->information_buf_len >= sizeof(struct setdig_parm))
{
//DEBUG_ERR(("===> oid_rt_pro_set_fw_dig_state_hdl. type:0x%02x.\n",*((unsigned char*)poid_par_priv->information_buf )));
if(!rtw_setfwdig_cmd(Adapter,*((unsigned char*)poid_par_priv->information_buf )))
{
if(poid_par_priv->information_buf_len >= sizeof(struct setdig_parm)) {
//DEBUG_ERR(("===> oid_rt_pro_set_fw_dig_state_hdl. type:0x%02x.\n",*((unsigned char*)poid_par_priv->information_buf )));
if(!rtw_setfwdig_cmd(Adapter,*((unsigned char*)poid_par_priv->information_buf ))) {
status = NDIS_STATUS_NOT_ACCEPTED;
}
}
else{
} else {
status = NDIS_STATUS_NOT_ACCEPTED;
}
}
_irqlevel_changed_(&oldirql,RAISE);
_func_exit_;
#endif
@@ -192,29 +184,25 @@ NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv* poid_par_priv)
#if 0
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
_irqL oldirql;
_func_enter_;
if(poid_par_priv->type_of_oid != SET_OID)
{
_func_enter_;
if(poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
_irqlevel_changed_(&oldirql,LOWER);
if(poid_par_priv->information_buf_len >= sizeof(struct setra_parm))
{
//DEBUG_ERR(("===> oid_rt_pro_set_fw_ra_state_hdl. type:0x%02x.\n",*((unsigned char*)poid_par_priv->information_buf )));
if(!rtw_setfwra_cmd(Adapter,*((unsigned char*)poid_par_priv->information_buf )))
{
if(poid_par_priv->information_buf_len >= sizeof(struct setra_parm)) {
//DEBUG_ERR(("===> oid_rt_pro_set_fw_ra_state_hdl. type:0x%02x.\n",*((unsigned char*)poid_par_priv->information_buf )));
if(!rtw_setfwra_cmd(Adapter,*((unsigned char*)poid_par_priv->information_buf ))) {
status = NDIS_STATUS_NOT_ACCEPTED;
}
}
else{
} else {
status = NDIS_STATUS_NOT_ACCEPTED;
}
}
_irqlevel_changed_(&oldirql,RAISE);
_func_exit_;
#endif
@@ -227,23 +215,19 @@ NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv* poid_par_priv)
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
//DEBUG_ERR(("<**********************oid_rt_get_signal_quality_hdl \n"));
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
#if 0
if(pMgntInfo->mAssoc || pMgntInfo->mIbss)
{
ulInfo = pAdapter->RxStats.SignalQuality;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
}
else
{
ulInfo = 0xffffffff; // It stands for -1 in 4-byte integer.
}
break;
if(pMgntInfo->mAssoc || pMgntInfo->mIbss) {
ulInfo = pAdapter->RxStats.SignalQuality;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
} else {
ulInfo = 0xffffffff; // It stands for -1 in 4-byte integer.
}
break;
#endif
return status;
@@ -256,19 +240,15 @@ NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
if(poid_par_priv->information_buf_len >= sizeof(ULONG) )
{
*(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_smallpacket_crcerr;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
}
else
{
if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) {
*(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_smallpacket_crcerr;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
} else {
status = NDIS_STATUS_INVALID_LENGTH;
}
@@ -280,19 +260,15 @@ NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
if(poid_par_priv->information_buf_len >= sizeof(ULONG) )
{
*(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_middlepacket_crcerr;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
}
else
{
if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) {
*(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_middlepacket_crcerr;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
} else {
status = NDIS_STATUS_INVALID_LENGTH;
}
@@ -305,19 +281,15 @@ NDIS_STATUS oid_rt_get_large_packet_crc_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
if(poid_par_priv->information_buf_len >= sizeof(ULONG) )
{
*(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_largepacket_crcerr;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
}
else
{
if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) {
*(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_largepacket_crcerr;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
} else {
status = NDIS_STATUS_INVALID_LENGTH;
}
@@ -331,11 +303,10 @@ NDIS_STATUS oid_rt_get_tx_retry_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
return status;
}
@@ -344,11 +315,10 @@ NDIS_STATUS oid_rt_get_rx_retry_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
return status;
}
@@ -358,18 +328,14 @@ NDIS_STATUS oid_rt_get_rx_total_packet_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
if(poid_par_priv->information_buf_len >= sizeof(ULONG) )
{
*(u64 *)poid_par_priv->information_buf = padapter->recvpriv.rx_pkts + padapter->recvpriv.rx_drop;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
}
else
{
if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) {
*(u64 *)poid_par_priv->information_buf = padapter->recvpriv.rx_pkts + padapter->recvpriv.rx_drop;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
} else {
status = NDIS_STATUS_INVALID_LENGTH;
}
@@ -382,11 +348,10 @@ NDIS_STATUS oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
return status;
}
@@ -395,11 +360,10 @@ NDIS_STATUS oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
return status;
}
@@ -409,22 +373,18 @@ NDIS_STATUS oid_rt_get_rx_icv_err_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
if(poid_par_priv->information_buf_len>= sizeof(u32))
{
if(poid_par_priv->information_buf_len>= sizeof(u32)) {
//_rtw_memcpy(*(uint *)poid_par_priv->information_buf,padapter->recvpriv.rx_icv_err,sizeof(u32));
*(uint *)poid_par_priv->information_buf = padapter->recvpriv.rx_icv_err;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
}
else
{
} else {
status = NDIS_STATUS_INVALID_LENGTH ;
}
return status;
}
@@ -434,11 +394,10 @@ NDIS_STATUS oid_rt_set_encryption_algorithm_hdl(struct oid_par_priv* poid_par_pr
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != SET_OID)
{
if(poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
return status;
}
@@ -447,28 +406,24 @@ NDIS_STATUS oid_rt_get_preamble_mode_hdl(struct oid_par_priv* poid_par_priv)
{
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
ULONG preamblemode = 0 ;
if(poid_par_priv->type_of_oid != QUERY_OID)
{
ULONG preamblemode = 0 ;
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
if(poid_par_priv->information_buf_len>= sizeof(ULONG))
{
}
if(poid_par_priv->information_buf_len>= sizeof(ULONG)) {
if(padapter->registrypriv.preamble == PREAMBLE_LONG)
preamblemode = 0;
else if (padapter->registrypriv.preamble == PREAMBLE_AUTO)
preamblemode = 1;
else if (padapter->registrypriv.preamble == PREAMBLE_SHORT)
preamblemode = 2;
*(ULONG *)poid_par_priv->information_buf = preamblemode ;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
}
else
{
} else {
status = NDIS_STATUS_INVALID_LENGTH ;
}
return status;
@@ -479,11 +434,10 @@ NDIS_STATUS oid_rt_get_ap_ip_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
return status;
}
@@ -492,13 +446,12 @@ NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv* poid_par_priv)
{
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
struct eeprom_priv* peeprompriv = &padapter->eeprompriv;
struct eeprom_priv* peeprompriv = &padapter->eeprompriv;
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
*(u16 *)poid_par_priv->information_buf = peeprompriv->channel_plan ;
@@ -508,14 +461,13 @@ NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv* poid_par_priv)
{
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
struct eeprom_priv* peeprompriv = &padapter->eeprompriv;
if(poid_par_priv->type_of_oid != SET_OID)
{
struct eeprom_priv* peeprompriv = &padapter->eeprompriv;
if(poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
peeprompriv->channel_plan = *(u16 *)poid_par_priv->information_buf ;
return status;
@@ -526,29 +478,25 @@ NDIS_STATUS oid_rt_set_preamble_mode_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
ULONG preamblemode = 0;
if(poid_par_priv->type_of_oid != SET_OID)
{
if(poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
if(poid_par_priv->information_buf_len>= sizeof(ULONG))
{
if(poid_par_priv->information_buf_len>= sizeof(ULONG)) {
preamblemode = *(ULONG *)poid_par_priv->information_buf ;
if( preamblemode == 0)
padapter->registrypriv.preamble = PREAMBLE_LONG;
else if (preamblemode==1 )
padapter->registrypriv.preamble = PREAMBLE_AUTO;
else if ( preamblemode==2 )
padapter->registrypriv.preamble = PREAMBLE_SHORT;
padapter->registrypriv.preamble = PREAMBLE_SHORT;
*(ULONG *)poid_par_priv->information_buf = preamblemode ;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
}
else
{
} else {
status = NDIS_STATUS_INVALID_LENGTH ;
}
}
return status;
}
@@ -558,8 +506,7 @@ NDIS_STATUS oid_rt_set_bcn_intvl_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != SET_OID)
{
if(poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
@@ -579,21 +526,17 @@ NDIS_STATUS oid_rt_get_total_tx_bytes_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
if(poid_par_priv->information_buf_len>= sizeof(ULONG))
{
}
if(poid_par_priv->information_buf_len>= sizeof(ULONG)) {
*(u64 *)poid_par_priv->information_buf = padapter->xmitpriv.tx_bytes;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
}
else
{
} else {
status = NDIS_STATUS_INVALID_LENGTH ;
}
return status;
}
@@ -603,19 +546,15 @@ NDIS_STATUS oid_rt_get_total_rx_bytes_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
if(poid_par_priv->information_buf_len>= sizeof(ULONG))
{
if(poid_par_priv->information_buf_len>= sizeof(ULONG)) {
//_rtw_memcpy(*(uint *)poid_par_priv->information_buf,padapter->recvpriv.rx_icv_err,sizeof(u32));
*(u64 *)poid_par_priv->information_buf = padapter->recvpriv.rx_bytes;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
}
else
{
} else {
status = NDIS_STATUS_INVALID_LENGTH ;
}
return status;
@@ -633,11 +572,10 @@ NDIS_STATUS oid_rt_get_enc_key_mismatch_count_hdl(struct oid_par_priv* poid_par_
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
return status;
}
@@ -646,11 +584,10 @@ NDIS_STATUS oid_rt_get_enc_key_match_count_hdl(struct oid_par_priv* poid_par_pri
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
return status;
}
@@ -664,21 +601,20 @@ NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv* poid_par_priv)
ULONG channelnum;
_func_enter_;
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
if ( (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE))
(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE))
pnic_Config = &pmlmepriv->cur_network.network.Configuration;
else
pnic_Config = &padapter->registrypriv.dev_network.Configuration;
channelnum = pnic_Config->DSConfig;
*(ULONG *)poid_par_priv->information_buf = channelnum;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
_func_exit_;
@@ -692,11 +628,10 @@ NDIS_STATUS oid_rt_get_hardware_radio_off_hdl(struct oid_par_priv* poid_par_priv
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
return status;
}
@@ -705,11 +640,10 @@ NDIS_STATUS oid_rt_get_key_mismatch_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
return status;
}
@@ -718,24 +652,22 @@ NDIS_STATUS oid_rt_supported_wireless_mode_hdl(struct oid_par_priv* poid_par_pri
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
ULONG ulInfo = 0 ;
//DEBUG_ERR(("<**********************oid_rt_supported_wireless_mode_hdl \n"));
if(poid_par_priv->type_of_oid != QUERY_OID)
{
//DEBUG_ERR(("<**********************oid_rt_supported_wireless_mode_hdl \n"));
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
if(poid_par_priv->information_buf_len >= sizeof(ULONG)){
}
if(poid_par_priv->information_buf_len >= sizeof(ULONG)) {
ulInfo |= 0x0100; //WIRELESS_MODE_B
ulInfo |= 0x0200; //WIRELESS_MODE_G
ulInfo |= 0x0400; //WIRELESS_MODE_A
*(ULONG *) poid_par_priv->information_buf = ulInfo;
//DEBUG_ERR(("<===oid_rt_supported_wireless_mode %x\n",ulInfo));
*(ULONG *) poid_par_priv->information_buf = ulInfo;
//DEBUG_ERR(("<===oid_rt_supported_wireless_mode %x\n",ulInfo));
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
}
else{
} else {
status = NDIS_STATUS_INVALID_LENGTH;
}
}
return status;
}
@@ -744,11 +676,10 @@ NDIS_STATUS oid_rt_get_channel_list_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
return status;
}
@@ -757,11 +688,10 @@ NDIS_STATUS oid_rt_get_scan_in_progress_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
return status;
}
@@ -786,11 +716,10 @@ NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
return status;
}
@@ -802,19 +731,18 @@ NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv* poid_par_priv
return status;
}
//************** oid_rtl_seg_01_01 section end **************
//************** oid_rtl_seg_01_01 section end **************
//************** oid_rtl_seg_01_03 section start **************
//************** oid_rtl_seg_01_03 section start **************
NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv* poid_par_priv)
{
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
return status;
}
@@ -837,16 +765,15 @@ NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != SET_OID)
{
if(poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
return status;
}
//************** oid_rtl_seg_01_03 section end **************
//************** oid_rtl_seg_01_03 section end **************
//**************** oid_rtl_seg_01_11 section start ****************
NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv* poid_par_priv)
@@ -856,32 +783,28 @@ NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv* poid_par_priv)
_irqL oldirql;
_func_enter_;
//DEBUG_ERR(("<**********************oid_rt_pro_rf_write_registry_hdl \n"));
if(poid_par_priv->type_of_oid != SET_OID) //QUERY_OID
{
if(poid_par_priv->type_of_oid != SET_OID) { //QUERY_OID
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
_irqlevel_changed_(&oldirql,LOWER);
if(poid_par_priv->information_buf_len== (sizeof(unsigned long)*3))
{
if(poid_par_priv->information_buf_len== (sizeof(unsigned long)*3)) {
//RegOffsetValue - The offset of RF register to write.
//RegDataWidth - The data width of RF register to write.
//RegDataValue - The value to write.
//RegDataValue - The value to write.
//RegOffsetValue = *((unsigned long*)InformationBuffer);
//RegDataWidth = *((unsigned long*)InformationBuffer+1);
//RegDataValue = *((unsigned long*)InformationBuffer+2);
if(!rtw_setrfreg_cmd(Adapter,
*(unsigned char*)poid_par_priv->information_buf,
(unsigned long)(*((unsigned long*)poid_par_priv->information_buf+2))))
{
//RegDataWidth = *((unsigned long*)InformationBuffer+1);
//RegDataValue = *((unsigned long*)InformationBuffer+2);
if(!rtw_setrfreg_cmd(Adapter,
*(unsigned char*)poid_par_priv->information_buf,
(unsigned long)(*((unsigned long*)poid_par_priv->information_buf+2)))) {
status = NDIS_STATUS_NOT_ACCEPTED;
}
}
else{
} else {
status = NDIS_STATUS_INVALID_LENGTH;
}
}
_irqlevel_changed_(&oldirql,RAISE);
_func_exit_;
@@ -898,45 +821,38 @@ NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv* poid_par_priv)
_func_enter_;
//DEBUG_ERR(("<**********************oid_rt_pro_rf_read_registry_hdl \n"));
if(poid_par_priv->type_of_oid != SET_OID) //QUERY_OID
{
if(poid_par_priv->type_of_oid != SET_OID) { //QUERY_OID
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
_irqlevel_changed_(&oldirql,LOWER);
if(poid_par_priv->information_buf_len== (sizeof(unsigned long)*3))
{
if(Adapter->mppriv.act_in_progress == _TRUE)
{
if(poid_par_priv->information_buf_len== (sizeof(unsigned long)*3)) {
if(Adapter->mppriv.act_in_progress == _TRUE) {
status = NDIS_STATUS_NOT_ACCEPTED;
}
else
{
} else {
//init workparam
Adapter->mppriv.act_in_progress = _TRUE;
Adapter->mppriv.workparam.bcompleted= _FALSE;
Adapter->mppriv.workparam.act_type = MPT_READ_RF;
Adapter->mppriv.workparam.io_offset = *(unsigned long*)poid_par_priv->information_buf;
Adapter->mppriv.workparam.io_offset = *(unsigned long*)poid_par_priv->information_buf;
Adapter->mppriv.workparam.io_value = 0xcccccccc;
//RegOffsetValue - The offset of RF register to read.
//RegDataWidth - The data width of RF register to read.
//RegDataValue - The value to read.
//RegDataValue - The value to read.
//RegOffsetValue = *((unsigned long*)InformationBuffer);
//RegDataWidth = *((unsigned long*)InformationBuffer+1);
//RegDataValue = *((unsigned long*)InformationBuffer+2);
if(!rtw_getrfreg_cmd(Adapter,
*(unsigned char*)poid_par_priv->information_buf,
(unsigned char*)&Adapter->mppriv.workparam.io_value))
{
//RegDataWidth = *((unsigned long*)InformationBuffer+1);
//RegDataValue = *((unsigned long*)InformationBuffer+2);
if(!rtw_getrfreg_cmd(Adapter,
*(unsigned char*)poid_par_priv->information_buf,
(unsigned char*)&Adapter->mppriv.workparam.io_value)) {
status = NDIS_STATUS_NOT_ACCEPTED;
}
}
}
else {
} else {
status = NDIS_STATUS_INVALID_LENGTH;
}
_irqlevel_changed_(&oldirql,RAISE);
@@ -945,11 +861,11 @@ NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv* poid_par_priv)
return status;
}
//**************** oid_rtl_seg_01_11 section end****************
//**************** oid_rtl_seg_01_11 section end****************
//************** oid_rtl_seg_03_00 section start **************
enum _CONNECT_STATE_{
//************** oid_rtl_seg_03_00 section start **************
enum _CONNECT_STATE_ {
CHECKINGSTATUS,
ASSOCIATED,
ADHOCMODE,
@@ -964,21 +880,20 @@ NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv* poid_par_priv)
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
ULONG ulInfo;
if(poid_par_priv->type_of_oid != QUERY_OID)
{
if(poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
}
// nStatus==0 CheckingStatus
// nStatus==1 Associated
// nStatus==2 AdHocMode
// nStatus==3 NotAssociated
if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)
ulInfo = CHECKINGSTATUS;
else if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
else if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
ulInfo = ASSOCIATED;
else if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)== _TRUE)
ulInfo = ADHOCMODE;
@@ -1011,13 +926,12 @@ NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv* poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
if(poid_par_priv->type_of_oid != SET_OID)
{
if(poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
return status;
}
//************** oid_rtl_seg_03_00 section end **************
//************** oid_rtl_seg_03_00 section end **************

906
backports/drivers/realtek/rtl8812au/core/rtw_ioctl_set.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

149
backports/drivers/realtek/rtl8812au/core/rtw_iol.c Executable file → Normal file
View File

@@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -29,20 +29,18 @@ struct xmit_frame *rtw_IOL_accquire_xmit_frame(ADAPTER *adapter)
struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
#if 1
if ((xmit_frame = rtw_alloc_xmitframe(pxmitpriv)) == NULL)
{
if ((xmit_frame = rtw_alloc_xmitframe(pxmitpriv)) == NULL) {
DBG_871X("%s rtw_alloc_xmitframe return null\n", __FUNCTION__);
goto exit;
}
if ((xmitbuf = rtw_alloc_xmitbuf(pxmitpriv)) == NULL)
{
if ((xmitbuf = rtw_alloc_xmitbuf(pxmitpriv)) == NULL) {
DBG_871X("%s rtw_alloc_xmitbuf return null\n", __FUNCTION__);
rtw_free_xmitframe(pxmitpriv, xmit_frame);
xmit_frame=NULL;
goto exit;
}
xmit_frame->frame_tag = MGNT_FRAMETAG;
xmit_frame->pxmitbuf = xmitbuf;
xmit_frame->buf_addr = xmitbuf->pbuf;
@@ -50,19 +48,17 @@ struct xmit_frame *rtw_IOL_accquire_xmit_frame(ADAPTER *adapter)
pattrib = &xmit_frame->attrib;
update_mgntframe_attrib(adapter, pattrib);
pattrib->qsel = 0x10;//Beacon
pattrib->subtype = WIFI_BEACON;
pattrib->qsel = QSLT_BEACON;//Beacon
pattrib->subtype = WIFI_BEACON;
pattrib->pktlen = pattrib->last_txcmdsz = 0;
#else
if ((xmit_frame = alloc_mgtxmitframe(pxmitpriv)) == NULL)
{
if ((xmit_frame = alloc_mgtxmitframe(pxmitpriv)) == NULL) {
DBG_871X("%s alloc_mgtxmitframe return null\n", __FUNCTION__);
}
else {
} else {
pattrib = &xmit_frame->attrib;
update_mgntframe_attrib(adapter, pattrib);
pattrib->qsel = 0x10;
pattrib->qsel = QSLT_BEACON;
pattrib->pktlen = pattrib->last_txcmdsz = 0;
}
#endif
@@ -84,7 +80,7 @@ int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len
//check if the io_buf can accommodate new cmds
if(ori_len + cmd_len + 8 > MAX_XMITBUF_SZ) {
DBG_871X("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate new cmds\n", __FUNCTION__
, ori_len + cmd_len + 8, MAX_XMITBUF_SZ);
, ori_len + cmd_len + 8, MAX_XMITBUF_SZ);
return _FAIL;
}
@@ -93,12 +89,12 @@ int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len
pattrib->last_txcmdsz += cmd_len;
//DBG_871X("%s ori:%u + cmd_len:%u = %u\n", __FUNCTION__, ori_len, cmd_len, buf_offset+pattrib->pktlen);
return _SUCCESS;
}
bool rtw_IOL_applied(ADAPTER *adapter)
{
{
if(1 == adapter->registrypriv.fw_iol)
return _TRUE;
@@ -124,18 +120,17 @@ int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8
{
struct ioreg_cfg cmd = {8,IOREG_CMD_WB_REG,0x0, 0x0,0x0};
//RTW_PUT_LE16((u8*)&cmd.address, addr);
//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);
cmd.address = cpu_to_le16(addr);
//RTW_PUT_LE16((u8*)&cmd.address, addr);
//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);
cmd.address = cpu_to_le16(addr);
cmd.data = cpu_to_le32(value);
if(mask!=0xFF)
{
if(mask!=0xFF) {
cmd.length = 12;
//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);
//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);
cmd.mask = cpu_to_le32(mask);
}
}
//DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length);
@@ -145,65 +140,62 @@ int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u
{
struct ioreg_cfg cmd = {8,IOREG_CMD_WW_REG,0x0, 0x0,0x0};
//RTW_PUT_LE16((u8*)&cmd.address, addr);
//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);
cmd.address = cpu_to_le16(addr);
//RTW_PUT_LE16((u8*)&cmd.address, addr);
//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);
cmd.address = cpu_to_le16(addr);
cmd.data = cpu_to_le32(value);
if(mask!=0xFFFF)
{
if(mask!=0xFFFF) {
cmd.length = 12;
//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);
//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);
cmd.mask = cpu_to_le32(mask);
}
}
//DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length);
}
int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask)
{
struct ioreg_cfg cmd = {8,IOREG_CMD_WD_REG,0x0, 0x0,0x0};
//RTW_PUT_LE16((u8*)&cmd.address, addr);
//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);
cmd.address = cpu_to_le16(addr);
//RTW_PUT_LE16((u8*)&cmd.address, addr);
//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);
cmd.address = cpu_to_le16(addr);
cmd.data = cpu_to_le32(value);
if(mask!=0xFFFFFFFF)
{
if(mask!=0xFFFFFFFF) {
cmd.length = 12;
//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);
//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);
cmd.mask = cpu_to_le32(mask);
}
}
//DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__, addr,value,mask);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length);
}
int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask)
{
struct ioreg_cfg cmd = {8,IOREG_CMD_W_RF,0x0, 0x0,0x0};
//RTW_PUT_LE16((u8*)&cmd.address, addr);
//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);
cmd.address = (rf_path<<8) |((addr) &0xFF);
//RTW_PUT_LE16((u8*)&cmd.address, addr);
//RTW_PUT_LE32((u8*)&cmd.value, (u32)value);
cmd.address = (rf_path<<8) |((addr) &0xFF);
cmd.data = cpu_to_le32(value);
if(mask!=0x000FFFFF)
{
if(mask!=0x000FFFFF) {
cmd.length = 12;
//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);
//RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask);
cmd.mask = cpu_to_le32(mask);
}
}
//DBG_871X("%s rf_path:0x%02x addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__,rf_path, addr,value,mask);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length);
}
@@ -211,8 +203,8 @@ int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr,
int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
{
struct ioreg_cfg cmd = {4,IOREG_CMD_DELAY_US,0x0, 0x0,0x0};
//RTW_PUT_LE16((u8*)&cmd.address, us);
cmd.address = cpu_to_le16(us);
//RTW_PUT_LE16((u8*)&cmd.address, us);
cmd.address = cpu_to_le16(us);
//DBG_871X("%s %u\n", __FUNCTION__, us);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4);
@@ -222,29 +214,29 @@ int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
{
struct ioreg_cfg cmd = {4,IOREG_CMD_DELAY_US,0x0, 0x0,0x0};
//RTW_PUT_LE16((u8*)&cmd.address, ms);
cmd.address = cpu_to_le16(ms);
//RTW_PUT_LE16((u8*)&cmd.address, ms);
cmd.address = cpu_to_le16(ms);
//DBG_871X("%s %u\n", __FUNCTION__, ms);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4);
}
int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
{
{
struct ioreg_cfg cmd = {4,IOREG_CMD_END,0xFFFF, 0xFF,0x0};
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4);
}
u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame)
{
{
u8 is_cmd_bndy = _FALSE;
if(((pxmit_frame->attrib.pktlen+32)%256) + 8 >= 256){
if(((pxmit_frame->attrib.pktlen+32)%256) + 8 >= 256) {
rtw_IOL_append_END_cmd(pxmit_frame);
pxmit_frame->attrib.pktlen = ((((pxmit_frame->attrib.pktlen+32)/256)+1)*256 );
//printk("==> %s, pktlen(%d)\n",__FUNCTION__,pxmit_frame->attrib.pktlen);
pxmit_frame->attrib.last_txcmdsz = pxmit_frame->attrib.pktlen;
is_cmd_bndy = _TRUE;
is_cmd_bndy = _TRUE;
}
return is_cmd_bndy;
}
@@ -253,23 +245,24 @@ void rtw_IOL_cmd_buf_dump(ADAPTER *Adapter,int buf_len,u8 *pbuf)
{
int i;
int j=1;
printk("###### %s ######\n",__FUNCTION__);
for(i=0;i< buf_len;i++){
for(i=0; i< buf_len; i++) {
printk("%02x-",*(pbuf+i));
if(j%32 ==0) printk("\n");j++;
if(j%32 ==0) printk("\n");
j++;
}
printk("\n");
printk("============= ioreg_cmd len = %d =============== \n",buf_len);
printk("============= ioreg_cmd len = %d =============== \n",buf_len);
}
#else //CONFIG_IOL_NEW_GENERATION
int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)
{
{
IOL_CMD cmd = {0x0, IOL_CMD_LLT, 0x0, 0x0};
RTW_PUT_BE32((u8*)&cmd.value, (u32)page_boundary);
return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8);
@@ -278,7 +271,7 @@ int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary)
int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value)
{
IOL_CMD cmd = {0x0, IOL_CMD_WB_REG, 0x0, 0x0};
RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
@@ -288,7 +281,7 @@ int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value)
int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value)
{
IOL_CMD cmd = {0x0, IOL_CMD_WW_REG, 0x0, 0x0};
RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
@@ -299,7 +292,7 @@ int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value)
{
IOL_CMD cmd = {0x0, IOL_CMD_WD_REG, 0x0, 0x0};
u8* pos = (u8 *)&cmd;
RTW_PUT_BE16((u8*)&cmd.address, (u16)addr);
RTW_PUT_BE32((u8*)&cmd.value, (u32)value);
@@ -335,7 +328,7 @@ int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value
int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
{
IOL_CMD cmd = {0x0, IOL_CMD_DELAY_US, 0x0, 0x0};
RTW_PUT_BE32((u8*)&cmd.value, (u32)us);
//DBG_871X("%s %u\n", __FUNCTION__, us);
@@ -346,7 +339,7 @@ int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us)
int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
{
IOL_CMD cmd = {0x0, IOL_CMD_DELAY_MS, 0x0, 0x0};
RTW_PUT_BE32((u8*)&cmd.value, (u32)ms);
//DBG_871X("%s %u\n", __FUNCTION__, ms);
@@ -355,7 +348,7 @@ int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms)
}
int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame)
{
{
IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0};

97
backports/drivers/realtek/rtl8812au/core/rtw_mem.c Normal file
View File

@@ -0,0 +1,97 @@
#include <drv_types.h>
#include <rtw_mem.h>
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Realtek Wireless Lan Driver");
MODULE_AUTHOR("Realtek Semiconductor Corp.");
MODULE_VERSION("DRIVERVERSION");
struct sk_buff_head rtk_skb_mem_q;
struct u8* rtk_buf_mem[NR_RECVBUFF];
struct u8 * rtw_get_buf_premem(int index)
{
printk("%s, rtk_buf_mem index : %d\n", __func__, index);
return rtk_buf_mem[index];
}
struct sk_buff *rtw_alloc_skb_premem(void)
{
struct sk_buff *skb = NULL;
skb = skb_dequeue(&rtk_skb_mem_q);
printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
return skb;
}
EXPORT_SYMBOL(rtw_alloc_skb_premem);
int rtw_free_skb_premem(struct sk_buff *pskb)
{
if(!pskb)
return -1;
if(skb_queue_len(&rtk_skb_mem_q) >= NR_PREALLOC_RECV_SKB)
return -1;
skb_queue_tail(&rtk_skb_mem_q, pskb);
printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
return 0;
}
EXPORT_SYMBOL(rtw_free_skb_premem);
static int __init rtw_mem_init(void)
{
int i;
SIZE_PTR tmpaddr=0;
SIZE_PTR alignment=0;
struct sk_buff *pskb=NULL;
printk("%s\n", __func__);
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
for(i=0; i<NR_RECVBUFF; i++) {
rtk_buf_mem[i] = usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma);
}
#endif //CONFIG_USE_USB_BUFFER_ALLOC_RX
skb_queue_head_init(&rtk_skb_mem_q);
for(i=0; i<NR_PREALLOC_RECV_SKB; i++) {
pskb = __dev_alloc_skb(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL);
if(pskb) {
tmpaddr = (SIZE_PTR)pskb->data;
alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment));
skb_queue_tail(&rtk_skb_mem_q, pskb);
} else {
printk("%s, alloc skb memory fail!\n", __func__);
}
pskb=NULL;
}
printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
return 0;
}
static void __exit rtw_mem_exit(void)
{
if (skb_queue_len(&rtk_skb_mem_q)) {
printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
}
skb_queue_purge(&rtk_skb_mem_q);
printk("%s\n", __func__);
}
module_init(rtw_mem_init);
module_exit(rtw_mem_exit);

2762
backports/drivers/realtek/rtl8812au/core/rtw_mlme.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

8140
backports/drivers/realtek/rtl8812au/core/rtw_mlme_ext.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

1733
backports/drivers/realtek/rtl8812au/core/rtw_mp.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

820
backports/drivers/realtek/rtl8812au/core/rtw_mp_ioctl.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

215
backports/drivers/realtek/rtl8812au/core/rtw_odm.c Executable file → Normal file
View File

@@ -37,13 +37,13 @@ const char *odm_comp_str[] = {
/* BIT12 */"ODM_COMP_DYNAMIC_PRICCA",
/* BIT13 */"ODM_COMP_RXHP",
/* BIT14 */"ODM_COMP_MP",
/* BIT15 */"ODM_COMP_DYNAMIC_ATC",
/* BIT16 */"ODM_COMP_EDCA_TURBO",
/* BIT17 */"ODM_COMP_EARLY_MODE",
/* BIT18 */NULL,
/* BIT15 */"ODM_COMP_CFO_TRACKING",
/* BIT16 */"ODM_COMP_ACS",
/* BIT17 */"PHYDM_COMP_ADAPTIVITY",
/* BIT18 */"PHYDM_COMP_RA_DBG",
/* BIT19 */NULL,
/* BIT20 */NULL,
/* BIT21 */NULL,
/* BIT20 */"ODM_COMP_EDCA_TURBO",
/* BIT21 */"ODM_COMP_EARLY_MODE",
/* BIT22 */NULL,
/* BIT23 */NULL,
/* BIT24 */"ODM_COMP_TX_PWR_TRACK",
@@ -51,7 +51,7 @@ const char *odm_comp_str[] = {
/* BIT26 */"ODM_COMP_CALIBRATION",
/* BIT27 */NULL,
/* BIT28 */NULL,
/* BIT29 */NULL,
/* BIT29 */"BEAMFORMING_DEBUG",
/* BIT30 */"ODM_COMP_COMMON",
/* BIT31 */"ODM_COMP_INIT",
};
@@ -73,14 +73,14 @@ const char *odm_ability_str[] = {
/* BIT11 */"ODM_BB_PSD",
/* BIT12 */"ODM_BB_RXHP",
/* BIT13 */"ODM_BB_ADAPTIVITY",
/* BIT14 */"ODM_BB_DYNAMIC_ATC",
/* BIT15 */NULL,
/* BIT16 */"ODM_MAC_EDCA_TURBO",
/* BIT17 */"ODM_MAC_EARLY_MODE",
/* BIT14 */"ODM_BB_CFO_TRACKING",
/* BIT15 */"ODM_BB_NHM_CNT",
/* BIT16 */"ODM_BB_PRIMARY_CCA",
/* BIT17 */NULL,
/* BIT18 */NULL,
/* BIT19 */NULL,
/* BIT20 */NULL,
/* BIT21 */NULL,
/* BIT20 */"ODM_MAC_EDCA_TURBO",
/* BIT21 */"ODM_MAC_EARLY_MODE",
/* BIT22 */NULL,
/* BIT23 */NULL,
/* BIT24 */"ODM_RF_TX_PWR_TRACK",
@@ -103,18 +103,18 @@ const char *odm_dbg_level_str[] = {
void rtw_odm_dbg_comp_msg(void *sel, _adapter *adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
int cnt = 0;
//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
//DM_ODM_T *odm = &pHalData->odmpriv;
//int cnt = 0;
u64 dbg_comp;
int i;
rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &dbg_comp);
DBG_871X_SEL_NL(sel, "odm.DebugComponents = 0x%016llx \n", dbg_comp);
for (i=0;i<RTW_ODM_COMP_MAX;i++) {
for (i=0; i<RTW_ODM_COMP_MAX; i++) {
if (odm_comp_str[i])
DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
(BIT0 << i) & dbg_comp ? '+' : ' ', i, odm_comp_str[i]);
DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
(BIT0 << i) & dbg_comp ? '+' : ' ', i, odm_comp_str[i]);
}
}
@@ -125,15 +125,15 @@ inline void rtw_odm_dbg_comp_set(_adapter *adapter, u64 comps)
void rtw_odm_dbg_level_msg(void *sel, _adapter *adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
int cnt = 0;
//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
//DM_ODM_T *odm = &pHalData->odmpriv;
//int cnt = 0;
u32 dbg_level;
int i;
rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &dbg_level);
DBG_871X_SEL_NL(sel, "odm.DebugDebugLevel = %u\n", dbg_level);
for (i=0;i<RTW_ODM_DBG_LEVEL_NUM;i++) {
DBG_871X_SEL_NL(sel, "odm.DebugLevel = %u\n", dbg_level);
for (i=0; i<RTW_ODM_DBG_LEVEL_NUM; i++) {
if (odm_dbg_level_str[i])
DBG_871X_SEL_NL(sel, "%u %s\n", i, odm_dbg_level_str[i]);
}
@@ -146,18 +146,18 @@ inline void rtw_odm_dbg_level_set(_adapter *adapter, u32 level)
void rtw_odm_ability_msg(void *sel, _adapter *adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
int cnt = 0;
//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
//DM_ODM_T *odm = &pHalData->odmpriv;
//int cnt = 0;
u32 ability = 0;
int i;
rtw_hal_get_hwreg(adapter, HW_VAR_DM_FLAG, (u8*)&ability);
DBG_871X_SEL_NL(sel, "odm.SupportAbility = 0x%08x\n", ability);
for (i=0;i<RTW_ODM_ABILITY_MAX;i++) {
for (i=0; i<RTW_ODM_ABILITY_MAX; i++) {
if (odm_ability_str[i])
DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
(BIT0 << i) & ability ? '+' : ' ', i, odm_ability_str[i]);
DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
(BIT0 << i) & ability ? '+' : ' ', i, odm_ability_str[i]);
}
}
@@ -166,25 +166,117 @@ inline void rtw_odm_ability_set(_adapter *adapter, u32 ability)
rtw_hal_set_hwreg(adapter, HW_VAR_DM_FLAG, (u8*)&ability);
}
void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
{
DBG_871X_SEL_NL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n");
}
#define RTW_ADAPTIVITY_EN_DISABLE 0
#define RTW_ADAPTIVITY_EN_ENABLE 1
void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
{
struct registry_priv *regsty = &adapter->registrypriv;
//struct mlme_priv *mlme = &adapter->mlmepriv;
//HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
//DM_ODM_T *odm = &hal_data->odmpriv;
DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_EN_");
if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE) {
DBG_871X_SEL(sel, "DISABLE\n");
} else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE) {
DBG_871X_SEL(sel, "ENABLE\n");
} else {
DBG_871X_SEL(sel, "INVALID\n");
}
}
#define RTW_ADAPTIVITY_MODE_NORMAL 0
#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1
void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter)
{
struct registry_priv *regsty = &adapter->registrypriv;
DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_MODE_");
if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL) {
DBG_871X_SEL(sel, "NORMAL\n");
} else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE) {
DBG_871X_SEL(sel, "CARRIER_SENSE\n");
} else {
DBG_871X_SEL(sel, "INVALID\n");
}
}
#define RTW_ADAPTIVITY_DML_DISABLE 0
#define RTW_ADAPTIVITY_DML_ENABLE 1
void rtw_odm_adaptivity_dml_msg(void *sel, _adapter *adapter)
{
struct registry_priv *regsty = &adapter->registrypriv;
DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_DML_");
if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_DISABLE) {
DBG_871X_SEL(sel, "DISABLE\n");
} else if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_ENABLE) {
DBG_871X_SEL(sel, "ENABLE\n");
} else {
DBG_871X_SEL(sel, "INVALID\n");
}
}
bool rtw_odm_adaptivity_needed(_adapter *adapter)
{
struct registry_priv *regsty = &adapter->registrypriv;
//struct mlme_priv *mlme = &adapter->mlmepriv;
bool ret = _FALSE;
if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE)
ret = _TRUE;
if (ret == _TRUE) {
rtw_odm_adaptivity_ver_msg(RTW_DBGDUMP, adapter);
rtw_odm_adaptivity_en_msg(RTW_DBGDUMP, adapter);
rtw_odm_adaptivity_mode_msg(RTW_DBGDUMP, adapter);
rtw_odm_adaptivity_dml_msg(RTW_DBGDUMP, adapter);
}
return ret;
}
void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
DBG_871X_SEL_NL(sel, "%10s %16s %8s %10s %11s %14s\n"
, "TH_L2H_ini", "TH_EDCCA_HL_diff", "IGI_Base", "ForceEDCCA", "AdapEn_RSSI", "IGI_LowerBound");
DBG_871X_SEL_NL(sel, "0x%-8x %-16d 0x%-6x %-10d %-11u %-14u\n"
, (u8)odm->TH_L2H_ini
, odm->TH_EDCCA_HL_diff
, odm->IGI_Base
, odm->ForceEDCCA
, odm->AdapEn_RSSI
, odm->IGI_LowerBound
);
rtw_odm_adaptivity_ver_msg(sel, adapter);
rtw_odm_adaptivity_en_msg(sel, adapter);
rtw_odm_adaptivity_mode_msg(sel, adapter);
rtw_odm_adaptivity_dml_msg(sel, adapter);
DBG_871X_SEL_NL(sel, "%10s %16s %8s %7s\n"
, "TH_L2H_ini", "TH_EDCCA_HL_diff", "IGI_Base", "FABound");
DBG_871X_SEL_NL(sel, "0x%-8x %-16d 0x%-6x %-7d\n"
, (u8)odm->TH_L2H_ini
, odm->TH_EDCCA_HL_diff
, odm->IGI_Base
, odm->FABound
);
DBG_871X_SEL_NL(sel, "%15s %9s\n", "AdapEnableState","Adap_Flag");
DBG_871X_SEL_NL(sel, "%-15x %-9x \n"
, odm->Adaptivity_enable
, odm->adaptivity_flag
);
}
void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound)
s8 IGI_Base, u32 FABound)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &pHalData->odmpriv;
@@ -192,8 +284,43 @@ void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_H
odm->TH_L2H_ini = TH_L2H_ini;
odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;
odm->IGI_Base = IGI_Base;
odm->ForceEDCCA = ForceEDCCA;
odm->AdapEn_RSSI = AdapEn_RSSI;
odm->IGI_LowerBound = IGI_LowerBound;
odm->FABound = FABound;
}
void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &(hal_data->odmpriv);
DBG_871X_SEL_NL(sel,"RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
}
void rtw_odm_acquirespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
_irqL irqL;
switch(type) {
case RT_IQK_SPINLOCK:
_enter_critical_bh(&pdmpriv->IQKSpinLock, &irqL);
default:
break;
}
}
void rtw_odm_releasespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
_irqL irqL;
switch(type) {
case RT_IQK_SPINLOCK:
_exit_critical_bh(&pdmpriv->IQKSpinLock, &irqL);
default:
break;
}
}

2544
backports/drivers/realtek/rtl8812au/core/rtw_p2p.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

1345
backports/drivers/realtek/rtl8812au/core/rtw_pwrctrl.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

3117
backports/drivers/realtek/rtl8812au/core/rtw_recv.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

18
backports/drivers/realtek/rtl8812au/core/rtw_rf.c Executable file → Normal file
View File

@@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -56,12 +56,10 @@ u32 rtw_ch2freq(u32 channel)
u8 i;
u32 freq = 0;
for (i = 0; i < ch_freq_map_num; i++)
{
if (channel == ch_freq_map[i].channel)
{
for (i = 0; i < ch_freq_map_num; i++) {
if (channel == ch_freq_map[i].channel) {
freq = ch_freq_map[i].frequency;
break;
break;
}
}
if (i == ch_freq_map_num)
@@ -75,12 +73,10 @@ u32 rtw_freq2ch(u32 freq)
u8 i;
u32 ch = 0;
for (i = 0; i < ch_freq_map_num; i++)
{
if (freq == ch_freq_map[i].frequency)
{
for (i = 0; i < ch_freq_map_num; i++) {
if (freq == ch_freq_map[i].frequency) {
ch = ch_freq_map[i].channel;
break;
break;
}
}
if (i == ch_freq_map_num)

2421
backports/drivers/realtek/rtl8812au/core/rtw_security.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

722
backports/drivers/realtek/rtl8812au/core/rtw_sreset.c Executable file → Normal file
View File

@@ -1,367 +1,355 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include <drv_types.h>
#include <hal_data.h>
#include <rtw_sreset.h>
void sreset_init_value(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
_rtw_mutex_init(&psrtpriv->silentreset_mutex);
psrtpriv->silent_reset_inprogress = _FALSE;
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
psrtpriv->last_tx_time =0;
psrtpriv->last_tx_complete_time =0;
#endif
}
void sreset_reset_value(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
psrtpriv->last_tx_time =0;
psrtpriv->last_tx_complete_time =0;
#endif
}
u8 sreset_get_wifi_status(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
u8 status = WIFI_STATUS_SUCCESS;
u32 val32 = 0;
_irqL irqL;
if(psrtpriv->silent_reset_inprogress == _TRUE)
{
return status;
}
val32 =rtw_read32(padapter,REG_TXDMA_STATUS);
if(val32==0xeaeaeaea){
psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST;
}
else if(val32!=0){
DBG_8192C("txdmastatu(%x)\n",val32);
psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR;
}
if(WIFI_STATUS_SUCCESS !=psrtpriv->Wifi_Error_Status)
{
DBG_8192C("==>%s error_status(0x%x) \n",__FUNCTION__,psrtpriv->Wifi_Error_Status);
status = (psrtpriv->Wifi_Error_Status &( ~(USB_READ_PORT_FAIL|USB_WRITE_PORT_FAIL)));
}
DBG_8192C("==> %s wifi_status(0x%x)\n",__FUNCTION__,status);
//status restore
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
return status;
#else
return WIFI_STATUS_SUCCESS;
#endif
}
void sreset_set_wifi_error_status(_adapter *padapter, u32 status)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
pHalData->srestpriv.Wifi_Error_Status = status;
#endif
}
void sreset_set_trigger_point(_adapter *padapter, s32 tgp)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
pHalData->srestpriv.dbg_trigger_point = tgp;
#endif
}
bool sreset_inprogress(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_RESET)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
return pHalData->srestpriv.silent_reset_inprogress;
#else
return _FALSE;
#endif
}
void sreset_restore_security_station(_adapter *padapter)
{
u8 EntryId = 0;
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct sta_priv * pstapriv = &padapter->stapriv;
struct sta_info *psta;
struct security_priv* psecuritypriv=&(padapter->securitypriv);
struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
{
u8 val8;
if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) {
val8 = 0xcc;
#ifdef CONFIG_WAPI_SUPPORT
} else if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) {
//Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey.
val8 = 0x4c;
#endif
} else {
val8 = 0xcf;
}
rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
}
#if 0
if ( ( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP40_ ) ||
( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP104_ ))
{
for(EntryId=0; EntryId<4; EntryId++)
{
if(EntryId == psecuritypriv->dot11PrivacyKeyIndex)
rtw_set_key(padapter,&padapter->securitypriv, EntryId, 1,_FALSE);
else
rtw_set_key(padapter,&padapter->securitypriv, EntryId, 0,_FALSE);
}
}
else
#endif
if((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
(padapter->securitypriv.dot11PrivacyAlgrthm == _AES_))
{
psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv));
if (psta == NULL) {
//DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n"));
}
else
{
//pairwise key
rtw_setstakey_cmd(padapter, (unsigned char *)psta, _TRUE,_FALSE);
//group key
rtw_set_key(padapter,&padapter->securitypriv,padapter->securitypriv.dot118021XGrpKeyid, 0,_FALSE);
}
}
}
void sreset_restore_network_station(_adapter *padapter)
{
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
#if 0
{
//=======================================================
// reset related register of Beacon control
//set MSR to nolink
Set_MSR(padapter, _HW_STATE_NOLINK_);
// reject all data frame
rtw_write16(padapter, REG_RXFLTMAP2,0x00);
//reset TSF
rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
// disable update TSF
SetBcnCtrlReg(padapter, BIT(4), 0);
//=======================================================
}
#endif
rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure,_FALSE);
{
u8 threshold;
#ifdef CONFIG_USB_HCI
// TH=1 => means that invalidate usb rx aggregation
// TH=0 => means that validate usb rx aggregation, use init value.
if(mlmepriv->htpriv.ht_option) {
if(padapter->registrypriv.wifi_spec==1)
threshold = 1;
else
threshold = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
} else {
threshold = 1;
rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
}
#endif
}
rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, NULL);
set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
//disable dynamic functions, such as high power, DIG
//Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
{
u8 join_type = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
}
Set_MSR(padapter, (pmlmeinfo->state & 0x3));
mlmeext_joinbss_event_callback(padapter, 1);
//restore Sequence No.
rtw_write8(padapter,0x4dc,padapter->xmitpriv.nqos_ssn);
sreset_restore_security_station(padapter);
}
void sreset_restore_network_status(_adapter *padapter)
{
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
sreset_restore_network_station(padapter);
} else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
rtw_ap_restore_network(padapter);
} else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
} else {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
}
}
void sreset_stop_adapter(_adapter *padapter)
{
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
if (padapter == NULL)
return;
DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
if (!rtw_netif_queue_stopped(padapter->pnetdev))
rtw_netif_stop_queue(padapter->pnetdev);
rtw_cancel_all_timer(padapter);
/* TODO: OS and HCI independent */
#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
tasklet_kill(&pxmitpriv->xmit_tasklet);
#endif
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
rtw_scan_abort(padapter);
if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING))
{
rtw_set_to_roam(padapter, 0);
_rtw_join_timeout_handler(padapter);
}
}
void sreset_start_adapter(_adapter *padapter)
{
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
if (padapter == NULL)
return;
DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
if (check_fwstate(pmlmepriv, _FW_LINKED)) {
sreset_restore_network_status(padapter);
}
/* TODO: OS and HCI independent */
#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
#endif
_set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000);
if (rtw_netif_queue_stopped(padapter->pnetdev))
rtw_netif_wake_queue(padapter->pnetdev);
}
void sreset_reset(_adapter *padapter)
{
#ifdef DBG_CONFIG_ERROR_RESET
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
_irqL irqL;
u32 start = rtw_get_current_time();
struct dvobj_priv *psdpriv = padapter->dvobj;
struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
DBG_871X("%s\n", __FUNCTION__);
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
#ifdef CONFIG_POWER_SAVING
rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "SRESET");
#endif
_enter_pwrlock(&pwrpriv->lock);
psrtpriv->silent_reset_inprogress = _TRUE;
pwrpriv->change_rfpwrstate = rf_off;
sreset_stop_adapter(padapter);
#ifdef CONFIG_CONCURRENT_MODE
sreset_stop_adapter(padapter->pbuddy_adapter);
#endif
#ifdef CONFIG_IPS
_ips_enter(padapter);
_ips_leave(padapter);
#endif
sreset_start_adapter(padapter);
#ifdef CONFIG_CONCURRENT_MODE
sreset_start_adapter(padapter->pbuddy_adapter);
#endif
psrtpriv->silent_reset_inprogress = _FALSE;
_exit_pwrlock(&pwrpriv->lock);
DBG_871X("%s done in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
pdbgpriv->dbg_sreset_cnt++;
#endif
}
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include <drv_types.h>
#include <hal_data.h>
#include <rtw_sreset.h>
void sreset_init_value(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
_rtw_mutex_init(&psrtpriv->silentreset_mutex);
psrtpriv->silent_reset_inprogress = _FALSE;
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
psrtpriv->last_tx_time =0;
psrtpriv->last_tx_complete_time =0;
#endif
}
void sreset_reset_value(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
psrtpriv->last_tx_time =0;
psrtpriv->last_tx_complete_time =0;
#endif
}
u8 sreset_get_wifi_status(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
u8 status = WIFI_STATUS_SUCCESS;
u32 val32 = 0;
//_irqL irqL;
if(psrtpriv->silent_reset_inprogress == _TRUE) {
return status;
}
val32 =rtw_read32(padapter,REG_TXDMA_STATUS);
if(val32==0xeaeaeaea) {
psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST;
} else if(val32!=0) {
DBG_8192C("txdmastatu(%x)\n",val32);
psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR;
}
if(WIFI_STATUS_SUCCESS !=psrtpriv->Wifi_Error_Status) {
DBG_8192C("==>%s error_status(0x%x) \n",__FUNCTION__,psrtpriv->Wifi_Error_Status);
status = (psrtpriv->Wifi_Error_Status &( ~(USB_READ_PORT_FAIL|USB_WRITE_PORT_FAIL)));
}
DBG_8192C("==> %s wifi_status(0x%x)\n",__FUNCTION__,status);
//status restore
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
return status;
#else
return WIFI_STATUS_SUCCESS;
#endif
}
void sreset_set_wifi_error_status(_adapter *padapter, u32 status)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
pHalData->srestpriv.Wifi_Error_Status = status;
#endif
}
void sreset_set_trigger_point(_adapter *padapter, s32 tgp)
{
#if defined(DBG_CONFIG_ERROR_DETECT)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
pHalData->srestpriv.dbg_trigger_point = tgp;
#endif
}
bool sreset_inprogress(_adapter *padapter)
{
#if defined(DBG_CONFIG_ERROR_RESET)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
return pHalData->srestpriv.silent_reset_inprogress;
#else
return _FALSE;
#endif
}
void sreset_restore_security_station(_adapter *padapter)
{
//u8 EntryId = 0;
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct sta_priv * pstapriv = &padapter->stapriv;
struct sta_info *psta;
//struct security_priv* psecuritypriv=&(padapter->securitypriv);
struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
{
u8 val8;
if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) {
val8 = 0xcc;
#ifdef CONFIG_WAPI_SUPPORT
} else if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) {
//Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey.
val8 = 0x4c;
#endif
} else {
val8 = 0xcf;
}
rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
}
#if 0
if ( ( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP40_ ) ||
( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP104_ )) {
for(EntryId=0; EntryId<4; EntryId++) {
if(EntryId == psecuritypriv->dot11PrivacyKeyIndex)
rtw_set_key(padapter,&padapter->securitypriv, EntryId, 1,_FALSE);
else
rtw_set_key(padapter,&padapter->securitypriv, EntryId, 0,_FALSE);
}
} else
#endif
if((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
(padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {
psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv));
if (psta == NULL) {
//DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n"));
} else {
//pairwise key
rtw_setstakey_cmd(padapter, psta, UNICAST_KEY,_FALSE);
//group key
rtw_set_key(padapter,&padapter->securitypriv,padapter->securitypriv.dot118021XGrpKeyid, 0,_FALSE);
}
}
}
void sreset_restore_network_station(_adapter *padapter)
{
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
#if 0
{
//=======================================================
// reset related register of Beacon control
//set MSR to nolink
Set_MSR(padapter, _HW_STATE_NOLINK_);
// reject all data frame
rtw_write16(padapter, REG_RXFLTMAP2,0x00);
//reset TSF
rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
// disable update TSF
SetBcnCtrlReg(padapter, BIT(4), 0);
//=======================================================
}
#endif
rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure,_FALSE);
{
u8 threshold;
#ifdef CONFIG_USB_HCI
// TH=1 => means that invalidate usb rx aggregation
// TH=0 => means that validate usb rx aggregation, use init value.
if(mlmepriv->htpriv.ht_option) {
if(padapter->registrypriv.wifi_spec==1)
threshold = 1;
else
threshold = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
} else {
threshold = 1;
rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
}
#endif
}
rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, NULL);
set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
//disable dynamic functions, such as high power, DIG
//Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
{
u8 join_type = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
}
Set_MSR(padapter, (pmlmeinfo->state & 0x3));
mlmeext_joinbss_event_callback(padapter, 1);
//restore Sequence No.
rtw_write8(padapter,0x4dc,padapter->xmitpriv.nqos_ssn);
sreset_restore_security_station(padapter);
}
void sreset_restore_network_status(_adapter *padapter)
{
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
//struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
//struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
sreset_restore_network_station(padapter);
} else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
rtw_ap_restore_network(padapter);
} else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
} else {
DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
}
}
void sreset_stop_adapter(_adapter *padapter)
{
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
if (padapter == NULL)
return;
DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
rtw_netif_stop_queue(padapter->pnetdev);
rtw_cancel_all_timer(padapter);
/* TODO: OS and HCI independent */
#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
tasklet_kill(&pxmitpriv->xmit_tasklet);
#endif
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
rtw_scan_abort(padapter);
if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) {
rtw_set_to_roam(padapter, 0);
_rtw_join_timeout_handler(padapter);
}
}
void sreset_start_adapter(_adapter *padapter)
{
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
if (padapter == NULL)
return;
DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
if (check_fwstate(pmlmepriv, _FW_LINKED)) {
sreset_restore_network_status(padapter);
}
/* TODO: OS and HCI independent */
#if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI)
tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
#endif
if (is_primary_adapter(padapter))
_set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000);
rtw_netif_wake_queue(padapter->pnetdev);
}
void sreset_reset(_adapter *padapter)
{
#ifdef DBG_CONFIG_ERROR_RESET
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
_irqL irqL;
u32 start = rtw_get_current_time();
struct dvobj_priv *psdpriv = padapter->dvobj;
struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
DBG_871X("%s\n", __FUNCTION__);
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
#ifdef CONFIG_LPS
rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "SRESET");
#endif//#ifdef CONFIG_LPS
_enter_pwrlock(&pwrpriv->lock);
psrtpriv->silent_reset_inprogress = _TRUE;
pwrpriv->change_rfpwrstate = rf_off;
sreset_stop_adapter(padapter);
#ifdef CONFIG_CONCURRENT_MODE
sreset_stop_adapter(padapter->pbuddy_adapter);
#endif
#ifdef CONFIG_IPS
_ips_enter(padapter);
_ips_leave(padapter);
#endif
sreset_start_adapter(padapter);
#ifdef CONFIG_CONCURRENT_MODE
sreset_start_adapter(padapter->pbuddy_adapter);
#endif
psrtpriv->silent_reset_inprogress = _FALSE;
_exit_pwrlock(&pwrpriv->lock);
DBG_871X("%s done in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
pdbgpriv->dbg_sreset_cnt++;
#endif
}

439
backports/drivers/realtek/rtl8812au/core/rtw_sta_mgt.c Executable file → Normal file
View File

@@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -32,33 +32,33 @@ void _rtw_init_stainfo(struct sta_info *psta);
void _rtw_init_stainfo(struct sta_info *psta)
{
_func_enter_;
_func_enter_;
_rtw_memset((u8 *)psta, 0, sizeof (struct sta_info));
_rtw_spinlock_init(&psta->lock);
_rtw_spinlock_init(&psta->lock);
_rtw_init_listhead(&psta->list);
_rtw_init_listhead(&psta->hash_list);
//_rtw_init_listhead(&psta->asoc_list);
//_rtw_init_listhead(&psta->sleep_list);
//_rtw_init_listhead(&psta->wakeup_list);
//_rtw_init_listhead(&psta->wakeup_list);
_rtw_init_queue(&psta->sleep_q);
psta->sleepq_len = 0;
_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
#ifdef CONFIG_AP_MODE
_rtw_init_listhead(&psta->asoc_list);
_rtw_init_listhead(&psta->auth_list);
psta->expire_to = 0;
psta->flags = 0;
psta->capability = 0;
psta->bpairwise_key_installed = _FALSE;
@@ -71,17 +71,17 @@ _func_enter_;
psta->no_ht_gf_set = 0;
psta->no_ht_set = 0;
psta->ht_20mhz_set = 0;
#endif
#endif
#ifdef CONFIG_TX_MCAST2UNI
psta->under_exist_checking = 0;
#endif // CONFIG_TX_MCAST2UNI
psta->keep_alive_trycnt = 0;
#endif // CONFIG_AP_MODE
_func_exit_;
#endif // CONFIG_AP_MODE
_func_exit_;
}
@@ -90,20 +90,20 @@ u32 _rtw_init_sta_priv(struct sta_priv *pstapriv)
struct sta_info *psta;
s32 i;
_func_enter_;
_func_enter_;
pstapriv->pallocated_stainfo_buf = rtw_zvmalloc (sizeof(struct sta_info) * NUM_STA+ 4);
if(!pstapriv->pallocated_stainfo_buf)
return _FAIL;
pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 -
((SIZE_PTR)(pstapriv->pallocated_stainfo_buf ) & 3);
pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 -
((SIZE_PTR)(pstapriv->pallocated_stainfo_buf ) & 3);
_rtw_init_queue(&pstapriv->free_sta_queue);
_rtw_spinlock_init(&pstapriv->sta_hash_lock);
//_rtw_init_queue(&pstapriv->asoc_q);
pstapriv->asoc_sta_count = 0;
_rtw_init_queue(&pstapriv->sleep_q);
@@ -111,9 +111,8 @@ _func_enter_;
psta = (struct sta_info *)(pstapriv->pstainfo_buf);
for(i = 0; i < NUM_STA; i++)
{
for(i = 0; i < NUM_STA; i++) {
_rtw_init_stainfo(psta);
_rtw_init_listhead(&(pstapriv->sta_hash[i]));
@@ -123,7 +122,7 @@ _func_enter_;
psta++;
}
#ifdef CONFIG_AP_MODE
@@ -137,7 +136,7 @@ _func_enter_;
pstapriv->asoc_list_cnt = 0;
pstapriv->auth_list_cnt = 0;
pstapriv->auth_to = 3; // 3*2 = 6 sec
pstapriv->auth_to = 3; // 3*2 = 6 sec
pstapriv->assoc_to = 3;
//pstapriv->expire_to = 900;// 900*2 = 1800 sec = 30 min, expire after no any traffic.
//pstapriv->expire_to = 30;// 30*2 = 60 sec = 1 min, expire after no any traffic.
@@ -145,18 +144,18 @@ _func_enter_;
pstapriv->expire_to = 3; // 3*2 = 6 sec
#else
pstapriv->expire_to = 60;// 60*2 = 120 sec = 2 min, expire after no any traffic.
#endif
#endif
#ifdef CONFIG_ATMEL_RC_PATCH
_rtw_memset( pstapriv->atmel_rc_pattern, 0, ETH_ALEN);
#endif
pstapriv->max_num_sta = NUM_STA;
#endif
_func_exit_;
pstapriv->max_num_sta = NUM_STA;
#endif
_func_exit_;
return _SUCCESS;
}
inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta)
@@ -180,7 +179,7 @@ inline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int
void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv);
void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv)
{
_func_enter_;
_func_enter_;
_rtw_spinlock_free(&psta_xmitpriv->lock);
@@ -188,33 +187,33 @@ _func_enter_;
_rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock));
_rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock));
_rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock));
_func_exit_;
_func_exit_;
}
static void _rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv)
{
_func_enter_;
_func_enter_;
_rtw_spinlock_free(&psta_recvpriv->lock);
_rtw_spinlock_free(&(psta_recvpriv->defrag_q.lock));
_func_exit_;
_func_exit_;
}
void rtw_mfree_stainfo(struct sta_info *psta);
void rtw_mfree_stainfo(struct sta_info *psta)
{
_func_enter_;
_func_enter_;
if(&psta->lock != NULL)
_rtw_spinlock_free(&psta->lock);
_rtw_spinlock_free(&psta->lock);
_rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv);
_rtw_free_sta_recv_priv_lock(&psta->sta_recvpriv);
_func_exit_;
_func_exit_;
}
@@ -225,25 +224,24 @@ void rtw_mfree_all_stainfo(struct sta_priv *pstapriv )
_irqL irqL;
_list *plist, *phead;
struct sta_info *psta = NULL;
_func_enter_;
_func_enter_;
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
phead = get_list_head(&pstapriv->free_sta_queue);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
psta = LIST_CONTAINOR(plist, struct sta_info ,list);
plist = get_next(plist);
rtw_mfree_stainfo(psta);
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
_func_exit_;
_func_exit_;
}
@@ -254,7 +252,7 @@ void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv)
struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
#endif
rtw_mfree_all_stainfo(pstapriv); //be done before free sta_hash_lock
rtw_mfree_all_stainfo(pstapriv); //be done before free sta_hash_lock
_rtw_spinlock_free(&pstapriv->free_sta_queue.lock);
@@ -278,48 +276,45 @@ u32 _rtw_free_sta_priv(struct sta_priv *pstapriv)
struct recv_reorder_ctrl *preorder_ctrl;
int index;
_func_enter_;
if(pstapriv){
_func_enter_;
if(pstapriv) {
/* delete all reordering_ctrl_timer */
/* delete all reordering_ctrl_timer */
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
for(index = 0; index < NUM_STA; index++)
{
for(index = 0; index < NUM_STA; index++) {
phead = &(pstapriv->sta_hash[index]);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
int i;
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
int i;
psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list);
plist = get_next(plist);
for(i=0; i < 16 ; i++)
{
for(i=0; i < 16 ; i++) {
preorder_ctrl = &psta->recvreorder_ctrl[i];
_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
}
}
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
/*===============================*/
rtw_mfree_sta_priv_lock(pstapriv);
if(pstapriv->pallocated_stainfo_buf) {
rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info)*NUM_STA+4);
}
}
_func_exit_;
_func_exit_;
return _SUCCESS;
}
//struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr)
struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
{
_irqL irqL, irqL2;
struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr)
{
_irqL irqL2;
uint tmp_aid;
s32 index;
_list *phash_list;
@@ -328,29 +323,26 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
struct recv_reorder_ctrl *preorder_ctrl;
int i = 0;
u16 wRxSeqInitialValue = 0xffff;
_func_enter_;
_func_enter_;
pfree_sta_queue = &pstapriv->free_sta_queue;
//_enter_critical_bh(&(pfree_sta_queue->lock), &irqL);
_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
if (_rtw_queue_empty(pfree_sta_queue) == _TRUE)
{
if (_rtw_queue_empty(pfree_sta_queue) == _TRUE) {
//_exit_critical_bh(&(pfree_sta_queue->lock), &irqL);
_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
psta = NULL;
}
else
{
} else {
psta = LIST_CONTAINOR(get_next(&pfree_sta_queue->queue), struct sta_info, list);
rtw_list_delete(&(psta->list));
//_exit_critical_bh(&(pfree_sta_queue->lock), &irqL);
tmp_aid = psta->aid;
tmp_aid = psta->aid;
_rtw_init_stainfo(psta);
psta->padapter = pstapriv->padapter;
@@ -361,9 +353,9 @@ _func_enter_;
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("rtw_alloc_stainfo: index = %x", index));
if(index >= NUM_STA){
if(index >= NUM_STA) {
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("ERROR=> rtw_alloc_stainfo: index >= NUM_STA"));
psta= NULL;
psta= NULL;
goto exit;
}
phash_list = &(pstapriv->sta_hash[index]);
@@ -381,13 +373,12 @@ _func_enter_;
// In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable.
// So, we initialize the tid_rxseq variable as the 0xffff.
for( i = 0; i < 16; i++ )
{
_rtw_memcpy( &psta->sta_recvpriv.rxcache.tid_rxseq[ i ], &wRxSeqInitialValue, 2 );
for( i = 0; i < 16; i++ ) {
_rtw_memcpy( &psta->sta_recvpriv.rxcache.tid_rxseq[ i ], &wRxSeqInitialValue, 2 );
}
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("alloc number_%d stainfo with hwaddr = %x %x %x %x %x %x \n",
pstapriv->asoc_sta_count , hwaddr[0], hwaddr[1], hwaddr[2],hwaddr[3],hwaddr[4],hwaddr[5]));
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("alloc number_%d stainfo with hwaddr = %x %x %x %x %x %x \n",
pstapriv->asoc_sta_count , hwaddr[0], hwaddr[1], hwaddr[2],hwaddr[3],hwaddr[4],hwaddr[5]));
init_addba_retry_timer(pstapriv->padapter, psta);
@@ -396,22 +387,22 @@ _func_enter_;
#endif //CONFIG_TDLS
//for A-MPDU Rx reordering buffer control
for(i=0; i < 16 ; i++)
{
for(i=0; i < 16 ; i++) {
preorder_ctrl = &psta->recvreorder_ctrl[i];
preorder_ctrl->padapter = pstapriv->padapter;
preorder_ctrl->enable = _FALSE;
preorder_ctrl->indicate_seq = 0xffff;
#ifdef DBG_RX_SEQ
#ifdef DBG_RX_SEQ
DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d\n", __FUNCTION__, __LINE__,
preorder_ctrl->indicate_seq);
#endif
preorder_ctrl->wend_b= 0xffff;
preorder_ctrl->indicate_seq);
#endif
preorder_ctrl->wend_b= 0xffff;
//preorder_ctrl->wsize_b = (NR_RECVBUFF-2);
preorder_ctrl->wsize_b = 64;//64;
preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;
_rtw_init_queue(&preorder_ctrl->pending_recvframe_queue);
@@ -432,12 +423,12 @@ _func_enter_;
rtw_alloc_macid(pstapriv->padapter, psta);
}
exit:
_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
_func_exit_;
_func_exit_;
return psta;
@@ -447,7 +438,7 @@ _func_exit_;
// using pstapriv->sta_hash_lock to protect
u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta)
{
{
int i;
_irqL irqL0;
_queue *pfree_sta_queue;
@@ -456,13 +447,19 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta)
struct xmit_priv *pxmitpriv= &padapter->xmitpriv;
struct sta_priv *pstapriv = &padapter->stapriv;
struct hw_xmit *phwxmit;
int pending_qcnt[4];
_func_enter_;
_func_enter_;
if (psta == NULL)
goto exit;
_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
rtw_list_delete(&psta->hash_list);
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("\n free number_%d stainfo with hwaddr = 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x \n",pstapriv->asoc_sta_count , psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5]));
pstapriv->asoc_sta_count --;
_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
_enter_critical_bh(&psta->lock, &irqL0);
psta->state &= ~_FW_LINKED;
@@ -472,22 +469,23 @@ _func_enter_;
pstaxmitpriv = &psta->sta_xmitpriv;
//rtw_list_delete(&psta->sleep_list);
//rtw_list_delete(&psta->wakeup_list);
_enter_critical_bh(&pxmitpriv->lock, &irqL0);
rtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q);
psta->sleepq_len = 0;
//vo
//_enter_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0);
rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->vo_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
phwxmit = pxmitpriv->hwxmits;
phwxmit->accnt -= pstaxmitpriv->vo_q.qcnt;
pending_qcnt[0] = pstaxmitpriv->vo_q.qcnt;
pstaxmitpriv->vo_q.qcnt = 0;
//_exit_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0);
@@ -497,6 +495,7 @@ _func_enter_;
rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
phwxmit = pxmitpriv->hwxmits+1;
phwxmit->accnt -= pstaxmitpriv->vi_q.qcnt;
pending_qcnt[1] = pstaxmitpriv->vi_q.qcnt;
pstaxmitpriv->vi_q.qcnt = 0;
//_exit_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0);
@@ -506,25 +505,25 @@ _func_enter_;
rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
phwxmit = pxmitpriv->hwxmits+2;
phwxmit->accnt -= pstaxmitpriv->be_q.qcnt;
pending_qcnt[2] = pstaxmitpriv->be_q.qcnt;
pstaxmitpriv->be_q.qcnt = 0;
//_exit_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0);
//bk
//_enter_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0);
rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->bk_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
phwxmit = pxmitpriv->hwxmits+3;
phwxmit->accnt -= pstaxmitpriv->bk_q.qcnt;
pending_qcnt[3] = pstaxmitpriv->bk_q.qcnt;
pstaxmitpriv->bk_q.qcnt = 0;
//_exit_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0);
rtw_os_wake_queue_at_free_stainfo(padapter, pending_qcnt);
_exit_critical_bh(&pxmitpriv->lock, &irqL0);
rtw_list_delete(&psta->hash_list);
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("\n free number_%d stainfo with hwaddr = 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x \n",pstapriv->asoc_sta_count , psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5]));
pstapriv->asoc_sta_count --;
// re-init sta_info; 20061114 // will be init in alloc_stainfo
//_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
//_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
@@ -532,66 +531,65 @@ _func_enter_;
_cancel_timer_ex(&psta->addba_retry_timer);
#ifdef CONFIG_TDLS
psta->tdls_sta_state = TDLS_STATE_NONE;
rtw_free_tdls_timer(psta);
#endif //CONFIG_TDLS
//for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer
for(i=0; i < 16 ; i++)
{
for(i=0; i < 16 ; i++) {
_irqL irqL;
_list *phead, *plist;
union recv_frame *prframe;
_queue *ppending_recvframe_queue;
_queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
preorder_ctrl = &psta->recvreorder_ctrl[i];
_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
preorder_ctrl = &psta->recvreorder_ctrl[i];
_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
_enter_critical_bh(&ppending_recvframe_queue->lock, &irqL);
phead = get_list_head(ppending_recvframe_queue);
plist = get_next(phead);
while(!rtw_is_list_empty(phead))
{
while(!rtw_is_list_empty(phead)) {
prframe = LIST_CONTAINOR(plist, union recv_frame, u);
plist = get_next(plist);
rtw_list_delete(&(prframe->u.hdr.list));
rtw_free_recvframe(prframe, pfree_recv_queue);
}
_exit_critical_bh(&ppending_recvframe_queue->lock, &irqL);
}
if (!(psta->state & WIFI_AP_STATE))
rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _FALSE);
//release mac id for non-bc/mc station,
rtw_release_macid(pstapriv->padapter, psta);
#ifdef CONFIG_AP_MODE
/*
_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
rtw_list_delete(&psta->asoc_list);
_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
*/
/*
_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
rtw_list_delete(&psta->asoc_list);
_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL0);
*/
_enter_critical_bh(&pstapriv->auth_list_lock, &irqL0);
if (!rtw_is_list_empty(&psta->auth_list)) {
rtw_list_delete(&psta->auth_list);
pstapriv->auth_list_cnt--;
}
_exit_critical_bh(&pstapriv->auth_list_lock, &irqL0);
psta->expire_to = 0;
#ifdef CONFIG_ATMEL_RC_PATCH
psta->flag_atmel_rc = 0;
@@ -608,38 +606,39 @@ _func_enter_;
psta->has_legacy_ac = 0;
#ifdef CONFIG_NATIVEAP_MLME
pstapriv->sta_dz_bitmap &=~BIT(psta->aid);
pstapriv->tim_bitmap &=~BIT(psta->aid);
pstapriv->tim_bitmap &=~BIT(psta->aid);
//rtw_indicate_sta_disassoc_event(padapter, psta);
if ((psta->aid >0)&&(pstapriv->sta_aid[psta->aid - 1] == psta))
{
if ((psta->aid >0)&&(pstapriv->sta_aid[psta->aid - 1] == psta)) {
pstapriv->sta_aid[psta->aid - 1] = NULL;
psta->aid = 0;
}
#endif // CONFIG_NATIVEAP_MLME
}
#endif // CONFIG_NATIVEAP_MLME
#ifdef CONFIG_TX_MCAST2UNI
psta->under_exist_checking = 0;
#endif // CONFIG_TX_MCAST2UNI
#endif // CONFIG_AP_MODE
#endif // CONFIG_AP_MODE
_rtw_spinlock_free(&psta->lock);
_rtw_spinlock_free(&psta->lock);
//_enter_critical_bh(&(pfree_sta_queue->lock), &irqL0);
_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue));
_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
//_exit_critical_bh(&(pfree_sta_queue->lock), &irqL0);
exit:
_func_exit_;
_func_exit_;
return _SUCCESS;
}
// free all stainfo which in sta_hash[all]
@@ -651,41 +650,54 @@ void rtw_free_all_stainfo(_adapter *padapter)
struct sta_info *psta = NULL;
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info* pbcmc_stainfo =rtw_get_bcmc_stainfo( padapter);
_func_enter_;
u8 free_sta_num = 0;
char free_sta_list[NUM_STA];
int stainfo_offset;
_func_enter_;
if(pstapriv->asoc_sta_count==1)
goto exit;
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
for(index=0; index< NUM_STA; index++)
{
for(index=0; index< NUM_STA; index++) {
phead = &(pstapriv->sta_hash[index]);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list);
plist = get_next(plist);
if(pbcmc_stainfo!=psta)
rtw_free_stainfo(padapter , psta);
if(pbcmc_stainfo!=psta) {
rtw_list_delete(&psta->hash_list);
//rtw_free_stainfo(padapter , psta);
stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
if (stainfo_offset_valid(stainfo_offset)) {
free_sta_list[free_sta_num++] = stainfo_offset;
}
}
}
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
exit:
_func_exit_;
for (index = 0; index < free_sta_num; index++) {
psta = rtw_get_stainfo_by_offset(pstapriv, free_sta_list[index]);
rtw_free_stainfo(padapter , psta);
}
exit:
_func_exit_;
}
/* any station allocated can be searched by hash list */
struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr)
{
_irqL irqL;
@@ -693,42 +705,38 @@ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
_list *plist, *phead;
struct sta_info *psta = NULL;
u32 index;
u8 *addr;
const u8 *addr;
u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
const u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
_func_enter_;
_func_enter_;
if(hwaddr==NULL)
return NULL;
if(IS_MCAST(hwaddr))
{
if(IS_MCAST(hwaddr)) {
addr = bc_addr;
}
else
{
} else {
addr = hwaddr;
}
index = wifi_mac_hash(addr);
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
phead = &(pstapriv->sta_hash[index]);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
if ((_rtw_memcmp(psta->hwaddr, addr, ETH_ALEN))== _TRUE)
{ // if found the matched address
if ((_rtw_memcmp(psta->hwaddr, addr, ETH_ALEN))== _TRUE) {
// if found the matched address
break;
}
psta=NULL;
@@ -736,9 +744,9 @@ _func_enter_;
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
_func_exit_;
_func_exit_;
return psta;
}
u32 rtw_init_bcmc_stainfo(_adapter* padapter)
@@ -748,36 +756,33 @@ u32 rtw_init_bcmc_stainfo(_adapter* padapter)
struct tx_servq *ptxservq;
u32 res=_SUCCESS;
NDIS_802_11_MAC_ADDRESS bcast_addr= {0xff,0xff,0xff,0xff,0xff,0xff};
struct sta_priv *pstapriv = &padapter->stapriv;
//_queue *pstapending = &padapter->xmitpriv.bm_pending;
_func_enter_;
//_queue *pstapending = &padapter->xmitpriv.bm_pending;
_func_enter_;
psta = rtw_alloc_stainfo(pstapriv, bcast_addr);
if(psta==NULL){
if(psta==NULL) {
res=_FAIL;
RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("rtw_alloc_stainfo fail"));
goto exit;
}
// default broadcast & multicast use macid 1
psta->mac_id = 1;
ptxservq= &(psta->sta_xmitpriv.be_q);
/*
_enter_critical(&pstapending->lock, &irqL0);
/*
_enter_critical(&pstapending->lock, &irqL0);
if (rtw_is_list_empty(&ptxservq->tx_pending))
rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(pstapending));
if (rtw_is_list_empty(&ptxservq->tx_pending))
rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(pstapending));
_exit_critical(&pstapending->lock, &irqL0);
*/
_exit_critical(&pstapending->lock, &irqL0);
*/
exit:
_func_exit_;
_func_exit_;
return _SUCCESS;
}
@@ -787,10 +792,10 @@ struct sta_info* rtw_get_bcmc_stainfo(_adapter* padapter)
{
struct sta_info *psta;
struct sta_priv *pstapriv = &padapter->stapriv;
u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
_func_enter_;
psta = rtw_get_stainfo(pstapriv, bc_addr);
_func_exit_;
const u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff};
_func_enter_;
psta = rtw_get_stainfo(pstapriv, bc_addr);
_func_exit_;
return psta;
}
@@ -806,40 +811,32 @@ u8 rtw_access_ctrl(_adapter *padapter, u8 *mac_addr)
struct sta_priv *pstapriv = &padapter->stapriv;
struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
_queue *pacl_node_q =&pacl_list->acl_node_q;
_enter_critical_bh(&(pacl_node_q->lock), &irqL);
phead = get_list_head(pacl_node_q);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list);
plist = get_next(plist);
if(_rtw_memcmp(paclnode->addr, mac_addr, ETH_ALEN))
{
if(paclnode->valid == _TRUE)
{
if(_rtw_memcmp(paclnode->addr, mac_addr, ETH_ALEN)) {
if(paclnode->valid == _TRUE) {
match = _TRUE;
break;
}
}
}
_exit_critical_bh(&(pacl_node_q->lock), &irqL);
if(pacl_list->mode == 1)//accept unless in deny list
{
res = (match == _TRUE) ? _FALSE:_TRUE;
}
else if(pacl_list->mode == 2)//deny unless in accept list
{
res = (match == _TRUE) ? _TRUE:_FALSE;
}
}
else
{
res = _TRUE;
}
_exit_critical_bh(&(pacl_node_q->lock), &irqL);
if(pacl_list->mode == 1) { //accept unless in deny list
res = (match == _TRUE) ? _FALSE:_TRUE;
} else if(pacl_list->mode == 2) { //deny unless in accept list
res = (match == _TRUE) ? _TRUE:_FALSE;
} else {
res = _TRUE;
}
#endif
return res;

5805
backports/drivers/realtek/rtl8812au/core/rtw_tdls.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

283
backports/drivers/realtek/rtl8812au/core/rtw_vht.c Executable file → Normal file
View File

@@ -1,7 +1,7 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
@@ -22,48 +22,60 @@
#include <drv_types.h>
#ifdef CONFIG_80211AC_VHT
// 20/40/80, ShortGI, MCS Rate
const u16 VHT_MCS_DATA_RATE[3][2][30] =
{ { {13, 26, 39, 52, 78, 104, 117, 130, 156, 156,
26, 52, 78, 104, 156, 208, 234, 260, 312, 312,
39, 78, 117, 156, 234, 312, 351, 390, 468, 520}, // Long GI, 20MHz
{14, 29, 43, 58, 87, 116, 130, 144, 173, 173,
// 20/40/80, ShortGI, MCS Rate
const u16 VHT_MCS_DATA_RATE[3][2][30] = {
{ {
13, 26, 39, 52, 78, 104, 117, 130, 156, 156,
26, 52, 78, 104, 156, 208, 234, 260, 312, 312,
39, 78, 117, 156, 234, 312, 351, 390, 468, 520
}, // Long GI, 20MHz
{
14, 29, 43, 58, 87, 116, 130, 144, 173, 173,
29, 58, 87, 116, 173, 231, 260, 289, 347, 347,
43, 87, 130, 173, 260, 347,390, 433, 520, 578} }, // Short GI, 20MHz
{ {27, 54, 81, 108, 162, 216, 243, 270, 324, 360,
43, 87, 130, 173, 260, 347,390, 433, 520, 578
}
}, // Short GI, 20MHz
{ {
27, 54, 81, 108, 162, 216, 243, 270, 324, 360,
54, 108, 162, 216, 324, 432, 486, 540, 648, 720,
81, 162, 243, 324, 486, 648, 729, 810, 972, 1080}, // Long GI, 40MHz
{30, 60, 90, 120, 180, 240, 270, 300,360, 400,
81, 162, 243, 324, 486, 648, 729, 810, 972, 1080
}, // Long GI, 40MHz
{
30, 60, 90, 120, 180, 240, 270, 300,360, 400,
60, 120, 180, 240, 360, 480, 540, 600, 720, 800,
90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200}}, // Short GI, 40MHz
{ {59, 117, 176, 234, 351, 468, 527, 585, 702, 780,
90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200
}
}, // Short GI, 40MHz
{ {
59, 117, 176, 234, 351, 468, 527, 585, 702, 780,
117, 234, 351, 468, 702, 936, 1053, 1170, 1404, 1560,
176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2106}, // Long GI, 80MHz
{65, 130, 195, 260, 390, 520, 585, 650, 780, 867,
176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2106
}, // Long GI, 80MHz
{
65, 130, 195, 260, 390, 520, 585, 650, 780, 867,
130, 260, 390, 520, 780, 1040, 1170, 1300, 1560,1734,
195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2340} } // Short GI, 80MHz
};
195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2340
}
} // Short GI, 80MHz
};
u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map)
{
u8 i, j;
u8 bit_map;
u8 vht_mcs_rate = 0;
for(i = 0; i < 2; i++)
{
if(pvht_mcs_map[i] != 0xff)
{
for(j = 0; j < 8; j += 2)
{
for(i = 0; i < 2; i++) {
if(pvht_mcs_map[i] != 0xff) {
for(j = 0; j < 8; j += 2) {
bit_map = (pvht_mcs_map[i] >> j) & 3;
if(bit_map != 3)
vht_mcs_rate = MGN_VHT1SS_MCS7 + 10*j/2 + i*40 + bit_map; //VHT rate indications begin from 0x90
}
}
}
//DBG_871X("HighestVHTMCSRate is %x\n", vht_mcs_rate);
return vht_mcs_rate;
}
@@ -73,21 +85,18 @@ u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map)
u8 i, j;
u8 bit_map;
u8 nss = 0;
for(i = 0; i < 2; i++)
{
if(pvht_mcs_map[i] != 0xff)
{
for(j = 0; j < 8; j += 2)
{
for(i = 0; i < 2; i++) {
if(pvht_mcs_map[i] != 0xff) {
for(j = 0; j < 8; j += 2) {
bit_map = (pvht_mcs_map[i] >> j) & 3;
if(bit_map != 3)
nss++;
}
}
}
//DBG_871X("%s : %dSS\n", __FUNCTION__, nss);
return nss;
}
@@ -96,24 +105,22 @@ void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map)
{
u8 i, j;
u8 cur_rate, target_rate;
for(i = 0; i < 2; i++)
{
for(i = 0; i < 2; i++) {
target_mcs_map[i] = 0;
for(j = 0; j < 8; j+=2)
{
for(j = 0; j < 8; j+=2) {
cur_rate = (cur_mcs_map[i] >> j) & 3;
if(cur_rate == 3) //0x3 indicates not supported that num of SS
target_rate = 3;
else if(nss <= ((j/2)+i*4))
target_rate = 3;
else
else
target_rate = cur_rate;
target_mcs_map[i] |= (target_rate << j);
}
}
//DBG_871X("%s : %dSS\n", __FUNCTION__, nss);
}
@@ -139,14 +146,12 @@ void rtw_vht_use_default_setting(_adapter *padapter)
// LDPC support
rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport);
CLEAR_FLAGS(pvhtpriv->ldpc_cap);
if(bHwLDPCSupport)
{
if(bHwLDPCSupport) {
if(TEST_FLAG(pregistrypriv->ldpc_cap, BIT0))
SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX);
}
rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport);
if(bHwLDPCSupport)
{
if(bHwLDPCSupport) {
if(TEST_FLAG(pregistrypriv->ldpc_cap, BIT1))
SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX);
}
@@ -156,14 +161,12 @@ void rtw_vht_use_default_setting(_adapter *padapter)
// STBC
rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport);
CLEAR_FLAGS(pvhtpriv->stbc_cap);
if(bHwSTBCSupport)
{
if(bHwSTBCSupport) {
if(TEST_FLAG(pregistrypriv->stbc_cap, BIT1))
SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX);
}
rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport);
if(bHwSTBCSupport)
{
if(bHwSTBCSupport) {
if(TEST_FLAG(pregistrypriv->stbc_cap, BIT0))
SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX);
}
@@ -174,13 +177,11 @@ void rtw_vht_use_default_setting(_adapter *padapter)
rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer);
rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee);
CLEAR_FLAGS(pvhtpriv->beamform_cap);
if(TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer)
{
if(TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) {
SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
DBG_871X("[VHT] Support Beamformer\n");
}
if(TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee)
{
if(TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) {
SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
DBG_871X("[VHT] Support Beamformee\n");
}
@@ -195,40 +196,23 @@ void rtw_vht_use_default_setting(_adapter *padapter)
pvhtpriv->vht_mcs_map[0] = 0xfa; //support 1SS MCS 0~9 2SS MCS 0~9
pvhtpriv->vht_mcs_map[1] = 0xff;
if(pregistrypriv->vht_rate_sel == 1)
{
if(pregistrypriv->vht_rate_sel == 1) {
pvhtpriv->vht_mcs_map[0] = 0xfc; // support 1SS MCS 0~7
}
else if(pregistrypriv->vht_rate_sel == 2)
{
} else if(pregistrypriv->vht_rate_sel == 2) {
pvhtpriv->vht_mcs_map[0] = 0xfd; // Support 1SS MCS 0~8
}
else if(pregistrypriv->vht_rate_sel == 3)
{
} else if(pregistrypriv->vht_rate_sel == 3) {
pvhtpriv->vht_mcs_map[0] = 0xfe; // Support 1SS MCS 0~9
}
else if(pregistrypriv->vht_rate_sel == 4)
{
} else if(pregistrypriv->vht_rate_sel == 4) {
pvhtpriv->vht_mcs_map[0] = 0xf0; // support 1SS MCS 0~7 2SS MCS 0~7
}
else if(pregistrypriv->vht_rate_sel == 5)
{
} else if(pregistrypriv->vht_rate_sel == 5) {
pvhtpriv->vht_mcs_map[0] = 0xf5; // support 1SS MCS 0~8 2SS MCS 0~8
}
else if(pregistrypriv->vht_rate_sel == 6)
{
} else if(pregistrypriv->vht_rate_sel == 6) {
pvhtpriv->vht_mcs_map[0] = 0xfa; // support 1SS MCS 0~9 2SS MCS 0~9
}
else if(pregistrypriv->vht_rate_sel == 7)
{
} else if(pregistrypriv->vht_rate_sel == 7) {
pvhtpriv->vht_mcs_map[0] = 0xf8; // support 1SS MCS 0-7 2SS MCS 0~9
}
else if(pregistrypriv->vht_rate_sel == 8)
{
} else if(pregistrypriv->vht_rate_sel == 8) {
pvhtpriv->vht_mcs_map[0] = 0xf9; // support 1SS MCS 0-8 2SS MCS 0~9
}
else if(pregistrypriv->vht_rate_sel == 9)
{
} else if(pregistrypriv->vht_rate_sel == 9) {
pvhtpriv->vht_mcs_map[0] = 0xf4; // support 1SS MCS 0-7 2SS MCS 0~8
}
@@ -240,22 +224,21 @@ u32 rtw_vht_rate_to_bitmap(u8 *pVHTRate)
u8 i,j , tmpRate;
u32 RateBitmap = 0;
for(i = j= 0; i < 4; i+=2, j+=10)
{
for(i = j= 0; i < 4; i+=2, j+=10) {
tmpRate = (pVHTRate[0] >> i) & 3;
switch(tmpRate){
switch(tmpRate) {
case 2:
RateBitmap = RateBitmap | (0x03ff << j);
RateBitmap = RateBitmap | (0x03ff << j);
break;
case 1:
RateBitmap = RateBitmap | (0x01ff << j);
break;
break;
case 0:
RateBitmap = RateBitmap | (0x00ff << j);
break;
break;
default:
break;
@@ -272,7 +255,7 @@ void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta)
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv;
struct vht_priv *pvhtpriv_sta = &psta->vhtpriv;
struct ht_priv *phtpriv_sta = &psta->htpriv;
//struct ht_priv *phtpriv_sta = &psta->htpriv;
u8 cur_ldpc_cap=0, cur_stbc_cap=0, cur_beamform_cap=0, bw_mode = 0;
u8 *pcap_mcs;
@@ -281,15 +264,17 @@ void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta)
}
bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify);
if (bw_mode > psta->bw_mode)
psta->bw_mode = bw_mode;
//if (bw_mode > psta->bw_mode)
psta->bw_mode = bw_mode;
// B4 Rx LDPC
if (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX)) {
SET_FLAG(cur_ldpc_cap, GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap) ? (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX) : 0);
if (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap)) {
SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
DBG_871X("Current STA(%d) VHT LDPC = %02X\n", psta->aid, cur_ldpc_cap);
}
pvhtpriv_sta->ldpc_cap = cur_ldpc_cap;
DBG_871X("Current STA VHT LDPC = %02X\n", cur_ldpc_cap);
if (psta->bw_mode > pmlmeext->cur_bwmode)
psta->bw_mode = pmlmeext->cur_bwmode;
@@ -297,37 +282,36 @@ void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta)
if (psta->bw_mode == CHANNEL_WIDTH_80) {
// B5 Short GI for 80 MHz
pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
DBG_871X("Current STA ShortGI80MHz = %d\n", pvhtpriv_sta->sgi_80m);
//DBG_871X("Current STA ShortGI80MHz = %d\n", pvhtpriv_sta->sgi_80m);
} else if (psta->bw_mode >= CHANNEL_WIDTH_160) {
// B5 Short GI for 80 MHz
pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
DBG_871X("Current STA ShortGI160MHz = %d\n", pvhtpriv_sta->sgi_80m);
//DBG_871X("Current STA ShortGI160MHz = %d\n", pvhtpriv_sta->sgi_80m);
}
// B8 B9 B10 Rx STBC
if (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) &&
GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap))
{
SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
if (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) &&
GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap)) {
SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
DBG_871X("Current STA(%d) VHT STBC = %02X\n", psta->aid, cur_stbc_cap);
}
pvhtpriv_sta->stbc_cap = cur_stbc_cap;
DBG_871X("Current STA VHT STBC = %02X\n", cur_stbc_cap);
// B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee
if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap))
{
if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap)) {
SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
}
// B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer
if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap))
{
GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap)) {
SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
}
pvhtpriv_sta->beamform_cap = cur_beamform_cap;
DBG_871X("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap);
if (cur_beamform_cap) {
DBG_871X("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->aid, cur_beamform_cap);
}
// B23 B24 B25 Maximum A-MPDU Length Exponent
pvhtpriv_sta->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pvhtpriv_sta->vht_cap);
@@ -370,40 +354,40 @@ void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
pmlmeinfo->VHT_enable = 1;
// B4 Rx LDPC
if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX)) {
SET_FLAG(cur_ldpc_cap, GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data) ? (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX) : 0);
if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data)) {
SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
DBG_871X("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap);
}
pvhtpriv->ldpc_cap = cur_ldpc_cap;
DBG_871X("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap);
// B5 Short GI for 80 MHz
pvhtpriv->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pIE->data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE;
DBG_871X("Current ShortGI80MHz = %d\n", pvhtpriv->sgi_80m);
//DBG_871X("Current ShortGI80MHz = %d\n", pvhtpriv->sgi_80m);
// B8 B9 B10 Rx STBC
if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) &&
GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data))
{
SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) &&
GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data)) {
SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
DBG_871X("Current VHT STBC Setting = %02X\n", cur_stbc_cap);
}
pvhtpriv->stbc_cap = cur_stbc_cap;
DBG_871X("Current VHT STBC Setting = %02X\n", cur_stbc_cap);
// B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data))
{
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) {
SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
}
// B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data))
{
GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) {
SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
}
pvhtpriv->beamform_cap = cur_beamform_cap;
DBG_871X("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap);
if (cur_beamform_cap) {
DBG_871X("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap);
}
// B23 B24 B25 Maximum A-MPDU Length Exponent
pvhtpriv->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pIE->data);
@@ -437,7 +421,7 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta)
struct sta_info *psta = (struct sta_info *)sta;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
//struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
u8 target_bw;
u8 target_rxss, current_rxss;
u8 update_ra = _FALSE;
@@ -462,7 +446,7 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta)
rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map);
_rtw_memcpy(psta->vhtpriv.vht_mcs_map, vht_mcs_map, 2);
rtw_hal_update_sta_rate_mask(padapter, psta);
}
@@ -474,8 +458,8 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta)
u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel)
{
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
//struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
//struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
//struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
u8 ChnlWidth, center_freq, bw_mode;
u32 len = 0;
@@ -485,25 +469,23 @@ u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel)
bw_mode = pregistrypriv->bw_mode >> 4;
if (bw_mode >= CHANNEL_WIDTH_80)
{
if (bw_mode >= CHANNEL_WIDTH_80) {
center_freq = rtw_get_center_ch(channel, bw_mode, HAL_PRIME_CHNL_OFFSET_LOWER);
ChnlWidth = 1;
}
else
{
} else {
center_freq = 0;
ChnlWidth = 0;
}
SET_VHT_OPERATION_ELE_CHL_WIDTH(operation, ChnlWidth);
//center frequency
SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(operation, center_freq);//Todo: need to set correct center channel
SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(operation,0);
SET_VHT_OPERATION_ELE_BASIC_MCS_SET(operation, 0xFFFF);
operation[3] = 0xff;
operation[4] = 0xff;
pbuf = rtw_set_ie(pbuf, EID_VHTOperation, 5, operation, &len);
rtw_set_ie(pbuf, EID_VHTOperation, 5, operation, &len);
return len;
}
@@ -553,8 +535,7 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0); //indicate we don't support neither 160M nor 80+80M bandwidth.
// B4 Rx LDPC
if(TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX))
{
if(TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) {
SET_VHT_CAPABILITY_ELE_RX_LDPC(pcap, 1);
}
@@ -565,34 +546,29 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
//SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pcap, pvhtpriv->sgi_80m? 1 : 0);
// B7 Tx STBC
if(TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX))
{
if(TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) {
SET_VHT_CAPABILITY_ELE_TX_STBC(pcap, 1);
}
// B8 B9 B10 Rx STBC
if(TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX))
{
if(TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) {
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
if ((rf_type == RF_2T2R) || (rf_type == RF_1T2R)) {
SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, 2);
}
else if (rf_type == RF_1T1R) {
} else if (rf_type == RF_1T1R) {
SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, 1);
}
}
// B11 SU Beamformer Capable
if(TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE))
{
if(TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1);
// B16 17 18 Number of Sounding Dimensions
SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, 1);
}
// B12 SU Beamformee Capable
if(TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE))
{
if(TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1);
// B13 14 15 Compressed Steering Number of Beamformer Antennas Supported
SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, 1);
@@ -607,12 +583,9 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
// B22 +HTC-VHT Capable
SET_VHT_CAPABILITY_ELE_HTC_VHT(pcap, 1);
// B23 24 25 Maximum A-MPDU Length Exponent
if (pregistrypriv->ampdu_factor != 0xFE)
{
if (pregistrypriv->ampdu_factor != 0xFE) {
SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, pregistrypriv->ampdu_factor);
}
else
{
} else {
SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, 7);
}
// B26 27 VHT Link Adaptation Capable
@@ -626,7 +599,7 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
bw = (pregistrypriv->bw_mode >> 4);
HighestRate = VHT_MCS_DATA_RATE[bw][pvhtpriv->sgi_80m][((pvhtpriv->vht_highest_rate - MGN_VHT1SS_MCS0)&0x3f)];
HighestRate = (HighestRate+1) >> 1;
HighestRate = (HighestRate+1) >> 1;
SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(pcap, HighestRate); //indicate we support highest rx rate is 600Mbps.
SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(pcap, HighestRate); //indicate we support highest tx rate is 600Mbps.
@@ -650,7 +623,7 @@ u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_le
p = rtw_get_ie(in_ie+12, EID_VHTCapability, &ielen, in_len-12);
if (p && ielen>0) {
supported_chnl_width = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p+2);
// VHT Capabilities element
cap_len = rtw_build_vht_cap_ie(padapter, out_ie+*pout_len);
*pout_len += cap_len;
@@ -691,9 +664,9 @@ u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_le
pvhtpriv->vht_option = _TRUE;
}
return (pvhtpriv->vht_option);
}
void VHTOnAssocRsp(_adapter *padapter)
@@ -703,7 +676,7 @@ void VHTOnAssocRsp(_adapter *padapter)
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
u8 ht_AMPDU_len;
DBG_871X("%s\n", __FUNCTION__);
if (!pmlmeinfo->HT_enable)

2577
backports/drivers/realtek/rtl8812au/core/rtw_wapi.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

1838
backports/drivers/realtek/rtl8812au/core/rtw_wapi_sms4.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

3399
backports/drivers/realtek/rtl8812au/core/rtw_wlan_util.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

3094
backports/drivers/realtek/rtl8812au/core/rtw_xmit.c Executable file → Normal file
View File

File diff suppressed because it is too large Load Diff

7
backports/drivers/realtek/rtl8812au/dkms.conf Normal file
View File

@@ -0,0 +1,7 @@
PACKAGE_NAME="rtl8812au"
PACKAGE_VERSION="#MODULE_VERSION#"
MAKE[0]="make KVER=$kernelver"
CLEAN="make clean"
BUILT_MODULE_NAME[0]="rtl8812au"
DEST_MODULE_LOCATION[0]="/kernel/drivers/net"
AUTOINSTALL="yes"

4
backports/drivers/realtek/rtl8812au/fetch.sh Normal file
View File

@@ -0,0 +1,4 @@
#!/bin/bash
if [ "$(md5sum linux-headers-4.0.1-040001_4.0.1-040001.201504290935_all.deb | cut -d ' ' -f 1)" != "d757d51819f8f945ae7715b532ab8d2e" ] ; then wget http://kernel.ubuntu.com/~kernel-ppa/mainline/v4.0.1-vivid/linux-headers-4.0.1-040001-generic_4.0.1-040001.201504290935_i386.deb; else echo "linux-headers-4.0.1-040001_4.0.1-040001.201504290935_all.deb up to date"; fi
if [ "$(md5sum linux-headers-4.0.1-040001-generic_4.0.1-040001.201504290935_i386.deb | cut -d ' ' -f 1)" != "657f07ae89395f9efd62bead00b42fbb" ] ; then wget http://kernel.ubuntu.com/~kernel-ppa/mainline/v4.0.1-vivid/linux-headers-4.0.1-040001-generic_4.0.1-040001.201504290935_i386.deb; else echo "linux-headers-4.0.1-040001-generic_4.0.1-040001.201504290935_i386.deb up to date"; fi
if [ "$(md5sum linux-image-4.0.1-040001-generic_4.0.1-040001.201504290935_i386.deb | cut -d ' ' -f 1)" != "69f423e3888fe56cd5c74658aa7aaea7" ] ; then wget http://kernel.ubuntu.com/~kernel-ppa/mainline/v4.0.1-vivid/linux-image-4.0.1-040001-generic_4.0.1-040001.201504290935_i386.deb; else echo "linux-image-4.0.1-040001-generic_4.0.1-040001.201504290935_i386.deb up to date"; fi

362
backports/drivers/realtek/rtl8812au/hal/HalPwrSeqCmd.c Executable file → Normal file
View File

@@ -1,183 +1,179 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
HalPwrSeqCmd.c
Abstract:
Implement HW Power sequence configuration CMD handling routine for Realtek devices.
Major Change History:
When Who What
---------- --------------- -------------------------------
2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
2011-07-07 Roger Create.
--*/
#include <HalPwrSeqCmd.h>
//
// Description:
// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
//
// Assumption:
// We should follow specific format which was released from HW SD.
//
// 2011.07.07, added by Roger.
//
u8 HalPwrSeqCmdParsing(
PADAPTER padapter,
u8 CutVersion,
u8 FabVersion,
u8 InterfaceType,
WLAN_PWR_CFG PwrSeqCmd[])
{
WLAN_PWR_CFG PwrCfgCmd = {0};
u8 bPollingBit = _FALSE;
u32 AryIdx = 0;
u8 value = 0;
u32 offset = 0;
u32 pollingCount = 0; // polling autoload done.
u32 maxPollingCnt = 5000;
do {
PwrCfgCmd = PwrSeqCmd[AryIdx];
RT_TRACE(_module_hal_init_c_ , _drv_info_,
("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
GET_PWR_CFG_OFFSET(PwrCfgCmd),
GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
GET_PWR_CFG_BASE(PwrCfgCmd),
GET_PWR_CFG_CMD(PwrCfgCmd),
GET_PWR_CFG_MASK(PwrCfgCmd),
GET_PWR_CFG_VALUE(PwrCfgCmd)));
//2 Only Handle the command whose FAB, CUT, and Interface are matched
if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
(GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
(GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType))
{
switch (GET_PWR_CFG_CMD(PwrCfgCmd))
{
case PWR_CMD_READ:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
break;
case PWR_CMD_WRITE:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
#ifdef CONFIG_SDIO_HCI
//
// <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
// 2011.07.07.
//
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
{
// Read Back SDIO Local value
value = SdioLocalCmd52Read1Byte(padapter, offset);
value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
// Write Back SDIO Local value
SdioLocalCmd52Write1Byte(padapter, offset, value);
}
else
#endif
{
#ifdef CONFIG_GSPI_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
offset = SPI_LOCAL_OFFSET | offset;
#endif
// Read the value from system register
value = rtw_read8(padapter, offset);
value=value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));
value=value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));
// Write the value back to sytem register
rtw_write8(padapter, offset, value);
}
break;
case PWR_CMD_POLLING:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
bPollingBit = _FALSE;
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
#ifdef CONFIG_GSPI_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
offset = SPI_LOCAL_OFFSET | offset;
#endif
do {
#ifdef CONFIG_SDIO_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
value = SdioLocalCmd52Read1Byte(padapter, offset);
else
#endif
value = rtw_read8(padapter, offset);
value=value&GET_PWR_CFG_MASK(PwrCfgCmd);
if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
bPollingBit = _TRUE;
else
rtw_udelay_os(10);
if (pollingCount++ > maxPollingCnt) {
DBG_871X("Fail to polling Offset[%#x]=%02x\n", offset, value);
return _FALSE;
}
} while (!bPollingBit);
break;
case PWR_CMD_DELAY:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
else
rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
break;
case PWR_CMD_END:
// When this command is parsed, end the process
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
return _TRUE;
break;
default:
RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
break;
}
}
AryIdx++;//Add Array Index
}while(1);
return _TRUE;
}
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
HalPwrSeqCmd.c
Abstract:
Implement HW Power sequence configuration CMD handling routine for Realtek devices.
Major Change History:
When Who What
---------- --------------- -------------------------------
2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
2011-07-07 Roger Create.
--*/
#include <HalPwrSeqCmd.h>
//
// Description:
// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
//
// Assumption:
// We should follow specific format which was released from HW SD.
//
// 2011.07.07, added by Roger.
//
u8 HalPwrSeqCmdParsing(
PADAPTER padapter,
u8 CutVersion,
u8 FabVersion,
u8 InterfaceType,
WLAN_PWR_CFG PwrSeqCmd[])
{
WLAN_PWR_CFG PwrCfgCmd = {0};
u8 bPollingBit = _FALSE;
u32 AryIdx = 0;
u8 value = 0;
u32 offset = 0;
u32 pollingCount = 0; // polling autoload done.
u32 maxPollingCnt = 5000;
do {
PwrCfgCmd = PwrSeqCmd[AryIdx];
RT_TRACE(_module_hal_init_c_ , _drv_info_,
("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
GET_PWR_CFG_OFFSET(PwrCfgCmd),
GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
GET_PWR_CFG_BASE(PwrCfgCmd),
GET_PWR_CFG_CMD(PwrCfgCmd),
GET_PWR_CFG_MASK(PwrCfgCmd),
GET_PWR_CFG_VALUE(PwrCfgCmd)));
//2 Only Handle the command whose FAB, CUT, and Interface are matched
if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
(GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
(GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
case PWR_CMD_READ:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
break;
case PWR_CMD_WRITE:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
#ifdef CONFIG_SDIO_HCI
//
// <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
// 2011.07.07.
//
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
// Read Back SDIO Local value
value = SdioLocalCmd52Read1Byte(padapter, offset);
value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
// Write Back SDIO Local value
SdioLocalCmd52Write1Byte(padapter, offset, value);
} else
#endif
{
#ifdef CONFIG_GSPI_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
offset = SPI_LOCAL_OFFSET | offset;
#endif
// Read the value from system register
value = rtw_read8(padapter, offset);
value=value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));
value=value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));
// Write the value back to sytem register
rtw_write8(padapter, offset, value);
}
break;
case PWR_CMD_POLLING:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
bPollingBit = _FALSE;
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
#ifdef CONFIG_GSPI_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
offset = SPI_LOCAL_OFFSET | offset;
#endif
do {
#ifdef CONFIG_SDIO_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
value = SdioLocalCmd52Read1Byte(padapter, offset);
else
#endif
value = rtw_read8(padapter, offset);
value=value&GET_PWR_CFG_MASK(PwrCfgCmd);
if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
bPollingBit = _TRUE;
else
rtw_udelay_os(10);
if (pollingCount++ > maxPollingCnt) {
DBG_871X_LEVEL(_drv_always_, "HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
return _FALSE;
}
} while (!bPollingBit);
break;
case PWR_CMD_DELAY:
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
else
rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
break;
case PWR_CMD_END:
// When this command is parsed, end the process
RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
return _TRUE;
break;
default:
RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
break;
}
}
AryIdx++;//Add Array Index
} while(1);
return _TRUE;
}

3762
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8188c2Ant.c Executable file → Normal file
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293
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8188c2Ant.h Executable file → Normal file
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@@ -1,144 +1,149 @@
//===========================================
// The following is for 8188C 2Ant BT Co-exist definition
//===========================================
#define BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT 6
typedef enum _BT_INFO_SRC_8188C_2ANT{
BT_INFO_SRC_8188C_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8188C_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8188C_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8188C_2ANT_MAX
}BT_INFO_SRC_8188C_2ANT,*PBT_INFO_SRC_8188C_2ANT;
typedef enum _BT_8188C_2ANT_BT_STATUS{
BT_8188C_2ANT_BT_STATUS_IDLE = 0x0,
BT_8188C_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8188C_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8188C_2ANT_BT_STATUS_MAX
}BT_8188C_2ANT_BT_STATUS,*PBT_8188C_2ANT_BT_STATUS;
typedef enum _BT_8188C_2ANT_COEX_ALGO{
BT_8188C_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8188C_2ANT_COEX_ALGO_SCO = 0x1,
BT_8188C_2ANT_COEX_ALGO_HID = 0x2,
BT_8188C_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8188C_2ANT_COEX_ALGO_PAN = 0x4,
BT_8188C_2ANT_COEX_ALGO_HID_A2DP = 0x5,
BT_8188C_2ANT_COEX_ALGO_HID_PAN = 0x6,
BT_8188C_2ANT_COEX_ALGO_PAN_A2DP = 0x7,
BT_8188C_2ANT_COEX_ALGO_MAX
}BT_8188C_2ANT_COEX_ALGO,*PBT_8188C_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8188C_2ANT{
// fw mechanism
BOOLEAN bPreBalanceOn;
BOOLEAN bCurBalanceOn;
// diminishWifi
BOOLEAN bPreDacOn;
BOOLEAN bCurDacOn;
BOOLEAN bPreInterruptOn;
BOOLEAN bCurInterruptOn;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bPreNavOn;
BOOLEAN bCurNavOn;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
//u4Byte preVal0x6c0;
//u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u4Byte preVal0x6cc;
u4Byte curVal0x6cc;
//BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
//u1Byte btStatus;
//u1Byte wifiChnlInfo[3];
} COEX_DM_8188C_2ANT, *PCOEX_DM_8188C_2ANT;
typedef struct _COEX_STA_8188C_2ANT{
u1Byte preWifiRssiState[4];
BOOLEAN bBtBusy;
BOOLEAN bBtUplink;
BOOLEAN bBtDownLink;
BOOLEAN bA2dpBusy;
}COEX_STA_8188C_2ANT, *PCOEX_STA_8188C_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8188c2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8188c2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8188c2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8188c2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8188c2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8188c2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
//===========================================
// The following is for 8188C 2Ant BT Co-exist definition
//===========================================
#define BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT 6
typedef enum _BT_INFO_SRC_8188C_2ANT {
BT_INFO_SRC_8188C_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8188C_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8188C_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8188C_2ANT_MAX
} BT_INFO_SRC_8188C_2ANT,*PBT_INFO_SRC_8188C_2ANT;
typedef enum _BT_8188C_2ANT_BT_STATUS {
BT_8188C_2ANT_BT_STATUS_IDLE = 0x0,
BT_8188C_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8188C_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8188C_2ANT_BT_STATUS_MAX
} BT_8188C_2ANT_BT_STATUS,*PBT_8188C_2ANT_BT_STATUS;
typedef enum _BT_8188C_2ANT_COEX_ALGO {
BT_8188C_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8188C_2ANT_COEX_ALGO_SCO = 0x1,
BT_8188C_2ANT_COEX_ALGO_HID = 0x2,
BT_8188C_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8188C_2ANT_COEX_ALGO_PAN = 0x4,
BT_8188C_2ANT_COEX_ALGO_HID_A2DP = 0x5,
BT_8188C_2ANT_COEX_ALGO_HID_PAN = 0x6,
BT_8188C_2ANT_COEX_ALGO_PAN_A2DP = 0x7,
BT_8188C_2ANT_COEX_ALGO_MAX
} BT_8188C_2ANT_COEX_ALGO,*PBT_8188C_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8188C_2ANT {
// fw mechanism
BOOLEAN bPreBalanceOn;
BOOLEAN bCurBalanceOn;
// diminishWifi
BOOLEAN bPreDacOn;
BOOLEAN bCurDacOn;
BOOLEAN bPreInterruptOn;
BOOLEAN bCurInterruptOn;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bPreNavOn;
BOOLEAN bCurNavOn;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
//u4Byte preVal0x6c0;
//u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u4Byte preVal0x6cc;
u4Byte curVal0x6cc;
//BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
//u1Byte btStatus;
//u1Byte wifiChnlInfo[3];
} COEX_DM_8188C_2ANT, *PCOEX_DM_8188C_2ANT;
typedef struct _COEX_STA_8188C_2ANT {
u1Byte preWifiRssiState[4];
BOOLEAN bBtBusy;
BOOLEAN bBtUplink;
BOOLEAN bBtDownLink;
BOOLEAN bA2dpBusy;
} COEX_STA_8188C_2ANT, *PCOEX_STA_8188C_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8188c2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8188c2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8188c2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8188c2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8188c2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8188c2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8188c2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8188c2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

3790
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8192d2Ant.c Executable file → Normal file
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335
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8192d2Ant.h Executable file → Normal file
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@@ -1,165 +1,170 @@
//===========================================
// The following is for 8192D 2Ant BT Co-exist definition
//===========================================
#define BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT 6
typedef enum _BT_INFO_SRC_8192D_2ANT{
BT_INFO_SRC_8192D_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8192D_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8192D_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8192D_2ANT_MAX
}BT_INFO_SRC_8192D_2ANT,*PBT_INFO_SRC_8192D_2ANT;
typedef enum _BT_8192D_2ANT_BT_STATUS{
BT_8192D_2ANT_BT_STATUS_IDLE = 0x0,
BT_8192D_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8192D_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8192D_2ANT_BT_STATUS_MAX
}BT_8192D_2ANT_BT_STATUS,*PBT_8192D_2ANT_BT_STATUS;
typedef enum _BT_8192D_2ANT_COEX_ALGO{
BT_8192D_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8192D_2ANT_COEX_ALGO_SCO = 0x1,
BT_8192D_2ANT_COEX_ALGO_HID = 0x2,
BT_8192D_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8192D_2ANT_COEX_ALGO_PAN = 0x4,
BT_8192D_2ANT_COEX_ALGO_HID_A2DP = 0x5,
BT_8192D_2ANT_COEX_ALGO_HID_PAN = 0x6,
BT_8192D_2ANT_COEX_ALGO_PAN_A2DP = 0x7,
BT_8192D_2ANT_COEX_ALGO_MAX
}BT_8192D_2ANT_COEX_ALGO,*PBT_8192D_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8192D_2ANT{
// fw mechanism
BOOLEAN bPreBalanceOn;
BOOLEAN bCurBalanceOn;
// diminishWifi
BOOLEAN bPreDacOn;
BOOLEAN bCurDacOn;
BOOLEAN bPreInterruptOn;
BOOLEAN bCurInterruptOn;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bPreNavOn;
BOOLEAN bCurNavOn;
//BOOLEAN bPreDecBtPwr;
//BOOLEAN bCurDecBtPwr;
//u1Byte preFwDacSwingLvl;
//u1Byte curFwDacSwingLvl;
//BOOLEAN bCurIgnoreWlanAct;
//BOOLEAN bPreIgnoreWlanAct;
//u1Byte prePsTdma;
//u1Byte curPsTdma;
//u1Byte psTdmaPara[5];
//u1Byte psTdmaDuAdjType;
//BOOLEAN bResetTdmaAdjust;
//BOOLEAN bPrePsTdmaOn;
//BOOLEAN bCurPsTdmaOn;
//BOOLEAN bPreBtAutoReport;
//BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
//u4Byte preVal0x6c0;
//u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u4Byte preVal0x6cc;
u4Byte curVal0x6cc;
//BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
//u1Byte btStatus;
//u1Byte wifiChnlInfo[3];
} COEX_DM_8192D_2ANT, *PCOEX_DM_8192D_2ANT;
typedef struct _COEX_STA_8192D_2ANT{
u1Byte preWifiRssiState[4];
BOOLEAN bBtBusy;
BOOLEAN bBtUplink;
BOOLEAN bBtDownLink;
BOOLEAN bA2dpBusy;
}COEX_STA_8192D_2ANT, *PCOEX_STA_8192D_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8192d2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192d2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192d2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192d2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192d2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8192d2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
//===========================================
// The following is for 8192D 2Ant BT Co-exist definition
//===========================================
#define BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT 6
typedef enum _BT_INFO_SRC_8192D_2ANT {
BT_INFO_SRC_8192D_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8192D_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8192D_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8192D_2ANT_MAX
} BT_INFO_SRC_8192D_2ANT,*PBT_INFO_SRC_8192D_2ANT;
typedef enum _BT_8192D_2ANT_BT_STATUS {
BT_8192D_2ANT_BT_STATUS_IDLE = 0x0,
BT_8192D_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8192D_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8192D_2ANT_BT_STATUS_MAX
} BT_8192D_2ANT_BT_STATUS,*PBT_8192D_2ANT_BT_STATUS;
typedef enum _BT_8192D_2ANT_COEX_ALGO {
BT_8192D_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8192D_2ANT_COEX_ALGO_SCO = 0x1,
BT_8192D_2ANT_COEX_ALGO_HID = 0x2,
BT_8192D_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8192D_2ANT_COEX_ALGO_PAN = 0x4,
BT_8192D_2ANT_COEX_ALGO_HID_A2DP = 0x5,
BT_8192D_2ANT_COEX_ALGO_HID_PAN = 0x6,
BT_8192D_2ANT_COEX_ALGO_PAN_A2DP = 0x7,
BT_8192D_2ANT_COEX_ALGO_MAX
} BT_8192D_2ANT_COEX_ALGO,*PBT_8192D_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8192D_2ANT {
// fw mechanism
BOOLEAN bPreBalanceOn;
BOOLEAN bCurBalanceOn;
// diminishWifi
BOOLEAN bPreDacOn;
BOOLEAN bCurDacOn;
BOOLEAN bPreInterruptOn;
BOOLEAN bCurInterruptOn;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bPreNavOn;
BOOLEAN bCurNavOn;
//BOOLEAN bPreDecBtPwr;
//BOOLEAN bCurDecBtPwr;
//u1Byte preFwDacSwingLvl;
//u1Byte curFwDacSwingLvl;
//BOOLEAN bCurIgnoreWlanAct;
//BOOLEAN bPreIgnoreWlanAct;
//u1Byte prePsTdma;
//u1Byte curPsTdma;
//u1Byte psTdmaPara[5];
//u1Byte psTdmaDuAdjType;
//BOOLEAN bResetTdmaAdjust;
//BOOLEAN bPrePsTdmaOn;
//BOOLEAN bCurPsTdmaOn;
//BOOLEAN bPreBtAutoReport;
//BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
//u4Byte preVal0x6c0;
//u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u4Byte preVal0x6cc;
u4Byte curVal0x6cc;
//BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
//u1Byte btStatus;
//u1Byte wifiChnlInfo[3];
} COEX_DM_8192D_2ANT, *PCOEX_DM_8192D_2ANT;
typedef struct _COEX_STA_8192D_2ANT {
u1Byte preWifiRssiState[4];
BOOLEAN bBtBusy;
BOOLEAN bBtUplink;
BOOLEAN bBtDownLink;
BOOLEAN bA2dpBusy;
} COEX_STA_8192D_2ANT, *PCOEX_STA_8192D_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8192d2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192d2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8192d2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192d2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192d2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192d2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192d2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8192d2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

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backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8192e1Ant.c Executable file → Normal file
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backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8192e1Ant.h Executable file → Normal file
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@@ -1,209 +1,214 @@
//===========================================
// The following is for 8192E_1ANT BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8192E_1ANT 0
#define BT_INFO_8192E_1ANT_B_FTP BIT7
#define BT_INFO_8192E_1ANT_B_A2DP BIT6
#define BT_INFO_8192E_1ANT_B_HID BIT5
#define BT_INFO_8192E_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8192E_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8192E_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8192E_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8192E_1ANT_B_CONNECTION BIT0
#define BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT 2
typedef enum _BT_INFO_SRC_8192E_1ANT{
BT_INFO_SRC_8192E_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8192E_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8192E_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8192E_1ANT_MAX
}BT_INFO_SRC_8192E_1ANT,*PBT_INFO_SRC_8192E_1ANT;
typedef enum _BT_8192E_1ANT_BT_STATUS{
BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8192E_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8192E_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8192E_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8192E_1ANT_BT_STATUS_MAX
}BT_8192E_1ANT_BT_STATUS,*PBT_8192E_1ANT_BT_STATUS;
typedef enum _BT_8192E_1ANT_WIFI_STATUS{
BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8192E_1ANT_WIFI_STATUS_MAX
}BT_8192E_1ANT_WIFI_STATUS,*PBT_8192E_1ANT_WIFI_STATUS;
typedef enum _BT_8192E_1ANT_COEX_ALGO{
BT_8192E_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8192E_1ANT_COEX_ALGO_SCO = 0x1,
BT_8192E_1ANT_COEX_ALGO_HID = 0x2,
BT_8192E_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8192E_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8192E_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8192E_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8192E_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8192E_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8192E_1ANT_COEX_ALGO,*PBT_8192E_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8192E_1ANT{
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u1Byte preSsType;
u1Byte curSsType;
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte errorCondition;
} COEX_DM_8192E_1ANT, *PCOEX_DM_8192E_1ANT;
typedef struct _COEX_STA_8192E_1ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8192E_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8192E_1ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8192E_1ANT, *PCOEX_STA_8192E_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8192e1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8192e1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8192e1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);
//===========================================
// The following is for 8192E_1ANT BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8192E_1ANT 0
#define BT_INFO_8192E_1ANT_B_FTP BIT7
#define BT_INFO_8192E_1ANT_B_A2DP BIT6
#define BT_INFO_8192E_1ANT_B_HID BIT5
#define BT_INFO_8192E_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8192E_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8192E_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8192E_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8192E_1ANT_B_CONNECTION BIT0
#define BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT 2
typedef enum _BT_INFO_SRC_8192E_1ANT {
BT_INFO_SRC_8192E_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8192E_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8192E_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8192E_1ANT_MAX
} BT_INFO_SRC_8192E_1ANT,*PBT_INFO_SRC_8192E_1ANT;
typedef enum _BT_8192E_1ANT_BT_STATUS {
BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8192E_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8192E_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8192E_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8192E_1ANT_BT_STATUS_MAX
} BT_8192E_1ANT_BT_STATUS,*PBT_8192E_1ANT_BT_STATUS;
typedef enum _BT_8192E_1ANT_WIFI_STATUS {
BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8192E_1ANT_WIFI_STATUS_MAX
} BT_8192E_1ANT_WIFI_STATUS,*PBT_8192E_1ANT_WIFI_STATUS;
typedef enum _BT_8192E_1ANT_COEX_ALGO {
BT_8192E_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8192E_1ANT_COEX_ALGO_SCO = 0x1,
BT_8192E_1ANT_COEX_ALGO_HID = 0x2,
BT_8192E_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8192E_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8192E_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8192E_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8192E_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8192E_1ANT_COEX_ALGO_MAX = 0xb,
} BT_8192E_1ANT_COEX_ALGO,*PBT_8192E_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8192E_1ANT {
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u1Byte preSsType;
u1Byte curSsType;
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte errorCondition;
} COEX_DM_8192E_1ANT, *PCOEX_DM_8192E_1ANT;
typedef struct _COEX_STA_8192E_1ANT {
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8192E_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8192E_1ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
} COEX_STA_8192E_1ANT, *PCOEX_STA_8192E_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8192e1ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8192e1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8192e1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8192e1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);

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backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8192e2Ant.c Executable file → Normal file
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backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8192e2Ant.h Executable file → Normal file
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@@ -1,201 +1,205 @@
//===========================================
// The following is for 8192E 2Ant BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8192E_2ANT 0
#define BT_INFO_8192E_2ANT_B_FTP BIT7
#define BT_INFO_8192E_2ANT_B_A2DP BIT6
#define BT_INFO_8192E_2ANT_B_HID BIT5
#define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8192E_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT 2
typedef enum _BT_INFO_SRC_8192E_2ANT{
BT_INFO_SRC_8192E_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8192E_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8192E_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8192E_2ANT_MAX
}BT_INFO_SRC_8192E_2ANT,*PBT_INFO_SRC_8192E_2ANT;
typedef enum _BT_8192E_2ANT_BT_STATUS{
BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8192E_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8192E_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8192E_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8192E_2ANT_BT_STATUS_MAX
}BT_8192E_2ANT_BT_STATUS,*PBT_8192E_2ANT_BT_STATUS;
typedef enum _BT_8192E_2ANT_COEX_ALGO{
BT_8192E_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8192E_2ANT_COEX_ALGO_SCO = 0x1,
BT_8192E_2ANT_COEX_ALGO_SCO_PAN = 0x2,
BT_8192E_2ANT_COEX_ALGO_HID = 0x3,
BT_8192E_2ANT_COEX_ALGO_A2DP = 0x4,
BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS = 0x5,
BT_8192E_2ANT_COEX_ALGO_PANEDR = 0x6,
BT_8192E_2ANT_COEX_ALGO_PANHS = 0x7,
BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8,
BT_8192E_2ANT_COEX_ALGO_PANEDR_HID = 0x9,
BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa,
BT_8192E_2ANT_COEX_ALGO_HID_A2DP = 0xb,
BT_8192E_2ANT_COEX_ALGO_MAX = 0xc
}BT_8192E_2ANT_COEX_ALGO,*PBT_8192E_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8192E_2ANT{
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u1Byte preSsType;
u1Byte curSsType;
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte curRaMaskType;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
} COEX_DM_8192E_2ANT, *PCOEX_DM_8192E_2ANT;
typedef struct _COEX_STA_8192E_2ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8192E_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8192E_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8192E_2ANT, *PCOEX_STA_8192E_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8192e2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8192e2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
//===========================================
// The following is for 8192E 2Ant BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8192E_2ANT 0
#define BT_INFO_8192E_2ANT_B_FTP BIT7
#define BT_INFO_8192E_2ANT_B_A2DP BIT6
#define BT_INFO_8192E_2ANT_B_HID BIT5
#define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8192E_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT 2
typedef enum _BT_INFO_SRC_8192E_2ANT {
BT_INFO_SRC_8192E_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8192E_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8192E_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8192E_2ANT_MAX
} BT_INFO_SRC_8192E_2ANT,*PBT_INFO_SRC_8192E_2ANT;
typedef enum _BT_8192E_2ANT_BT_STATUS {
BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8192E_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8192E_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8192E_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8192E_2ANT_BT_STATUS_MAX
} BT_8192E_2ANT_BT_STATUS,*PBT_8192E_2ANT_BT_STATUS;
typedef enum _BT_8192E_2ANT_COEX_ALGO {
BT_8192E_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8192E_2ANT_COEX_ALGO_SCO = 0x1,
BT_8192E_2ANT_COEX_ALGO_SCO_PAN = 0x2,
BT_8192E_2ANT_COEX_ALGO_HID = 0x3,
BT_8192E_2ANT_COEX_ALGO_A2DP = 0x4,
BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS = 0x5,
BT_8192E_2ANT_COEX_ALGO_PANEDR = 0x6,
BT_8192E_2ANT_COEX_ALGO_PANHS = 0x7,
BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8,
BT_8192E_2ANT_COEX_ALGO_PANEDR_HID = 0x9,
BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa,
BT_8192E_2ANT_COEX_ALGO_HID_A2DP = 0xb,
BT_8192E_2ANT_COEX_ALGO_MAX = 0xc
} BT_8192E_2ANT_COEX_ALGO,*PBT_8192E_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8192E_2ANT {
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u1Byte preSsType;
u1Byte curSsType;
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte curRaMaskType;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
} COEX_DM_8192E_2ANT, *PCOEX_DM_8192E_2ANT;
typedef struct _COEX_STA_8192E_2ANT {
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8192E_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8192E_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
} COEX_STA_8192E_2ANT, *PCOEX_STA_8192E_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8192e2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8192e2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8192e2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

2967
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8723a1Ant.c Executable file → Normal file
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341
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8723a1Ant.h Executable file → Normal file
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@@ -1,171 +1,170 @@
//===========================================
// The following is for 8723A 1Ant BT Co-exist definition
//===========================================
#define BT_INFO_8723A_1ANT_B_FTP BIT7
#define BT_INFO_8723A_1ANT_B_A2DP BIT6
#define BT_INFO_8723A_1ANT_B_HID BIT5
#define BT_INFO_8723A_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723A_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723A_1ANT_B_CONNECTION BIT0
typedef enum _BT_STATE_8723A_1ANT{
BT_STATE_8723A_1ANT_DISABLED = 0,
BT_STATE_8723A_1ANT_NO_CONNECTION = 1,
BT_STATE_8723A_1ANT_CONNECT_IDLE = 2,
BT_STATE_8723A_1ANT_INQ_OR_PAG = 3,
BT_STATE_8723A_1ANT_ACL_ONLY_BUSY = 4,
BT_STATE_8723A_1ANT_SCO_ONLY_BUSY = 5,
BT_STATE_8723A_1ANT_ACL_SCO_BUSY = 6,
BT_STATE_8723A_1ANT_HID_BUSY = 7,
BT_STATE_8723A_1ANT_HID_SCO_BUSY = 8,
BT_STATE_8723A_1ANT_MAX
}BT_STATE_8723A_1ANT, *PBT_STATE_8723A_1ANT;
#define BTC_RSSI_COEX_THRESH_TOL_8723A_1ANT 2
typedef enum _BT_INFO_SRC_8723A_1ANT{
BT_INFO_SRC_8723A_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723A_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723A_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723A_1ANT_MAX
}BT_INFO_SRC_8723A_1ANT,*PBT_INFO_SRC_8723A_1ANT;
typedef enum _BT_8723A_1ANT_BT_STATUS{
BT_8723A_1ANT_BT_STATUS_IDLE = 0x0,
BT_8723A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723A_1ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8723A_1ANT_BT_STATUS_MAX
}BT_8723A_1ANT_BT_STATUS,*PBT_8723A_1ANT_BT_STATUS;
typedef enum _BT_8723A_1ANT_COEX_ALGO{
BT_8723A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723A_1ANT_COEX_ALGO_SCO = 0x1,
BT_8723A_1ANT_COEX_ALGO_HID = 0x2,
BT_8723A_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8723A_1ANT_COEX_ALGO_PANEDR = 0x4,
BT_8723A_1ANT_COEX_ALGO_PANHS = 0x5,
BT_8723A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x6,
BT_8723A_1ANT_COEX_ALGO_PANEDR_HID = 0x7,
BT_8723A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8,
BT_8723A_1ANT_COEX_ALGO_HID_A2DP = 0x9,
BT_8723A_1ANT_COEX_ALGO_MAX
}BT_8723A_1ANT_COEX_ALGO,*PBT_8723A_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8723A_1ANT{
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
u4Byte psTdmaMonitorCnt;
u4Byte psTdmaGlobalCnt;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
} COEX_DM_8723A_1ANT, *PCOEX_DM_8723A_1ANT;
typedef struct _COEX_STA_8723A_1ANT{
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preBtRssiState1;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723A_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_1ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
//BOOLEAN bHoldForStackOperation;
//u1Byte bHoldPeriodCnt;
// this is for c2h hang work-around
u4Byte c2hHangDetectCnt;
}COEX_STA_8723A_1ANT, *PCOEX_STA_8723A_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723a1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723a1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
//===========================================
// The following is for 8723A 1Ant BT Co-exist definition
//===========================================
#define BT_INFO_8723A_1ANT_B_FTP BIT7
#define BT_INFO_8723A_1ANT_B_A2DP BIT6
#define BT_INFO_8723A_1ANT_B_HID BIT5
#define BT_INFO_8723A_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723A_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723A_1ANT_B_CONNECTION BIT0
typedef enum _BT_STATE_8723A_1ANT {
BT_STATE_8723A_1ANT_DISABLED = 0,
BT_STATE_8723A_1ANT_NO_CONNECTION = 1,
BT_STATE_8723A_1ANT_CONNECT_IDLE = 2,
BT_STATE_8723A_1ANT_INQ_OR_PAG = 3,
BT_STATE_8723A_1ANT_ACL_ONLY_BUSY = 4,
BT_STATE_8723A_1ANT_SCO_ONLY_BUSY = 5,
BT_STATE_8723A_1ANT_ACL_SCO_BUSY = 6,
BT_STATE_8723A_1ANT_HID_BUSY = 7,
BT_STATE_8723A_1ANT_HID_SCO_BUSY = 8,
BT_STATE_8723A_1ANT_MAX
} BT_STATE_8723A_1ANT, *PBT_STATE_8723A_1ANT;
#define BTC_RSSI_COEX_THRESH_TOL_8723A_1ANT 2
typedef enum _BT_INFO_SRC_8723A_1ANT {
BT_INFO_SRC_8723A_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723A_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723A_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723A_1ANT_MAX
} BT_INFO_SRC_8723A_1ANT,*PBT_INFO_SRC_8723A_1ANT;
typedef enum _BT_8723A_1ANT_BT_STATUS {
BT_8723A_1ANT_BT_STATUS_IDLE = 0x0,
BT_8723A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723A_1ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8723A_1ANT_BT_STATUS_MAX
} BT_8723A_1ANT_BT_STATUS,*PBT_8723A_1ANT_BT_STATUS;
typedef enum _BT_8723A_1ANT_COEX_ALGO {
BT_8723A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723A_1ANT_COEX_ALGO_SCO = 0x1,
BT_8723A_1ANT_COEX_ALGO_HID = 0x2,
BT_8723A_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8723A_1ANT_COEX_ALGO_PANEDR = 0x4,
BT_8723A_1ANT_COEX_ALGO_PANHS = 0x5,
BT_8723A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x6,
BT_8723A_1ANT_COEX_ALGO_PANEDR_HID = 0x7,
BT_8723A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8,
BT_8723A_1ANT_COEX_ALGO_HID_A2DP = 0x9,
BT_8723A_1ANT_COEX_ALGO_MAX
} BT_8723A_1ANT_COEX_ALGO,*PBT_8723A_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8723A_1ANT {
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
u4Byte psTdmaMonitorCnt;
u4Byte psTdmaGlobalCnt;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
} COEX_DM_8723A_1ANT, *PCOEX_DM_8723A_1ANT;
typedef struct _COEX_STA_8723A_1ANT {
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preBtRssiState1;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723A_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_1ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
//BOOLEAN bHoldForStackOperation;
//u1Byte bHoldPeriodCnt;
// this is for c2h hang work-around
u4Byte c2hHangDetectCnt;
} COEX_STA_8723A_1ANT, *PCOEX_STA_8723A_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723a1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723a1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

6860
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8723a2Ant.c Executable file → Normal file
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362
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8723a2Ant.h Executable file → Normal file
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@@ -1,179 +1,183 @@
//===========================================
// The following is for 8723A 2Ant BT Co-exist definition
//===========================================
#define BT_INFO_8723A_2ANT_B_FTP BIT7
#define BT_INFO_8723A_2ANT_B_A2DP BIT6
#define BT_INFO_8723A_2ANT_B_HID BIT5
#define BT_INFO_8723A_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723A_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723A_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723A_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723A_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT 2
typedef enum _BT_INFO_SRC_8723A_2ANT{
BT_INFO_SRC_8723A_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723A_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723A_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723A_2ANT_MAX
}BT_INFO_SRC_8723A_2ANT,*PBT_INFO_SRC_8723A_2ANT;
typedef enum _BT_8723A_2ANT_BT_STATUS{
BT_8723A_2ANT_BT_STATUS_IDLE = 0x0,
BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723A_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8723A_2ANT_BT_STATUS_MAX
}BT_8723A_2ANT_BT_STATUS,*PBT_8723A_2ANT_BT_STATUS;
typedef enum _BT_8723A_2ANT_COEX_ALGO{
BT_8723A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723A_2ANT_COEX_ALGO_SCO = 0x1,
BT_8723A_2ANT_COEX_ALGO_HID = 0x2,
BT_8723A_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8723A_2ANT_COEX_ALGO_PANEDR = 0x4,
BT_8723A_2ANT_COEX_ALGO_PANHS = 0x5,
BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x6,
BT_8723A_2ANT_COEX_ALGO_PANEDR_HID = 0x7,
BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8,
BT_8723A_2ANT_COEX_ALGO_HID_A2DP = 0x9,
BT_8723A_2ANT_COEX_ALGO_MAX
}BT_8723A_2ANT_COEX_ALGO,*PBT_8723A_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8723A_2ANT{
// fw mechanism
BOOLEAN bPreDecBtPwr;
BOOLEAN bCurDecBtPwr;
//BOOLEAN bPreBtLnaConstrain;
//BOOLEAN bCurBtLnaConstrain;
//u1Byte bPreBtPsdMode;
//u1Byte bCurBtPsdMode;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
//BOOLEAN bPreBtAutoReport;
//BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
} COEX_DM_8723A_2ANT, *PCOEX_DM_8723A_2ANT;
typedef struct _COEX_STA_8723A_2ANT{
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preBtRssiState1;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723A_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
BOOLEAN bHoldForStackOperation;
u1Byte bHoldPeriodCnt;
// this is for c2h hang work-around
u4Byte c2hHangDetectCnt;
}COEX_STA_8723A_2ANT, *PCOEX_STA_8723A_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723a2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723a2ant_StackOperationNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
//===========================================
// The following is for 8723A 2Ant BT Co-exist definition
//===========================================
#define BT_INFO_8723A_2ANT_B_FTP BIT7
#define BT_INFO_8723A_2ANT_B_A2DP BIT6
#define BT_INFO_8723A_2ANT_B_HID BIT5
#define BT_INFO_8723A_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723A_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723A_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723A_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723A_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT 2
typedef enum _BT_INFO_SRC_8723A_2ANT {
BT_INFO_SRC_8723A_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723A_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723A_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723A_2ANT_MAX
} BT_INFO_SRC_8723A_2ANT,*PBT_INFO_SRC_8723A_2ANT;
typedef enum _BT_8723A_2ANT_BT_STATUS {
BT_8723A_2ANT_BT_STATUS_IDLE = 0x0,
BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723A_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8723A_2ANT_BT_STATUS_MAX
} BT_8723A_2ANT_BT_STATUS,*PBT_8723A_2ANT_BT_STATUS;
typedef enum _BT_8723A_2ANT_COEX_ALGO {
BT_8723A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723A_2ANT_COEX_ALGO_SCO = 0x1,
BT_8723A_2ANT_COEX_ALGO_HID = 0x2,
BT_8723A_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8723A_2ANT_COEX_ALGO_PANEDR = 0x4,
BT_8723A_2ANT_COEX_ALGO_PANHS = 0x5,
BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x6,
BT_8723A_2ANT_COEX_ALGO_PANEDR_HID = 0x7,
BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8,
BT_8723A_2ANT_COEX_ALGO_HID_A2DP = 0x9,
BT_8723A_2ANT_COEX_ALGO_MAX
} BT_8723A_2ANT_COEX_ALGO,*PBT_8723A_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8723A_2ANT {
// fw mechanism
BOOLEAN bPreDecBtPwr;
BOOLEAN bCurDecBtPwr;
//BOOLEAN bPreBtLnaConstrain;
//BOOLEAN bCurBtLnaConstrain;
//u1Byte bPreBtPsdMode;
//u1Byte bCurBtPsdMode;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
//BOOLEAN bPreBtAutoReport;
//BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
} COEX_DM_8723A_2ANT, *PCOEX_DM_8723A_2ANT;
typedef struct _COEX_STA_8723A_2ANT {
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preBtRssiState1;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723A_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
BOOLEAN bHoldForStackOperation;
u1Byte bHoldPeriodCnt;
// this is for c2h hang work-around
u4Byte c2hHangDetectCnt;
} COEX_STA_8723A_2ANT, *PCOEX_STA_8723A_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723a2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8723a2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723a2ant_StackOperationNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

7872
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8723b1Ant.c Executable file → Normal file
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File diff suppressed because it is too large Load Diff

523
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8723b1Ant.h Executable file → Normal file
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@@ -1,209 +1,314 @@
//===========================================
// The following is for 8723B 1ANT BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8723B_1ANT 1
#define BT_INFO_8723B_1ANT_B_FTP BIT7
#define BT_INFO_8723B_1ANT_B_A2DP BIT6
#define BT_INFO_8723B_1ANT_B_HID BIT5
#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
#define BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT 2
typedef enum _BT_INFO_SRC_8723B_1ANT{
BT_INFO_SRC_8723B_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723B_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723B_1ANT_MAX
}BT_INFO_SRC_8723B_1ANT,*PBT_INFO_SRC_8723B_1ANT;
typedef enum _BT_8723B_1ANT_BT_STATUS{
BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723B_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8723B_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8723B_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8723B_1ANT_BT_STATUS_MAX
}BT_8723B_1ANT_BT_STATUS,*PBT_8723B_1ANT_BT_STATUS;
typedef enum _BT_8723B_1ANT_WIFI_STATUS{
BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8723B_1ANT_WIFI_STATUS_MAX
}BT_8723B_1ANT_WIFI_STATUS,*PBT_8723B_1ANT_WIFI_STATUS;
typedef enum _BT_8723B_1ANT_COEX_ALGO{
BT_8723B_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723B_1ANT_COEX_ALGO_SCO = 0x1,
BT_8723B_1ANT_COEX_ALGO_HID = 0x2,
BT_8723B_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8723B_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8723B_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8723B_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8723B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8723B_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8723B_1ANT_COEX_ALGO,*PBT_8723B_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8723B_1ANT{
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
u1Byte errorCondition;
} COEX_DM_8723B_1ANT, *PCOEX_DM_8723B_1ANT;
typedef struct _COEX_STA_8723B_1ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte specialPktPeriodCnt;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723B_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723B_1ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8723B_1ANT, *PCOEX_STA_8723B_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723b1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723b1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8723b1ant_CoexDmReset(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
//===========================================
// The following is for 8723B 1ANT BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8723B_1ANT 1
#define BT_INFO_8723B_1ANT_B_FTP BIT7
#define BT_INFO_8723B_1ANT_B_A2DP BIT6
#define BT_INFO_8723B_1ANT_B_HID BIT5
#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
#define BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT 2
#define BT_8723B_1ANT_WIFI_NOISY_THRESH 30 //max: 255
typedef enum _BT_INFO_SRC_8723B_1ANT {
BT_INFO_SRC_8723B_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723B_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723B_1ANT_MAX
} BT_INFO_SRC_8723B_1ANT,*PBT_INFO_SRC_8723B_1ANT;
typedef enum _BT_8723B_1ANT_BT_STATUS {
BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723B_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8723B_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8723B_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8723B_1ANT_BT_STATUS_MAX
} BT_8723B_1ANT_BT_STATUS,*PBT_8723B_1ANT_BT_STATUS;
typedef enum _BT_8723B_1ANT_WIFI_STATUS {
BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8723B_1ANT_WIFI_STATUS_MAX
} BT_8723B_1ANT_WIFI_STATUS,*PBT_8723B_1ANT_WIFI_STATUS;
typedef enum _BT_8723B_1ANT_COEX_ALGO {
BT_8723B_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723B_1ANT_COEX_ALGO_SCO = 0x1,
BT_8723B_1ANT_COEX_ALGO_HID = 0x2,
BT_8723B_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8723B_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8723B_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8723B_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8723B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8723B_1ANT_COEX_ALGO_MAX = 0xb,
} BT_8723B_1ANT_COEX_ALGO,*PBT_8723B_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8723B_1ANT {
// hw setting
u1Byte preAntPosType;
u1Byte curAntPosType;
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
u4Byte nArpCnt;
u1Byte errorCondition;
} COEX_DM_8723B_1ANT, *PCOEX_DM_8723B_1ANT;
typedef struct _COEX_STA_8723B_1ANT {
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bBtHiPriLinkExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte specialPktPeriodCnt;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
s1Byte btRssi;
BOOLEAN bBtTxRxMask;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723B_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723B_1ANT_MAX];
BOOLEAN bBtWhckTest;
BOOLEAN bC2hBtInquiryPage;
BOOLEAN bC2hBtPage; //Add for win8.1 page out issue
BOOLEAN bWiFiIsHighPriTask; //Add for win8.1 page out issue
u1Byte btRetryCnt;
u1Byte btInfoExt;
u4Byte popEventCnt;
u1Byte nScanAPNum;
u4Byte nCRCOK_CCK;
u4Byte nCRCOK_11g;
u4Byte nCRCOK_11n;
u4Byte nCRCOK_11nAgg;
u4Byte nCRCErr_CCK;
u4Byte nCRCErr_11g;
u4Byte nCRCErr_11n;
u4Byte nCRCErr_11nAgg;
BOOLEAN bCCKLock;
BOOLEAN bPreCCKLock;
BOOLEAN bCCKEverLock;
u1Byte nCoexTableType;
BOOLEAN bForceLpsOn;
} COEX_STA_8723B_1ANT, *PCOEX_STA_8723B_1ANT;
#define BT_8723B_1ANT_ANTDET_PSD_POINTS 256 //MAX:1024
#define BT_8723B_1ANT_ANTDET_PSD_AVGNUM 1 //MAX:3
typedef struct _PSDSCAN_STA_8723B_1ANT {
BOOLEAN bIsAntDetEnable;
BOOLEAN bIsAntIsoEnable;
BOOLEAN bIsPSDScanEnable;
u4Byte realcentFreq; //ex:2412
s4Byte realoffset;
u4Byte realspan;
u4Byte realseconds;
BOOLEAN bAntDetFinish;
u1Byte nAntIsolation;
u4Byte nPSDBandWidth; //unit: Hz
u4Byte nPSDPoint; //128/256/512/1024
u4Byte nPSDReport[1024]; //unit:dB (20logx), 0~255
u4Byte nPSDReport_MaxHold[1024]; //unit:dB (20logx), 0~255
u4Byte nPSDStartPoint;
u4Byte nPSDStopPoint;
u4Byte nPSDMaxValuePoint;
u4Byte nPSDMaxValue;
u4Byte nPSDStartBase;
u4Byte nPSDAvgNum; // 1/8/16/32
u4Byte nPSDGenCount;
u4Byte nPSDGenTotalCount;
BOOLEAN bIsSetupFinish;
BOOLEAN bIsPSDRunning;
BOOLEAN bIsPSDShowMaxOnly;
} PSDSCAN_STA_8723B_1ANT, *PPSDSCAN_STA_8723B_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723b1ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_PreLoadFirmware(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8723b1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723b1ant_RfStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8723b1ant_CoexDmReset(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b1ant_AntennaDetection(
IN PBTC_COEXIST pBtCoexist,
IN u4Byte centFreq,
IN u4Byte offset,
IN u4Byte span,
IN u4Byte seconds
);
VOID
EXhalbtc8723b1ant_AntennaIsolation(
IN PBTC_COEXIST pBtCoexist,
IN u4Byte centFreq,
IN u4Byte offset,
IN u4Byte span,
IN u4Byte seconds
);
VOID
EXhalbtc8723b1ant_PSDScan(
IN PBTC_COEXIST pBtCoexist,
IN u4Byte centFreq,
IN u4Byte offset,
IN u4Byte span,
IN u4Byte seconds
);
VOID
EXhalbtc8723b1ant_DisplayAntIsolation(
IN PBTC_COEXIST pBtCoexist
);

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backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8723b2Ant.c Executable file → Normal file
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411
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8723b2Ant.h Executable file → Normal file
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@@ -1,186 +1,225 @@
//===========================================
// The following is for 8723B 2Ant BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8723B_2ANT 1
#define BT_INFO_8723B_2ANT_B_FTP BIT7
#define BT_INFO_8723B_2ANT_B_A2DP BIT6
#define BT_INFO_8723B_2ANT_B_HID BIT5
#define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723B_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT 2
typedef enum _BT_INFO_SRC_8723B_2ANT{
BT_INFO_SRC_8723B_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723B_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723B_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723B_2ANT_MAX
}BT_INFO_SRC_8723B_2ANT,*PBT_INFO_SRC_8723B_2ANT;
typedef enum _BT_8723B_2ANT_BT_STATUS{
BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723B_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8723B_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8723B_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8723B_2ANT_BT_STATUS_MAX
}BT_8723B_2ANT_BT_STATUS,*PBT_8723B_2ANT_BT_STATUS;
typedef enum _BT_8723B_2ANT_COEX_ALGO{
BT_8723B_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723B_2ANT_COEX_ALGO_SCO = 0x1,
BT_8723B_2ANT_COEX_ALGO_HID = 0x2,
BT_8723B_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8723B_2ANT_COEX_ALGO_PANEDR = 0x5,
BT_8723B_2ANT_COEX_ALGO_PANHS = 0x6,
BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8723B_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8723B_2ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8723B_2ANT_COEX_ALGO_MAX = 0xb,
}BT_8723B_2ANT_COEX_ALGO,*PBT_8723B_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8723B_2ANT{
// fw mechanism
BOOLEAN bPreDecBtPwr;
BOOLEAN bCurDecBtPwr;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
BOOLEAN bNeedRecover0x948;
u2Byte backup0x948;
} COEX_DM_8723B_2ANT, *PCOEX_DM_8723B_2ANT;
typedef struct _COEX_STA_8723B_2ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723B_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723B_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8723B_2ANT, *PCOEX_STA_8723B_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723b2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723b2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
//===========================================
// The following is for 8723B 2Ant BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8723B_2ANT 1
#define BT_INFO_8723B_2ANT_B_FTP BIT7
#define BT_INFO_8723B_2ANT_B_A2DP BIT6
#define BT_INFO_8723B_2ANT_B_HID BIT5
#define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723B_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT 2
#define BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES 42 //WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation
#define BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES 46 //BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation
typedef enum _BT_INFO_SRC_8723B_2ANT {
BT_INFO_SRC_8723B_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723B_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723B_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723B_2ANT_MAX
} BT_INFO_SRC_8723B_2ANT,*PBT_INFO_SRC_8723B_2ANT;
typedef enum _BT_8723B_2ANT_BT_STATUS {
BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723B_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8723B_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8723B_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8723B_2ANT_BT_STATUS_MAX
} BT_8723B_2ANT_BT_STATUS,*PBT_8723B_2ANT_BT_STATUS;
typedef enum _BT_8723B_2ANT_COEX_ALGO {
BT_8723B_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723B_2ANT_COEX_ALGO_SCO = 0x1,
BT_8723B_2ANT_COEX_ALGO_HID = 0x2,
BT_8723B_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8723B_2ANT_COEX_ALGO_PANEDR = 0x5,
BT_8723B_2ANT_COEX_ALGO_PANHS = 0x6,
BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8723B_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8723B_2ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8723B_2ANT_COEX_ALGO_MAX = 0xb,
} BT_8723B_2ANT_COEX_ALGO,*PBT_8723B_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8723B_2ANT {
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
BOOLEAN bNeedRecover0x948;
u4Byte backup0x948;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
} COEX_DM_8723B_2ANT, *PCOEX_DM_8723B_2ANT;
typedef struct _COEX_STA_8723B_2ANT {
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
BOOLEAN bBtTxRxMask;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723B_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723B_2ANT_MAX];
BOOLEAN bBtWhckTest;
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
u4Byte nCRCOK_CCK;
u4Byte nCRCOK_11g;
u4Byte nCRCOK_11n;
u4Byte nCRCOK_11nAgg;
u4Byte nCRCErr_CCK;
u4Byte nCRCErr_11g;
u4Byte nCRCErr_11n;
u4Byte nCRCErr_11nAgg;
u1Byte nCoexTableType;
BOOLEAN bForceLpsOn;
u1Byte disVerInfoCnt;
} COEX_STA_8723B_2ANT, *PCOEX_STA_8723B_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723b2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b2ant_PreLoadFirmware(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8723b2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723b2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723b2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b2ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8723b2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723b2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

5552
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8812a1Ant.c Executable file → Normal file
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407
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8812a1Ant.h Executable file → Normal file
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@@ -1,201 +1,206 @@
//===========================================
// The following is for 8812A_1ANT BT Co-exist definition
//===========================================
#define BT_INFO_8812A_1ANT_B_FTP BIT7
#define BT_INFO_8812A_1ANT_B_A2DP BIT6
#define BT_INFO_8812A_1ANT_B_HID BIT5
#define BT_INFO_8812A_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8812A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8812A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8812A_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8812A_1ANT_B_CONNECTION BIT0
#define BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT 2
#define BTC_8812A_1ANT_SWITCH_TO_WIFI 0
#define BTC_8812A_1ANT_SWITCH_TO_BT 1
typedef enum _BT_INFO_SRC_8812A_1ANT{
BT_INFO_SRC_8812A_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8812A_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8812A_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8812A_1ANT_MAX
}BT_INFO_SRC_8812A_1ANT,*PBT_INFO_SRC_8812A_1ANT;
typedef enum _BT_8812A_1ANT_BT_STATUS{
BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8812A_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8812A_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8812A_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8812A_1ANT_BT_STATUS_MAX
}BT_8812A_1ANT_BT_STATUS,*PBT_8812A_1ANT_BT_STATUS;
typedef enum _BT_8812A_1ANT_WIFI_STATUS{
BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8812A_1ANT_WIFI_STATUS_MAX
}BT_8812A_1ANT_WIFI_STATUS,*PBT_8812A_1ANT_WIFI_STATUS;
typedef enum _BT_8812A_1ANT_COEX_ALGO{
BT_8812A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8812A_1ANT_COEX_ALGO_SCO = 0x1,
BT_8812A_1ANT_COEX_ALGO_HID = 0x2,
BT_8812A_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8812A_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8812A_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8812A_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8812A_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8812A_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8812A_1ANT_COEX_ALGO,*PBT_8812A_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8812A_1ANT{
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte errorCondition;
} COEX_DM_8812A_1ANT, *PCOEX_DM_8812A_1ANT;
typedef struct _COEX_STA_8812A_1ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8812A_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8812A_1ANT_MAX];
u4Byte btInfoQueryCnt;
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8812A_1ANT, *PCOEX_STA_8812A_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8812a1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8812a1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8812a1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);
//===========================================
// The following is for 8812A_1ANT BT Co-exist definition
//===========================================
#define BT_INFO_8812A_1ANT_B_FTP BIT7
#define BT_INFO_8812A_1ANT_B_A2DP BIT6
#define BT_INFO_8812A_1ANT_B_HID BIT5
#define BT_INFO_8812A_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8812A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8812A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8812A_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8812A_1ANT_B_CONNECTION BIT0
#define BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT 2
#define BTC_8812A_1ANT_SWITCH_TO_WIFI 0
#define BTC_8812A_1ANT_SWITCH_TO_BT 1
typedef enum _BT_INFO_SRC_8812A_1ANT {
BT_INFO_SRC_8812A_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8812A_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8812A_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8812A_1ANT_MAX
} BT_INFO_SRC_8812A_1ANT,*PBT_INFO_SRC_8812A_1ANT;
typedef enum _BT_8812A_1ANT_BT_STATUS {
BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8812A_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8812A_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8812A_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8812A_1ANT_BT_STATUS_MAX
} BT_8812A_1ANT_BT_STATUS,*PBT_8812A_1ANT_BT_STATUS;
typedef enum _BT_8812A_1ANT_WIFI_STATUS {
BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8812A_1ANT_WIFI_STATUS_MAX
} BT_8812A_1ANT_WIFI_STATUS,*PBT_8812A_1ANT_WIFI_STATUS;
typedef enum _BT_8812A_1ANT_COEX_ALGO {
BT_8812A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8812A_1ANT_COEX_ALGO_SCO = 0x1,
BT_8812A_1ANT_COEX_ALGO_HID = 0x2,
BT_8812A_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8812A_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8812A_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8812A_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8812A_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8812A_1ANT_COEX_ALGO_MAX = 0xb,
} BT_8812A_1ANT_COEX_ALGO,*PBT_8812A_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8812A_1ANT {
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte errorCondition;
} COEX_DM_8812A_1ANT, *PCOEX_DM_8812A_1ANT;
typedef struct _COEX_STA_8812A_1ANT {
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8812A_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8812A_1ANT_MAX];
u4Byte btInfoQueryCnt;
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
} COEX_STA_8812A_1ANT, *PCOEX_STA_8812A_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8812a1ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8812a1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8812a1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8812a1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a1ant_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);

9062
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8812a2Ant.c Executable file → Normal file
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431
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8812a2Ant.h Executable file → Normal file
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@@ -1,213 +1,218 @@
//===========================================
// The following is for 8812A 2Ant BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8812A_2ANT 0
#define BT_INFO_8812A_2ANT_B_FTP BIT7
#define BT_INFO_8812A_2ANT_B_A2DP BIT6
#define BT_INFO_8812A_2ANT_B_HID BIT5
#define BT_INFO_8812A_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8812A_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8812A_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8812A_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8812A_2ANT_B_CONNECTION BIT0
#define BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT 2
typedef enum _BT_INFO_SRC_8812A_2ANT{
BT_INFO_SRC_8812A_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8812A_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8812A_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8812A_2ANT_MAX
}BT_INFO_SRC_8812A_2ANT,*PBT_INFO_SRC_8812A_2ANT;
typedef enum _BT_8812A_2ANT_BT_STATUS{
BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8812A_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8812A_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8812A_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8812A_2ANT_BT_STATUS_MAX
}BT_8812A_2ANT_BT_STATUS,*PBT_8812A_2ANT_BT_STATUS;
typedef enum _BT_8812A_2ANT_COEX_ALGO{
BT_8812A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8812A_2ANT_COEX_ALGO_SCO = 0x1,
BT_8812A_2ANT_COEX_ALGO_SCO_HID = 0x2,
BT_8812A_2ANT_COEX_ALGO_HID = 0x3,
BT_8812A_2ANT_COEX_ALGO_A2DP = 0x4,
BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS = 0x5,
BT_8812A_2ANT_COEX_ALGO_PANEDR = 0x6,
BT_8812A_2ANT_COEX_ALGO_PANHS = 0x7,
BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8,
BT_8812A_2ANT_COEX_ALGO_PANEDR_HID = 0x9,
BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa,
BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS = 0xb,
BT_8812A_2ANT_COEX_ALGO_HID_A2DP = 0xc,
BT_8812A_2ANT_COEX_ALGO_MAX = 0xd
}BT_8812A_2ANT_COEX_ALGO,*PBT_8812A_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8812A_2ANT{
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bAutoTdmaAdjustLowRssi;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte curRaMaskType;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
} COEX_DM_8812A_2ANT, *PCOEX_DM_8812A_2ANT;
typedef struct _COEX_STA_8812A_2ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8812A_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8812A_2ANT_MAX];
u4Byte btInfoQueryCnt;
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8812A_2ANT, *PCOEX_STA_8812A_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8812a2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8812a2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);
//===========================================
// The following is for 8812A 2Ant BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8812A_2ANT 0
#define BT_INFO_8812A_2ANT_B_FTP BIT7
#define BT_INFO_8812A_2ANT_B_A2DP BIT6
#define BT_INFO_8812A_2ANT_B_HID BIT5
#define BT_INFO_8812A_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8812A_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8812A_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8812A_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8812A_2ANT_B_CONNECTION BIT0
#define BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT 2
typedef enum _BT_INFO_SRC_8812A_2ANT {
BT_INFO_SRC_8812A_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8812A_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8812A_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8812A_2ANT_MAX
} BT_INFO_SRC_8812A_2ANT,*PBT_INFO_SRC_8812A_2ANT;
typedef enum _BT_8812A_2ANT_BT_STATUS {
BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8812A_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8812A_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8812A_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8812A_2ANT_BT_STATUS_MAX
} BT_8812A_2ANT_BT_STATUS,*PBT_8812A_2ANT_BT_STATUS;
typedef enum _BT_8812A_2ANT_COEX_ALGO {
BT_8812A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8812A_2ANT_COEX_ALGO_SCO = 0x1,
BT_8812A_2ANT_COEX_ALGO_SCO_HID = 0x2,
BT_8812A_2ANT_COEX_ALGO_HID = 0x3,
BT_8812A_2ANT_COEX_ALGO_A2DP = 0x4,
BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS = 0x5,
BT_8812A_2ANT_COEX_ALGO_PANEDR = 0x6,
BT_8812A_2ANT_COEX_ALGO_PANHS = 0x7,
BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8,
BT_8812A_2ANT_COEX_ALGO_PANEDR_HID = 0x9,
BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa,
BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS = 0xb,
BT_8812A_2ANT_COEX_ALGO_HID_A2DP = 0xc,
BT_8812A_2ANT_COEX_ALGO_MAX = 0xd
} BT_8812A_2ANT_COEX_ALGO,*PBT_8812A_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8812A_2ANT {
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bAutoTdmaAdjustLowRssi;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte curRaMaskType;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
} COEX_DM_8812A_2ANT, *PCOEX_DM_8812A_2ANT;
typedef struct _COEX_STA_8812A_2ANT {
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bAclBusy;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8812A_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8812A_2ANT_MAX];
u4Byte btInfoQueryCnt;
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
} COEX_STA_8812A_2ANT, *PCOEX_STA_8812A_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8812a2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8812a2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8812a2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8812a2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8812a2ant_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);

6257
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8821a1Ant.c Executable file → Normal file
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422
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8821a1Ant.h Executable file → Normal file
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@@ -1,210 +1,212 @@
//===========================================
// The following is for 8821A 1ANT BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8821A_1ANT 0
#define BT_INFO_8821A_1ANT_B_FTP BIT7
#define BT_INFO_8821A_1ANT_B_A2DP BIT6
#define BT_INFO_8821A_1ANT_B_HID BIT5
#define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8821A_1ANT_B_CONNECTION BIT0
#define BT_INFO_8821A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT 2
typedef enum _BT_INFO_SRC_8821A_1ANT{
BT_INFO_SRC_8821A_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8821A_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8821A_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8821A_1ANT_MAX
}BT_INFO_SRC_8821A_1ANT,*PBT_INFO_SRC_8821A_1ANT;
typedef enum _BT_8821A_1ANT_BT_STATUS{
BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8821A_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8821A_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8821A_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8821A_1ANT_BT_STATUS_MAX
}BT_8821A_1ANT_BT_STATUS,*PBT_8821A_1ANT_BT_STATUS;
typedef enum _BT_8821A_1ANT_WIFI_STATUS{
BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8821A_1ANT_WIFI_STATUS_MAX
}BT_8821A_1ANT_WIFI_STATUS,*PBT_8821A_1ANT_WIFI_STATUS;
typedef enum _BT_8821A_1ANT_COEX_ALGO{
BT_8821A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8821A_1ANT_COEX_ALGO_SCO = 0x1,
BT_8821A_1ANT_COEX_ALGO_HID = 0x2,
BT_8821A_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8821A_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8821A_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8821A_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8821A_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8821A_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8821A_1ANT_COEX_ALGO,*PBT_8821A_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8821A_1ANT{
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
u1Byte errorCondition;
} COEX_DM_8821A_1ANT, *PCOEX_DM_8821A_1ANT;
typedef struct _COEX_STA_8821A_1ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte specialPktPeriodCnt;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8821A_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8821A_1ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8821A_1ANT, *PCOEX_STA_8821A_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8821a1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8821a1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8821a1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);
//===========================================
// The following is for 8821A 1ANT BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8821A_1ANT 1
#define BT_INFO_8821A_1ANT_B_FTP BIT7
#define BT_INFO_8821A_1ANT_B_A2DP BIT6
#define BT_INFO_8821A_1ANT_B_HID BIT5
#define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8821A_1ANT_B_CONNECTION BIT0
#define BT_INFO_8821A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? TRUE:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT 2
typedef enum _BT_INFO_SRC_8821A_1ANT {
BT_INFO_SRC_8821A_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8821A_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8821A_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8821A_1ANT_MAX
} BT_INFO_SRC_8821A_1ANT,*PBT_INFO_SRC_8821A_1ANT;
typedef enum _BT_8821A_1ANT_BT_STATUS {
BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8821A_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8821A_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8821A_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8821A_1ANT_BT_STATUS_MAX
} BT_8821A_1ANT_BT_STATUS,*PBT_8821A_1ANT_BT_STATUS;
typedef enum _BT_8821A_1ANT_WIFI_STATUS {
BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8821A_1ANT_WIFI_STATUS_MAX
} BT_8821A_1ANT_WIFI_STATUS,*PBT_8821A_1ANT_WIFI_STATUS;
typedef enum _BT_8821A_1ANT_COEX_ALGO {
BT_8821A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8821A_1ANT_COEX_ALGO_SCO = 0x1,
BT_8821A_1ANT_COEX_ALGO_HID = 0x2,
BT_8821A_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8821A_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8821A_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8821A_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8821A_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8821A_1ANT_COEX_ALGO_MAX = 0xb,
} BT_8821A_1ANT_COEX_ALGO,*PBT_8821A_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8821A_1ANT {
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt
u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt
u2Byte backupRetryLimit;
u1Byte backupAmpduMaxTime;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte preArfrType;
u1Byte curArfrType;
u1Byte preRetryLimitType;
u1Byte curRetryLimitType;
u1Byte preAmpduTimeType;
u1Byte curAmpduTimeType;
u4Byte nArpCnt;
u1Byte errorCondition;
} COEX_DM_8821A_1ANT, *PCOEX_DM_8821A_1ANT;
typedef struct _COEX_STA_8821A_1ANT {
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte specialPktPeriodCnt;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
BOOLEAN bBtTxRxMask;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8821A_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8821A_1ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
BOOLEAN bC2hBtPage; //Add for win8.1 page out issue
BOOLEAN bWiFiIsHighPriTask; //Add for win8.1 page out issue
u1Byte btRetryCnt;
u1Byte btInfoExt;
} COEX_STA_8821A_1ANT, *PCOEX_STA_8821A_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8821a1ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8821a1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8821a1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8821a1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

8192
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8821a2Ant.c Executable file → Normal file
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405
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8821a2Ant.h Executable file → Normal file
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@@ -1,180 +1,225 @@
//===========================================
// The following is for 8821A 2Ant BT Co-exist definition
//===========================================
#define BT_INFO_8821A_2ANT_B_FTP BIT7
#define BT_INFO_8821A_2ANT_B_A2DP BIT6
#define BT_INFO_8821A_2ANT_B_HID BIT5
#define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8821A_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT 2
typedef enum _BT_INFO_SRC_8821A_2ANT{
BT_INFO_SRC_8821A_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8821A_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8821A_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8821A_2ANT_MAX
}BT_INFO_SRC_8821A_2ANT,*PBT_INFO_SRC_8821A_2ANT;
typedef enum _BT_8821A_2ANT_BT_STATUS{
BT_8821A_2ANT_BT_STATUS_IDLE = 0x0,
BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8821A_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8821A_2ANT_BT_STATUS_MAX
}BT_8821A_2ANT_BT_STATUS,*PBT_8821A_2ANT_BT_STATUS;
typedef enum _BT_8821A_2ANT_COEX_ALGO{
BT_8821A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8821A_2ANT_COEX_ALGO_SCO = 0x1,
BT_8821A_2ANT_COEX_ALGO_HID = 0x2,
BT_8821A_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8821A_2ANT_COEX_ALGO_PANEDR = 0x5,
BT_8821A_2ANT_COEX_ALGO_PANHS = 0x6,
BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8821A_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8821A_2ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8821A_2ANT_COEX_ALGO_MAX = 0xb,
}BT_8821A_2ANT_COEX_ALGO,*PBT_8821A_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8821A_2ANT{
// fw mechanism
BOOLEAN bPreDecBtPwr;
BOOLEAN bCurDecBtPwr;
BOOLEAN bPreBtLnaConstrain;
BOOLEAN bCurBtLnaConstrain;
u1Byte bPreBtPsdMode;
u1Byte bCurBtPsdMode;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
} COEX_DM_8821A_2ANT, *PCOEX_DM_8821A_2ANT;
typedef struct _COEX_STA_8821A_2ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8821A_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8821A_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8821A_2ANT, *PCOEX_STA_8821A_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8821a2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8821a2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
//===========================================
// The following is for 8821A 2Ant BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8821A_2ANT 1
#define BT_INFO_8821A_2ANT_B_FTP BIT7
#define BT_INFO_8821A_2ANT_B_A2DP BIT6
#define BT_INFO_8821A_2ANT_B_HID BIT5
#define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8821A_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT 2
#define BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES 42 //WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation
#define BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES 46 //BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation
typedef enum _BT_INFO_SRC_8821A_2ANT {
BT_INFO_SRC_8821A_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8821A_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8821A_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8821A_2ANT_MAX
} BT_INFO_SRC_8821A_2ANT,*PBT_INFO_SRC_8821A_2ANT;
typedef enum _BT_8821A_2ANT_BT_STATUS {
BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8821A_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8821A_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8821A_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8821A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8821A_2ANT_BT_STATUS_MAX
} BT_8821A_2ANT_BT_STATUS,*PBT_8821A_2ANT_BT_STATUS;
typedef enum _BT_8821A_2ANT_COEX_ALGO {
BT_8821A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8821A_2ANT_COEX_ALGO_SCO = 0x1,
BT_8821A_2ANT_COEX_ALGO_HID = 0x2,
BT_8821A_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8821A_2ANT_COEX_ALGO_PANEDR = 0x5,
BT_8821A_2ANT_COEX_ALGO_PANHS = 0x6,
BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8821A_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8821A_2ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8821A_2ANT_COEX_ALGO_MAX = 0xb,
} BT_8821A_2ANT_COEX_ALGO,*PBT_8821A_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8821A_2ANT {
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
BOOLEAN bNeedRecover0x948;
u4Byte backup0x948;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
} COEX_DM_8821A_2ANT, *PCOEX_DM_8821A_2ANT;
typedef struct _COEX_STA_8821A_2ANT {
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
BOOLEAN bBtTxRxMask;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8821A_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8821A_2ANT_MAX];
BOOLEAN bBtWhckTest;
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
u4Byte nCRCOK_CCK;
u4Byte nCRCOK_11g;
u4Byte nCRCOK_11n;
u4Byte nCRCOK_11nAgg;
u4Byte nCRCErr_CCK;
u4Byte nCRCErr_11g;
u4Byte nCRCErr_11n;
u4Byte nCRCErr_11nAgg;
u1Byte nCoexTableType;
BOOLEAN bForceLpsOn;
u1Byte disVerInfoCnt;
} COEX_STA_8821A_2ANT, *PCOEX_STA_8821A_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8821a2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_PreLoadFirmware(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8821a2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821a2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8821a2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8821a2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821a2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

3632
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8821aCsr2Ant.c Normal file
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File diff suppressed because it is too large Load Diff

206
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtc8821aCsr2Ant.h Normal file
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@@ -0,0 +1,206 @@
//===========================================
// The following is for 8821A_CSR 2Ant BT Co-exist definition
//===========================================
#define BT_INFO_8821A_CSR_2ANT_B_FTP BIT7
#define BT_INFO_8821A_CSR_2ANT_B_A2DP BIT6
#define BT_INFO_8821A_CSR_2ANT_B_HID BIT5
#define BT_INFO_8821A_CSR_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8821A_CSR_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8821A_CSR_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8821A_CSR_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8821A_CSR_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT 2
typedef enum _BT_INFO_SRC_8821A_CSR_2ANT {
BT_INFO_SRC_8821A_CSR_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8821A_CSR_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8821A_CSR_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8821A_CSR_2ANT_MAX
} BT_INFO_SRC_8821A_CSR_2ANT,*PBT_INFO_SRC_8821A_CSR_2ANT;
typedef enum _BT_8821A_CSR_2ANT_BT_STATUS {
BT_8821A_CSR_2ANT_BT_STATUS_IDLE = 0x0,
BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8821A_CSR_2ANT_BT_STATUS_MAX
} BT_8821A_CSR_2ANT_BT_STATUS,*PBT_8821A_CSR_2ANT_BT_STATUS;
typedef enum _BT_8821A_CSR_2ANT_COEX_ALGO {
BT_8821A_CSR_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8821A_CSR_2ANT_COEX_ALGO_SCO = 0x1,
BT_8821A_CSR_2ANT_COEX_ALGO_HID = 0x2,
BT_8821A_CSR_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8821A_CSR_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR = 0x5,
BT_8821A_CSR_2ANT_COEX_ALGO_PANHS = 0x6,
BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8821A_CSR_2ANT_COEX_ALGO_MAX = 0xb,
} BT_8821A_CSR_2ANT_COEX_ALGO,*PBT_8821A_CSR_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8821A_CSR_2ANT {
// fw mechanism
BOOLEAN bPreDecBtPwr;
BOOLEAN bCurDecBtPwr;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[6];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN bLimitedDig;
u4Byte preRaMask;
u4Byte curRaMask;
u1Byte curAmpduNumType;
u1Byte preAmpduNumType;
u2Byte backupAmpduMaxNum;
u1Byte curAmpduTimeType;
u1Byte preAmpduTimeType;
u1Byte backupAmpduMaxTime;
u1Byte curArfrType;
u1Byte preArfrType;
u4Byte backupArfrCnt1;
u4Byte backupArfrCnt2;
u1Byte curRetryLimitType;
u1Byte preRetryLimitType;
u2Byte backupRetryLimit;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
} COEX_DM_8821A_CSR_2ANT, *PCOEX_DM_8821A_CSR_2ANT;
typedef struct _COEX_STA_8821A_CSR_2ANT {
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bSlave;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8821A_CSR_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8821A_CSR_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
} COEX_STA_8821A_CSR_2ANT, *PCOEX_STA_8821A_CSR_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8821aCsr2ant_PowerOnSetting(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821aCsr2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist,
IN BOOLEAN bWifiOnly
);
VOID
EXhalbtc8821aCsr2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821aCsr2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8821aCsr2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8821aCsr2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821aCsr2ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8821aCsr2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8821aCsr2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

1456
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/HalBtcOutSrc.h Executable file → Normal file
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File diff suppressed because it is too large Load Diff

1
backports/drivers/realtek/rtl8812au/hal/OUTSRC-BTCoexist/Mp_Precomp.h Executable file → Normal file
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@@ -52,5 +52,6 @@
#include "HalBtc8812a2Ant.h"
#include "HalBtc8821a1Ant.h"
#include "HalBtc8821a2Ant.h"
#include "HalBtc8821aCsr2Ant.h"
#endif // __MP_PRECOMP_H__

455
backports/drivers/realtek/rtl8812au/hal/OUTSRC/HalPhyRf.c Executable file → Normal file
View File

@@ -18,8 +18,8 @@
*
******************************************************************************/
//#include "Mp_Precomp.h"
#include "odm_precomp.h"
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \
@@ -37,16 +37,78 @@
_offset = _size-1;\
} while(0)
#if (RTL8192C_SUPPORT||RTL8192D_SUPPORT||RTL8723A_SUPPORT)
void phydm_txpwrtrack_setpwr_dummy(
PDM_ODM_T pDM_Odm,
PWRTRACK_METHOD Method,
u1Byte RFPath,
u1Byte ChannelMappedIndex
)
{
};
void doiqk_dummy(
PDM_ODM_T pDM_Odm,
u1Byte DeltaThermalIndex,
u1Byte ThermalValue,
u1Byte Threshold
)
{
};
VOID phy_lccalibrate_dummy(
IN PDM_ODM_T pDM_Odm
)
{
};
VOID get_delta_swing_table_dummy(
IN PDM_ODM_T pDM_Odm,
OUT pu1Byte *TemperatureUP_A,
OUT pu1Byte *TemperatureDOWN_A,
OUT pu1Byte *TemperatureUP_B,
OUT pu1Byte *TemperatureDOWN_B
)
{
};
void configure_txpower_track_dummy(
PTXPWRTRACK_CFG pConfig
)
{
pConfig->ODM_TxPwrTrackSetPwr = phydm_txpwrtrack_setpwr_dummy;
pConfig->DoIQK = doiqk_dummy;
pConfig->PHY_LCCalibrate = phy_lccalibrate_dummy;
pConfig->GetDeltaSwingTable = get_delta_swing_table_dummy;
}
#endif
void ConfigureTxpowerTrack(
IN PDM_ODM_T pDM_Odm,
OUT PTXPWRTRACK_CFG pConfig
)
IN PDM_ODM_T pDM_Odm,
OUT PTXPWRTRACK_CFG pConfig
)
{
#if RTL8192C_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8192C)
configure_txpower_track_dummy(pConfig);
#endif
#if RTL8192D_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8192D)
configure_txpower_track_dummy(pConfig);
#endif
#if RTL8723A_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8723A)
configure_txpower_track_dummy(pConfig);
#endif
#if RTL8192E_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8192E)
ConfigureTxpowerTrack_8192E(pConfig);
#endif
#endif
#if RTL8821A_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8821)
ConfigureTxpowerTrack_8821A(pConfig);
@@ -58,7 +120,7 @@ void ConfigureTxpowerTrack(
#if RTL8188E_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8188E)
ConfigureTxpowerTrack_8188E(pConfig);
#endif
#endif
#if RTL8723B_SUPPORT
if(pDM_Odm->SupportICType==ODM_RTL8723B)
@@ -69,29 +131,28 @@ void ConfigureTxpowerTrack(
//======================================================================
// <20121113, Kordan> This function should be called when TxAGC changed.
// Otherwise the previous compensation is gone, because we record the
// Otherwise the previous compensation is gone, because we record the
// delta of temperature between two TxPowerTracking watch dogs.
//
// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
// need to call this function.
//======================================================================
VOID
ODM_ClearTxPowerTrackingState(
IN PDM_ODM_T pDM_Odm
)
IN PDM_ODM_T pDM_Odm
)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
u1Byte p = 0;
pDM_Odm->BbSwingIdxCckBase = pDM_Odm->DefaultCckIndex;
pDM_Odm->BbSwingIdxCck = pDM_Odm->DefaultCckIndex;
pDM_Odm->RFCalibrateInfo.CCK_index = 0;
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p)
{
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->DefaultOfdmIndex;
pDM_Odm->BbSwingIdxOfdm[p] = pDM_Odm->DefaultOfdmIndex;
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pDM_Odm->DefaultOfdmIndex;
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pDM_Odm->DefaultOfdmIndex;
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = 0;
@@ -99,39 +160,39 @@ ODM_ClearTxPowerTrackingState(
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
pDM_Odm->Absolute_OFDMSwingIdx[p] = 0; // Initial Mix mode power tracking
pDM_Odm->Remnant_OFDMSwingIdx[p] = 0;
pDM_Odm->Remnant_OFDMSwingIdx[p] = 0;
}
pDM_Odm->Modify_TxAGC_Flag_PathA= FALSE; //Initial at Modify Tx Scaling Mode
pDM_Odm->Modify_TxAGC_Flag_PathB= FALSE; //Initial at Modify Tx Scaling Mode
pDM_Odm->Remnant_CCKSwingIdx= 0;
pDM_Odm->RFCalibrateInfo.ThermalValue = pHalData->EEPROMThermalMeter;
pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = pHalData->EEPROMThermalMeter;
pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = pHalData->EEPROMThermalMeter;
pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = pHalData->EEPROMThermalMeter;
}
VOID
ODM_TXPowerTrackingCallback_ThermalMeter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER Adapter
IN PADAPTER Adapter
#endif
)
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
#endif
#endif
#endif
u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
u1Byte ThermalValue_AVG_count = 0;
u4Byte ThermalValue_AVG = 0;
u4Byte ThermalValue_AVG = 0;
u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur
u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel)
@@ -144,70 +205,66 @@ ODM_TXPowerTrackingCallback_ThermalMeter(
pu1Byte deltaSwingTableIdx_TDOWN_A;
pu1Byte deltaSwingTableIdx_TUP_B;
pu1Byte deltaSwingTableIdx_TDOWN_B;
//4 2. Initilization ( 7 steps in total )
ConfigureTxpowerTrack(pDM_Odm, &c);
(*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_A, (pu1Byte*)&deltaSwingTableIdx_TDOWN_A,
(pu1Byte*)&deltaSwingTableIdx_TUP_B, (pu1Byte*)&deltaSwingTableIdx_TDOWN_B);
(pu1Byte*)&deltaSwingTableIdx_TUP_B, (pu1Byte*)&deltaSwingTableIdx_TDOWN_B);
pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; //cosa add for debug
pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = TRUE;
#if (MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = pHalData->TxPowerTrackControl; // <Kordan> We should keep updating the control variable according to HalData.
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
if ( *(pDM_Odm->mp_mode) == 1)
if (pDM_Odm->mp_mode == TRUE)
#endif
// <Kordan> RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files.
pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317;
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("===>ODM_TXPowerTrackingCallback_ThermalMeter, \
\n pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase[A]: %d, pDM_Odm->DefaultOfdmIndex: %d\n",
pDM_Odm->BbSwingIdxCckBase, pDM_Odm->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pDM_Odm->DefaultOfdmIndex));
("===>ODM_TXPowerTrackingCallback_ThermalMeter, \
\n pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase[A]: %d, pDM_Odm->DefaultOfdmIndex: %d\n",
pDM_Odm->BbSwingIdxCckBase, pDM_Odm->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pDM_Odm->DefaultOfdmIndex));
ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E
if( ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl || pHalData->EEPROMThermalMeter == 0 ||
pHalData->EEPROMThermalMeter == 0xFF)
return;
if( ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl || pHalData->EEPROMThermalMeter == 0 ||
pHalData->EEPROMThermalMeter == 0xFF)
return;
//4 3. Initialize ThermalValues of RFCalibrateInfo
if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n"));
if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n"));
}
//4 4. Calculate average thermal meter
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue;
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++;
if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) //Average times = c.AverageThermalNum
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0;
for(i = 0; i < c.AverageThermalNum; i++)
{
if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i])
{
for(i = 0; i < c.AverageThermalNum; i++) {
if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) {
ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i];
ThermalValue_AVG_count++;
}
}
if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times
{
if(ThermalValue_AVG_count) { //Calculate Average ThermalValue after average enough times
ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter));
("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter));
}
//4 5. Calculate delta, delta_LCK, delta_IQK.
//"delta" here is used to determine whether thermal value changes or not.
@@ -216,183 +273,167 @@ ODM_TXPowerTrackingCallback_ThermalMeter(
delta_IQK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK):(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK));
//4 6. If necessary, do LCK.
if ((delta_LCK >= c.Threshold_IQK)) // Delta temperature is equal to or larger than 20 centigrade.
{
//4 6. If necessary, do LCK.
if ((delta_LCK >= c.Threshold_IQK)) { // Delta temperature is equal to or larger than 20 centigrade.
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK));
pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue;
if(c.PHY_LCCalibrate)
(*c.PHY_LCCalibrate)(pDM_Odm);
}
//3 7. If necessary, move the index of swing table to adjust Tx power.
if (delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
{
//3 7. If necessary, move the index of swing table to adjust Tx power.
if (delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) {
//"delta" here is used to record the absolute value of differrence.
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
#else
delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue);
delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue);
#endif
if (delta >= TXPWR_TRACK_TABLE_SIZE)
delta = TXPWR_TRACK_TABLE_SIZE - 1;
//4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(ThermalValue > pHalData->EEPROMThermalMeter) {
#else
if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) {
#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta]));
("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta]));
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_A] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A];
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A] = deltaSwingTableIdx_TUP_A[delta];
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = deltaSwingTableIdx_TUP_A[delta]; // Record delta swing for mix mode power tracking
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A]));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A]));
if(c.RfPathCount > 1)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta]));
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_B] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B];
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B] = deltaSwingTableIdx_TUP_B[delta];
if(c.RfPathCount > 1) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta]));
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_B] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B];
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B] = deltaSwingTableIdx_TUP_B[delta];
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = deltaSwingTableIdx_TUP_B[delta]; // Record delta swing for mix mode power tracking
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = deltaSwingTableIdx_TUP_B[delta]; // Record delta swing for mix mode power tracking
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B]));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B]));
}
}
else {
} else {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta]));
("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta]));
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_A] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A];
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A] = -1 * deltaSwingTableIdx_TDOWN_A[delta];
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; // Record delta swing for mix mode power tracking
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A]));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A]));
if(c.RfPathCount > 1)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta]));
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_B] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B];
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B] = -1 * deltaSwingTableIdx_TDOWN_B[delta];
if(c.RfPathCount > 1) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta]));
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; // Record delta swing for mix mode power tracking
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_B] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B];
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B] = -1 * deltaSwingTableIdx_TDOWN_B[delta];
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B]));
}
}
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
{
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; // Record delta swing for mix mode power tracking
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B]));
}
}
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("\n\n================================ [Path-%c] Calculating PowerIndexOffset ================================\n", (p == ODM_RF_PATH_A ? 'A' : 'B')));
if (pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] == pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]) // If Thermal value changes but lookup table value still the same
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
else
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]; // Power Index Diff between 2 times Power Tracking
("\n\n================================ [Path-%c] Calculating PowerIndexOffset ================================\n", (p == ODM_RF_PATH_A ? 'A' : 'B')));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("[Path-%c] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n",
(p == ODM_RF_PATH_A ? 'A' : 'B'), pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p], pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p],
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]));
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pDM_Odm->BbSwingIdxOfdmBase[p] + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p];
pDM_Odm->RFCalibrateInfo.CCK_index = pDM_Odm->BbSwingIdxCckBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p];
if (pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] == pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]) // If Thermal value changes but lookup table value still the same
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
else
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]; // Power Index Diff between 2 times Power Tracking
pDM_Odm->BbSwingIdxCck = pDM_Odm->RFCalibrateInfo.CCK_index;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("[Path-%c] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n",
(p == ODM_RF_PATH_A ? 'A' : 'B'), pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p], pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p],
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]));
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pDM_Odm->BbSwingIdxOfdmBase[p] + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p];
pDM_Odm->RFCalibrateInfo.CCK_index = pDM_Odm->BbSwingIdxCckBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p];
pDM_Odm->BbSwingIdxCck = pDM_Odm->RFCalibrateInfo.CCK_index;
pDM_Odm->BbSwingIdxOfdm[p] = pDM_Odm->RFCalibrateInfo.OFDM_index[p];
// *************Print BB Swing Base and Index Offset*************
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n",
pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p]));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'OFDM' final index(%d) = BaseIndex[%c](%d) + PowerIndexOffset(%d)\n",
pDM_Odm->BbSwingIdxOfdm[p], (p == ODM_RF_PATH_A ? 'A' : 'B'), pDM_Odm->BbSwingIdxOfdmBase[p], pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p]));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n",
pDM_Odm->BbSwingIdxCck, pDM_Odm->BbSwingIdxCckBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p]));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'OFDM' final index(%d) = BaseIndex[%c](%d) + PowerIndexOffset(%d)\n",
pDM_Odm->BbSwingIdxOfdm[p], (p == ODM_RF_PATH_A ? 'A' : 'B'), pDM_Odm->BbSwingIdxOfdmBase[p], pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p]));
//4 7.1 Handle boundary conditions of index.
if(pDM_Odm->RFCalibrateInfo.OFDM_index[p] > c.SwingTableSize_OFDM-1)
{
//4 7.1 Handle boundary conditions of index.
if(pDM_Odm->RFCalibrateInfo.OFDM_index[p] > c.SwingTableSize_OFDM-1) {
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = c.SwingTableSize_OFDM-1;
}
else if (pDM_Odm->RFCalibrateInfo.OFDM_index[p] < OFDM_min_index)
{
} else if (pDM_Odm->RFCalibrateInfo.OFDM_index[p] < OFDM_min_index) {
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = OFDM_min_index;
}
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("\n\n========================================================================================================\n"));
("\n\n========================================================================================================\n"));
if(pDM_Odm->RFCalibrateInfo.CCK_index > c.SwingTableSize_CCK-1)
pDM_Odm->RFCalibrateInfo.CCK_index = c.SwingTableSize_CCK-1;
//else if (pDM_Odm->RFCalibrateInfo.CCK_index < 0)
//pDM_Odm->RFCalibrateInfo.CCK_index = 0;
}
else
{
//pDM_Odm->RFCalibrateInfo.CCK_index = 0;
} else {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d\n",
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl, ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d\n",
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl, ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n",
pDM_Odm->RFCalibrateInfo.CCK_index, pDM_Odm->BbSwingIdxCckBase)); //Print Swing base & current
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
{
("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n",
pDM_Odm->RFCalibrateInfo.CCK_index, pDM_Odm->BbSwingIdxCckBase)); //Print Swing base & current
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%c]: %d\n",
pDM_Odm->RFCalibrateInfo.OFDM_index[p], (p == ODM_RF_PATH_A ? 'A' : 'B'), pDM_Odm->BbSwingIdxOfdmBase[p]));
("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%c]: %d\n",
pDM_Odm->RFCalibrateInfo.OFDM_index[p], (p == ODM_RF_PATH_A ? 'A' : 'B'), pDM_Odm->BbSwingIdxOfdmBase[p]));
}
if ((pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A] != 0 ||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B] != 0 ) &&
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
{
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B] != 0 ) &&
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) {
//4 7.2 Configure the Swing Table to adjust Tx Power.
pDM_Odm->RFCalibrateInfo.bTxPowerChanged = TRUE; // Always TRUE after Tx Power is adjusted by power tracking.
pDM_Odm->RFCalibrateInfo.bTxPowerChanged = TRUE; // Always TRUE after Tx Power is adjusted by power tracking.
//
// 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
// to increase TX power. Otherwise, EVM will be bad.
//
// 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.
if (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)
{
if (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature Increasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
("Temperature Increasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
if(c.RfPathCount > 1)
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature Increasing(B): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature Increasing(B): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
}
else if (ThermalValue < pDM_Odm->RFCalibrateInfo.ThermalValue)// Low temperature
{
} else if (ThermalValue < pDM_Odm->RFCalibrateInfo.ThermalValue) { // Low temperature
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature Decreasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
("Temperature Decreasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
if(c.RfPathCount > 1)
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature Decreasing(B): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature Decreasing(B): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
@@ -402,65 +443,57 @@ ODM_TXPowerTrackingCallback_ThermalMeter(
#endif
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E ||
pDM_Odm->SupportICType == ODM_RTL8821 || pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B)
{
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E ||
pDM_Odm->SupportICType == ODM_RTL8821 || pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking MIX_MODE**********\n"));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking BBSWING_MODE**********\n"));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
}
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E ||
pDM_Odm->SupportICType == ODM_RTL8821 || pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking MIX_MODE**********\n"));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel);
}
else
{
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
} else {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking BBSWING_MODE**********\n"));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
}
} else {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E ||
pDM_Odm->SupportICType == ODM_RTL8821 || pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking MIX_MODE**********\n"));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel);
} else {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking BBSWING_MODE**********\n"));
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
}
}
pDM_Odm->BbSwingIdxCckBase = pDM_Odm->BbSwingIdxCck; // Record last time Power Tracking result as base.
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->BbSwingIdxOfdm[p];
pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->BbSwingIdxOfdm[p];
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("pDM_Odm->RFCalibrateInfo.ThermalValue = %d ThermalValue= %d\n", pDM_Odm->RFCalibrateInfo.ThermalValue, ThermalValue));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("pDM_Odm->RFCalibrateInfo.ThermalValue = %d ThermalValue= %d\n", pDM_Odm->RFCalibrateInfo.ThermalValue, ThermalValue));
pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; //Record last Power Tracking Thermal Value
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
#if (RTL8723B_SUPPORT == 0)
// Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).
if ((delta_IQK >= c.Threshold_IQK)) {
if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress)
if ((delta_IQK >= c.Threshold_IQK)) {
if ( ! pDM_Odm->RFCalibrateInfo.bIQKInProgress)
(*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8);
}
#endif
#endif
#endif
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("<===ODM_TXPowerTrackingCallback_ThermalMeter\n"));
pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
}
@@ -473,7 +506,7 @@ ODM_TXPowerTrackingCallback_ThermalMeter(
VOID
ODM_ResetIQKResult(
IN PDM_ODM_T pDM_Odm
IN PDM_ODM_T pDM_Odm
)
{
u1Byte i;
@@ -486,18 +519,17 @@ ODM_ResetIQKResult(
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,("PHY_ResetIQKResult:: settings regs %d default regs %d\n", (u4Byte)(sizeof(pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting)/sizeof(IQK_MATRIX_REGS_SETTING)), IQK_Matrix_Settings_NUM));
//0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc
for(i = 0; i < IQK_Matrix_Settings_NUM; i++)
{
for(i = 0; i < IQK_Matrix_Settings_NUM; i++) {
{
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][0] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][2] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][4] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][6] = 0x100;
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][0] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][2] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][4] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][6] = 0x100;
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][1] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][3] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][5] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][7] = 0x0;
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][1] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][3] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][5] =
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].Value[0][7] = 0x0;
pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[i].bIQKDone = FALSE;
@@ -508,21 +540,18 @@ ODM_ResetIQKResult(
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl)
{
u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] =
u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] =
{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165};
u1Byte place = chnl;
if(chnl > 14)
{
for(place = 14; place<sizeof(channel_all); place++)
{
if(channel_all[place] == chnl)
{
if(chnl > 14) {
for(place = 14; place<sizeof(channel_all); place++) {
if(channel_all[place] == chnl) {
return place-13;
}
}
}
}
return 0;
}

38
backports/drivers/realtek/rtl8812au/hal/OUTSRC/HalPhyRf.h Executable file → Normal file
View File

@@ -17,10 +17,10 @@
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
typedef enum _SPUR_CAL_METHOD {
PLL_RESET,
AFE_PHASE_SEL
@@ -38,37 +38,37 @@ typedef VOID (*FuncLCK)(PDM_ODM_T);
typedef VOID (*FuncSwing)(PDM_ODM_T, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
typedef struct _TXPWRTRACK_CFG {
u1Byte SwingTableSize_CCK;
u1Byte SwingTableSize_CCK;
u1Byte SwingTableSize_OFDM;
u1Byte Threshold_IQK;
u1Byte Threshold_IQK;
u1Byte AverageThermalNum;
u1Byte RfPathCount;
u4Byte ThermalRegAddr;
u4Byte ThermalRegAddr;
FuncSetPwr ODM_TxPwrTrackSetPwr;
FuncIQK DoIQK;
FuncLCK PHY_LCCalibrate;
FuncSwing GetDeltaSwingTable;
FuncSwing GetDeltaSwingTable;
} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG;
void ConfigureTxpowerTrack(
IN PDM_ODM_T pDM_Odm,
OUT PTXPWRTRACK_CFG pConfig
);
IN PDM_ODM_T pDM_Odm,
OUT PTXPWRTRACK_CFG pConfig
);
VOID
ODM_ClearTxPowerTrackingState(
IN PDM_ODM_T pDM_Odm
);
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_TXPowerTrackingCallback_ThermalMeter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER Adapter
IN PADAPTER Adapter
#endif
);
);
@@ -77,13 +77,13 @@ ODM_TXPowerTrackingCallback_ThermalMeter(
VOID
ODM_ResetIQKResult(
IN PDM_ODM_T pDM_Odm
IN PDM_ODM_T pDM_Odm
);
u1Byte
u1Byte
ODM_GetRightChnlPlaceforIQK(
IN u1Byte chnl
);
#endif // #ifndef __HAL_PHY_RF_H__

23
backports/drivers/realtek/rtl8812au/hal/OUTSRC/Mp_Precomp.h Normal file
View File

@@ -0,0 +1,23 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//#include <Precomp.h>
//#include "phydm_precomp.h"
//#include "../phydm_precomp.h"

834
backports/drivers/realtek/rtl8812au/hal/OUTSRC/PhyDM_Adaptivity.c Normal file
View File

@@ -0,0 +1,834 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if WPP_SOFTWARE_TRACE
#include "PhyDM_Adaptivity.tmh"
#endif
#endif
VOID
Phydm_CheckAdaptivity(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) {
if(pDM_Odm->DynamicLinkAdaptivity == TRUE) {
if(pDM_Odm->bLinked && pDM_Odm->bCheck == FALSE) {
Phydm_NHMCounterStatistics(pDM_Odm);
Phydm_CheckEnvironment(pDM_Odm);
} else if(!pDM_Odm->bLinked) {
pDM_Odm->bCheck = FALSE;
}
} else {
pDM_Odm->Adaptivity_enable = TRUE;
if(pDM_Odm->SupportICType & ODM_RTL8814A)
pDM_Odm->adaptivity_flag = FALSE;
else
pDM_Odm->adaptivity_flag = TRUE;
}
} else {
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
}
}
VOID
Phydm_NHMCounterStatisticsInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
//PHY parameters initialize for ac series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, 0xC350); //0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff); //0x994[31:16]=0xffff th_9, th_10
//ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff5c); //0x998=0xffffff5c th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); //0x998=0xffffff52 th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); //0x99c=0xffffffff th_7, th_6, th_5, th_4
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); //0x9a0[7:0]=0xff th_8
//ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 0x7); //0x994[9:8]=3 enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, 0x1); //0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1); //0x9e8[7]=1 max power among all RX ants
} else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
//PHY parameters initialize for n series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0xC350); //0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms
//ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, 0x4e20); //0x894[31:16]=0x4e20 Time duration for NHM unit: 4us, 0x4e20=80ms
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff); //0x890[31:16]=0xffff th_9, th_10
//ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff5c); //0x898=0xffffff5c th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); //0x898=0xffffff52 th_3, th_2, th_1, th_0
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); //0x89c=0xffffffff th_7, th_6, th_5, th_4
ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); //0xe28[7:0]=0xff th_8
//ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x7); //0x890[9:8]=3 enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, 0x1); //0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); //0xc0c[7]=1 max power among all RX ants
}
}
VOID
Phydm_NHMCounterStatistics(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
return;
// Get NHM report
Phydm_GetNHMCounterStatistics(pDM_Odm);
// Reset NHM counter
Phydm_NHMCounterStatisticsReset(pDM_Odm);
}
VOID
Phydm_GetNHMCounterStatistics(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u4Byte value32 = 0;
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord);
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord);
pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0);
pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1)>>8);
}
VOID
Phydm_NHMCounterStatisticsReset(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);
} else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);
}
}
VOID
Phydm_SetEDCCAThreshold(
IN PVOID pDM_VOID,
IN s1Byte H2L,
IN s1Byte L2H
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)L2H);
ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)H2L);
} else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte0, (u1Byte)L2H);
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskByte1, (u1Byte)H2L);
}
}
VOID
Phydm_SetTRxMux(
IN PVOID pDM_VOID,
IN PhyDM_Trx_MUX_Type txMode,
IN PhyDM_Trx_MUX_Type rxMode
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3|BIT2|BIT1, txMode); // set TXmod to standby mode to remove outside noise affect
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22|BIT21|BIT20, rxMode); // set RXmod to standby mode to remove outside noise affect
if(pDM_Odm->RFType > ODM_1T1R) {
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3|BIT2|BIT1, txMode); // set TXmod to standby mode to remove outside noise affect
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22|BIT21|BIT20, rxMode); // set RXmod to standby mode to remove outside noise affect
}
} else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11|BIT10|BIT9|BIT8, txMode); // set TXmod to standby mode to remove outside noise affect
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7|BIT6|BIT5|BIT4, rxMode); // set RXmod to standby mode to remove outside noise affect
if(pDM_Odm->RFType > ODM_1T1R) {
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11|BIT10|BIT9|BIT8, txMode); // set TXmod to standby mode to remove outside noise affect
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7|BIT6|BIT5|BIT4, rxMode); // set RXmod to standby mode to remove outside noise affect
}
}
}
VOID
Phydm_MACEDCCAState(
IN PVOID pDM_VOID,
IN PhyDM_MACEDCCA_Type State
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(State == PhyDM_IGNORE_EDCCA) {
ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1); //ignore EDCCA reg520[15]=1
ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0); //reg524[11]=0
} else { // don't set MAC ignore EDCCA signal
ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0); //don't ignore EDCCA reg520[15]=0
ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); //reg524[11]=1
}
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d \n", State));
}
BOOLEAN
Phydm_CalNHMcnt(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u2Byte Base = 0;
Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1;
if(Base != 0) {
pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base;
pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base;
}
if((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100)
return TRUE; // clean environment
else
return FALSE; //noisy environment
}
VOID
Phydm_CheckEnvironment(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
BOOLEAN isCleanEnvironment = FALSE;
//u1Byte clean = 0;
if(pDM_Odm->bFirstLink == TRUE) {
if(pDM_Odm->SupportICType & ODM_RTL8814A)
pDM_Odm->adaptivity_flag = FALSE;
else
pDM_Odm->adaptivity_flag = TRUE;
pDM_Odm->bFirstLink = FALSE;
return;
} else {
if(pDM_Odm->NHMWait < 3) { // Start enter NHM after 4 NHMWait
pDM_Odm->NHMWait ++;
Phydm_NHMCounterStatistics(pDM_Odm);
return;
} else {
Phydm_NHMCounterStatistics(pDM_Odm);
isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);
if(isCleanEnvironment == TRUE) {
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup; //mode 1
pDM_Odm->TH_EDCCA_HL_diff= pDM_Odm->TH_EDCCA_HL_diff_backup;
#endif
pDM_Odm->Adaptivity_enable = TRUE;
if(pDM_Odm->SupportICType & ODM_RTL8814A)
pDM_Odm->adaptivity_flag = FALSE;
else
pDM_Odm->adaptivity_flag = TRUE;
} else {
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);
#else
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; // for AP mode 2
pDM_Odm->TH_EDCCA_HL_diff= pDM_Odm->TH_EDCCA_HL_diff_mode2;
#endif
pDM_Odm->adaptivity_flag = FALSE;
pDM_Odm->Adaptivity_enable = FALSE;
}
pDM_Odm->bFirstLink = TRUE;
pDM_Odm->bCheck = TRUE;
}
}
}
VOID
Phydm_SearchPwdBLowerBound(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u4Byte value32 =0;
u1Byte cnt, IGI_Pause = 0x7f, IGI_Resume = 0x20, IGI = 0x50; //IGI = 0x50 for cal EDCCA lower bound
u1Byte txEdcca1 = 0, txEdcca0 = 0;
BOOLEAN bAdjust=TRUE;
s1Byte TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32;
s1Byte Diff;
Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
ODM_Write_DIG(pDM_Odm, IGI_Pause);
Diff = IGI_target -(s1Byte)IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
if(TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
ODM_delay_ms(5);
while(bAdjust) {
for(cnt=0; cnt<20; cnt ++) {
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
value32 = ODM_GetBBReg(pDM_Odm,ODM_REG_RPT_11N, bMaskDWord);
else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
value32 = ODM_GetBBReg(pDM_Odm,ODM_REG_RPT_11AC, bMaskDWord);
if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8723B|ODM_RTL8188E)))
txEdcca1 = txEdcca1 + 1;
else if(value32 & BIT29)
txEdcca1 = txEdcca1 + 1;
else
txEdcca0 = txEdcca0 + 1;
}
if(txEdcca1 > 9 ) {
IGI = IGI -1;
TH_L2H_dmc = TH_L2H_dmc + 1;
if(TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
txEdcca1 = 0;
txEdcca0 = 0;
if(TH_L2H_dmc == 10) {
bAdjust = FALSE;
pDM_Odm->H2L_lb = TH_H2L_dmc;
pDM_Odm->L2H_lb = TH_L2H_dmc;
pDM_Odm->Adaptivity_IGI_upper = IGI;
}
} else {
bAdjust = FALSE;
pDM_Odm->H2L_lb = TH_H2L_dmc;
pDM_Odm->L2H_lb = TH_L2H_dmc;
pDM_Odm->Adaptivity_IGI_upper = IGI;
}
}
Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);
ODM_Write_DIG(pDM_Odm, IGI_Resume);
Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); // resume to no link state
}
VOID
Phydm_AdaptivityInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER pAdapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
pDM_Odm->Carrier_Sense_enable = (BOOLEAN)pMgntInfo->RegEnableCarrierSense;
pDM_Odm->DynamicLinkAdaptivity = (BOOLEAN)pMgntInfo->RegDmLinkAdaptivity;
#elif(DM_ODM_SUPPORT_TYPE == ODM_CE)
pDM_Odm->Carrier_Sense_enable = (pDM_Odm->Adapter->registrypriv.adaptivity_mode!=0)?TRUE:FALSE;
pDM_Odm->DynamicLinkAdaptivity = (pDM_Odm->Adapter->registrypriv.adaptivity_dml!=0)?TRUE:FALSE;
#endif
#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
if(pDM_Odm->Carrier_Sense_enable == FALSE) {
#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
if( pMgntInfo->RegL2HForAdaptivity != 0 )
pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;
else
#endif
pDM_Odm->TH_L2H_ini = 0xf5; // -7
} else {
#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
if( pMgntInfo->RegL2HForAdaptivity != 0 )
pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity;
else
#endif
pDM_Odm->TH_L2H_ini = 0xa;
}
#if(DM_ODM_SUPPORT_TYPE == ODM_WIN)
if( pMgntInfo->RegHLDiffForAdaptivity != 0 )
pDM_Odm->TH_EDCCA_HL_diff = pMgntInfo->RegHLDiffForAdaptivity;
else
#endif
pDM_Odm->TH_EDCCA_HL_diff = 7;
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
if(pDM_Odm->Carrier_Sense_enable) {
pDM_Odm->TH_L2H_ini = 10;
pDM_Odm->TH_EDCCA_HL_diff = 7;
} else {
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_backup; //set by mib
pDM_Odm->TH_EDCCA_HL_diff = 7;
}
pDM_Odm->TH_L2H_ini_mode2 = 20;
pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8;
//pDM_Odm->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini;
pDM_Odm->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff ;
if(priv->pshare->rf_ft_var.adaptivity_enable == 2)
pDM_Odm->DynamicLinkAdaptivity = TRUE;
else
pDM_Odm->DynamicLinkAdaptivity = FALSE;
#endif
pDM_Odm->IGI_Base = 0x32;
pDM_Odm->IGI_target = 0x1c;
pDM_Odm->FABound = 6000;
pDM_Odm->H2L_lb= 0;
pDM_Odm->L2H_lb= 0;
pDM_Odm->Adaptivity_IGI_upper = 0;
pDM_Odm->NHMWait = 0;
pDM_Odm->bCheck = FALSE;
pDM_Odm->bFirstLink = TRUE;
pDM_Odm->Adaptivity_enable = FALSE; // use this flag to judge enable or disable
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
//Search pwdB lower bound
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT9|BIT8, 0x0); /* set forgetting factor = 0 for all n series IC*/
} else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);
ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIReadBack, BIT1|BIT0, 0x0);
}
if (pDM_Odm->SupportICType & ODM_RTL8814A) { /* 8814a no need to find pwdB lower bound, maybe */
ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT, BIT30|BIT29|BIT28, 0x7); /* interfernce need > 2^x us, and then EDCCA will be 1 */
ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_POWER_CAL, BIT5, 1); /* 0: mean, 1:max pwdB */
ODM_SetBBReg(pDM_Odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT29|BIT28, 0x1); /* 0 : rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out */
} else
Phydm_SearchPwdBLowerBound(pDM_Odm);
}
VOID
Phydm_Adaptivity(
IN PVOID pDM_VOID,
IN u1Byte IGI
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
s1Byte TH_L2H_dmc, TH_H2L_dmc;
s1Byte Diff, IGI_target;
//BOOLEAN EDCCA_State = FALSE;
PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER pAdapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
BOOLEAN bFwCurrentInPSMode=FALSE;
PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
// Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
if(bFwCurrentInPSMode)
return;
#endif
if(!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)) {
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Go to odm_DynamicEDCCA() \n"));
// Add by Neil Chen to enable edcca to MP Platform
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
// Adjust EDCCA.
if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
Phydm_DynamicEDCCA(pDM_Odm);
#endif
return;
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
if(pMgntInfo->RegEnableAdaptivity== 2) {
if(pDM_Odm->Carrier_Sense_enable == FALSE) { // check domain Code for Adaptivity or CarrierSense
if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
!(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d \n", pDM_Odm->odm_Regulation5G));
return;
}
else if((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
!(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d \n", pDM_Odm->odm_Regulation2_4G));
return;
} else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n"));
return;
}
} else {
if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
!(pDM_Odm->odm_Regulation5G == REGULATION_MKK || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));
return;
}
else if((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
!(pDM_Odm->odm_Regulation2_4G == REGULATION_MKK || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));
return;
} else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));
return;
}
}
}
#endif
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====> \n"));
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d\n",
pDM_Odm->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
// fix AC series when enable EDCCA hang issue
ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 1); //ADC_mask disable
ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); //ADC_mask enable
}
if(*pDM_Odm->pBandWidth == ODM_BW20M) //CHANNEL_WIDTH_20
IGI_target = pDM_Odm->IGI_Base;
else if(*pDM_Odm->pBandWidth == ODM_BW40M)
IGI_target = pDM_Odm->IGI_Base + 2;
else if(*pDM_Odm->pBandWidth == ODM_BW80M)
IGI_target = pDM_Odm->IGI_Base + 2;
else
IGI_target = pDM_Odm->IGI_Base;
pDM_Odm->IGI_target = (u1Byte) IGI_target;
if(*pDM_Odm->pChannel >= 149) { // Band4 -> for AP : mode2
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
if(pDM_Odm->bLinked) {
if(pDM_Odm->SupportICType & ODM_RTL8814A) {
L2H_nolink_Band4 = (s1Byte)pDM_Odm->TH_L2H_ini_mode2 + IGI_target;
H2L_nolink_Band4 = L2H_nolink_Band4 - pDM_Odm->TH_EDCCA_HL_diff_mode2;
} else {
Diff = IGI_target -(s1Byte)IGI;
L2H_nolink_Band4 = pDM_Odm->TH_L2H_ini_mode2 + Diff;
if(L2H_nolink_Band4 > 10)
L2H_nolink_Band4 = 10;
H2L_nolink_Band4 = L2H_nolink_Band4 - pDM_Odm->TH_EDCCA_HL_diff_mode2;
}
} else {
L2H_nolink_Band4 = 0x7f;
H2L_nolink_Band4 = 0x7f;
}
Phydm_SetEDCCAThreshold(pDM_Odm, H2L_nolink_Band4, L2H_nolink_Band4);
return;
#endif
}
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, FABound = %d, DynamicLinkAdaptivity = %d\n",
(*pDM_Odm->pBandWidth==ODM_BW80M)?"80M":((*pDM_Odm->pBandWidth==ODM_BW40M)?"40M":"20M"), IGI_target, pDM_Odm->FABound, pDM_Odm->DynamicLinkAdaptivity));
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, AdapIGIUpper= 0x%x, adaptivity_flag = %d, Adaptivity_enable = %d\n",
pDM_Odm->RSSI_Min, pDM_Odm->Adaptivity_IGI_upper, pDM_Odm->adaptivity_flag, pDM_Odm->Adaptivity_enable));
if((pDM_Odm->DynamicLinkAdaptivity == TRUE) && (!pDM_Odm->bLinked) && (pDM_Odm->Adaptivity_enable == FALSE)) {
Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n"));
return;
}
#if (!(DM_ODM_SUPPORT_TYPE & ODM_AP))
else if((pDM_Odm->DynamicLinkAdaptivity == TRUE) && (pDM_Odm->Adaptivity_enable == FALSE)) {
Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) disable EDCCA, return!!\n"));
return;
}
#endif
if((pDM_Odm->SupportICType & ODM_RTL8723B) && (pDM_Odm->CutVersion & ODM_CUT_B) && (FalseAlmCnt->Cnt_all > pDM_Odm->FABound) && (IGI == pDM_Odm->Adaptivity_IGI_upper)) {
pDM_Odm->Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper + 3;
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("FA > %d, IGI upper bound + 3!!\n", pDM_Odm->FABound));
}
if(pDM_Odm->SupportICType & ODM_RTL8814A) {
TH_L2H_dmc = (s1Byte)pDM_Odm->TH_L2H_ini + IGI_target;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
} else {
Diff = IGI_target -(s1Byte)IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
if(TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
//replace lower bound to prevent EDCCA always equal 1
if(TH_H2L_dmc < pDM_Odm->H2L_lb)
TH_H2L_dmc = pDM_Odm->H2L_lb;
if(TH_L2H_dmc < pDM_Odm->L2H_lb)
TH_L2H_dmc = pDM_Odm->L2H_lb;
}
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc));
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
return;
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
Phydm_AdaptivityBSOD(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
u1Byte count = 0;
u4Byte u4Value;
/*
1. turn off RF (TRX Mux in standby mode)
2. H2C mac id drop
3. ignore EDCCA
4. wait for clear FIFO
5. don't ignore EDCCA
6. turn on RF (TRX Mux in TRx mdoe)
7. H2C mac id resume
*/
RT_TRACE(COMP_MLME, DBG_WARNING, ("MAC id drop packet!!!!!\n"));
pAdapter->dropPktByMacIdCnt++;
pMgntInfo->bDropPktInProgress = TRUE;
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_MAX_Q_PAGE_NUM, (pu1Byte)(&u4Value));
RT_TRACE(COMP_INIT, DBG_LOUD, ("Queue Reserved Page Number = 0x%08x\n", u4Value));
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));
RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));
#if 1
//3 Standby mode
Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
ODM_Write_DIG(pDM_Odm, 0x20);
//3 H2C mac id drop
MacIdIndicateDisconnect(pAdapter);
//3 Ignore EDCCA
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
delay_ms(50);
count = 5;
#else
do {
u8Byte diffTime, curTime, oldestTime;
u1Byte queueIdx
//3 Standby mode
Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
ODM_Write_DIG(pDM_Odm, 0x20);
//3 H2C mac id drop
MacIdIndicateDisconnect(pAdapter);
//3 Ignore EDCCA
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
count++;
delay_ms(10);
// Check latest packet
curTime = PlatformGetCurrentTime();
oldestTime = 0xFFFFFFFFFFFFFFFF;
for(queueIdx = 0; queueIdx < MAX_TX_QUEUE; queueIdx++) {
if(!IS_DATA_QUEUE(queueIdx))
continue;
if(!pAdapter->bTcbBusyQEmpty[queueIdx]) {
RT_TRACE(COMP_MLME, DBG_WARNING, ("oldestTime = %llu\n", oldestTime));
RT_TRACE(COMP_MLME, DBG_WARNING, ("Q[%d] = %llu\n", queueIdx, pAdapter->firstTcbSysTime[queueIdx]));
if(pAdapter->firstTcbSysTime[queueIdx] < oldestTime) {
oldestTime = pAdapter->firstTcbSysTime[queueIdx];
}
}
}
diffTime = curTime - oldestTime;
RT_TRACE(COMP_MLME, DBG_WARNING, ("diff s = %llu\n", (diffTime/1000000)));
} while(((diffTime/1000000) >= 4) && (oldestTime != 0xFFFFFFFFFFFFFFFF));
#endif
//3 Resume EDCCA
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
//3 Turn on TRx mode
Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);
ODM_Write_DIG(pDM_Odm, 0x20);
//3 Resume H2C macid
MacIdRecoverMediaStatus(pAdapter);
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));
RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));
pMgntInfo->bDropPktInProgress = FALSE;
RT_TRACE(COMP_MLME, DBG_WARNING, ("End of MAC id drop packet, spent %dms\n", count*10));
}
VOID
Phydm_EnableEDCCA(
IN PVOID pDM_VOID
)
{
// This should be moved out of OUTSRC
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
// Enable EDCCA. The value is suggested by SD3 Wilson.
//
// Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13.
//
if((pDM_Odm->SupportICType == ODM_RTL8723A)&&(IS_WIRELESS_MODE_G(pAdapter))) {
//PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x00);
ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x00);
ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0xFD);
} else {
//PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x03);
ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x03);
ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0x00);
}
//PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold+2, 0x00);
}
VOID
Phydm_DisableEDCCA(
IN PVOID pDM_VOID
)
{
// Disable EDCCA..
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x7f);
ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold+2, 0x7f);
}
//
// Description: According to initial gain value to determine to enable or disable EDCCA.
//
// Suggested by SD3 Wilson. Added by tynli. 2011.11.25.
//
VOID
Phydm_DynamicEDCCA(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u1Byte RegC50, RegC58;
BOOLEAN bEDCCAenable = FALSE;
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
BOOLEAN bFwCurrentInPSMode=FALSE;
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
// Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
if(bFwCurrentInPSMode)
return;
#endif
//
// 2013/11/14 Ken According to BB team Jame's suggestion, we need to disable soft AP mode EDCCA.
// 2014/01/08 MH For Miracst AP mode test. We need to disable EDCCA. Otherwise, we may stop
// to send beacon in noisy environment or platform.
//
if(ACTING_AS_AP(pAdapter) || ACTING_AS_AP(GetFirstAPAdapter(pAdapter)))
//if(ACTING_AS_AP(pAdapter))
{
ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("At least One Port as AP disable EDCCA\n"));
Phydm_DisableEDCCA(pDM_Odm);
if(pHalData->bPreEdccaEnable)
Phydm_DisableEDCCA(pDM_Odm);
pHalData->bPreEdccaEnable = FALSE;
return;
}
RegC50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);
RegC58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0);
if((RegC50 > 0x28 && RegC58 > 0x28) ||
((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50>0x26)) ||
(pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28)) {
if(!pHalData->bPreEdccaEnable) {
Phydm_EnableEDCCA(pDM_Odm);
pHalData->bPreEdccaEnable = TRUE;
}
} else if((RegC50 < 0x25 && RegC58 < 0x25) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25)) {
if(pHalData->bPreEdccaEnable) {
Phydm_DisableEDCCA(pDM_Odm);
pHalData->bPreEdccaEnable = FALSE;
}
}
}
#endif

141
backports/drivers/realtek/rtl8812au/hal/OUTSRC/PhyDM_Adaptivity.h Normal file
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@@ -0,0 +1,141 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMADAPTIVITY_H__
#define __PHYDMADAPTIVITY_H__
#define ADAPTIVITY_VERSION "8.2"
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
typedef enum _tag_PhyDM_REGULATION_Type {
REGULATION_FCC = 0,
REGULATION_MKK = 1,
REGULATION_ETSI = 2,
REGULATION_WW = 3,
MAX_REGULATION_NUM = 4
} PhyDM_REGULATION_TYPE;
#endif
typedef enum tag_PhyDM_TRx_MUX_Type {
PhyDM_SHUTDOWN = 0,
PhyDM_STANDBY_MODE = 1,
PhyDM_TX_MODE = 2,
PhyDM_RX_MODE = 3
} PhyDM_Trx_MUX_Type;
typedef enum tag_PhyDM_MACEDCCA_Type {
PhyDM_IGNORE_EDCCA = 0,
PhyDM_DONT_IGNORE_EDCCA = 1
} PhyDM_MACEDCCA_Type;
VOID
Phydm_CheckAdaptivity(
IN PVOID pDM_VOID
);
VOID
Phydm_CheckEnvironment(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatisticsInit(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatistics(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatisticsReset(
IN PVOID pDM_VOID
);
VOID
Phydm_GetNHMCounterStatistics(
IN PVOID pDM_VOID
);
VOID
Phydm_MACEDCCAState(
IN PVOID pDM_VOID,
IN PhyDM_MACEDCCA_Type State
);
VOID
Phydm_SetEDCCAThreshold(
IN PVOID pDM_VOID,
IN s1Byte H2L,
IN s1Byte L2H
);
VOID
Phydm_SetTRxMux(
IN PVOID pDM_VOID,
IN PhyDM_Trx_MUX_Type txMode,
IN PhyDM_Trx_MUX_Type rxMode
);
BOOLEAN
Phydm_CalNHMcnt(
IN PVOID pDM_VOID
);
VOID
Phydm_SearchPwdBLowerBound(
IN PVOID pDM_VOID
);
VOID
Phydm_AdaptivityInit(
IN PVOID pDM_VOID
);
VOID
Phydm_Adaptivity(
IN PVOID pDM_VOID,
IN u1Byte IGI
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
Phydm_DisableEDCCA(
IN PVOID pDM_VOID
);
VOID
Phydm_DynamicEDCCA(
IN PVOID pDM_VOID
);
VOID
Phydm_AdaptivityBSOD(
IN PVOID pDM_VOID
);
#endif
#endif

14176
backports/drivers/realtek/rtl8812au/hal/OUTSRC/odm.c
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2366
backports/drivers/realtek/rtl8812au/hal/OUTSRC/odm.h
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File diff suppressed because it is too large Load Diff

2269
backports/drivers/realtek/rtl8812au/hal/OUTSRC/odm_AntDiv.c
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File diff suppressed because it is too large Load Diff

136
backports/drivers/realtek/rtl8812au/hal/OUTSRC/odm_AntDiv.h
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@@ -1,136 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODMANTDIV_H__
#define __ODMANTDIV_H__
#define ANT1_2G 0 // = ANT2_5G
#define ANT2_2G 1 // = ANT1_5G
//Antenna Diversty Control Type
#define ODM_AUTO_ANT 0
#define ODM_FIX_MAIN_ANT 1
#define ODM_FIX_AUX_ANT 2
#define TX_BY_REG 0
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#define ODM_RTL8881A 0 //Just for windows driver to jointly use ODM-driver
#endif
#define ODM_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)
#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E)
#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A)
#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_ANTDIV_2G BIT0
#define ODM_ANTDIV_5G BIT1
#define ANTDIV_ON 1
#define ANTDIV_OFF 0
VOID
ODM_AntDivInit(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_AntDiv(
IN PDM_ODM_T pDM_Odm
);
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
VOID
ODM_UpdateRxIdleAnt(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Ant
);
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
ODM_SW_AntDiv_Callback(
IN PRT_TIMER pTimer
);
VOID
ODM_SW_AntDiv_WorkitemCallback(
IN PVOID pContext
);
#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
VOID
ODM_SW_AntDiv_Callback(void *FunctionContext);
#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#endif
#if(RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
VOID
odm_FastAntTraining(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_FastAntTrainingCallback(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_FastAntTrainingWorkItemCallback(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif
VOID
ODM_Process_RSSIForAntDiv(
IN OUT PDM_ODM_T pDM_Odm,
IN PODM_PHY_INFO_T pPhyInfo,
IN PODM_PACKET_INFO_T pPktinfo
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
ODM_SetTxAntByTxInfo(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte pDesc,
IN u1Byte macId
);
#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
ODM_SetTxAntByTxInfo(
//IN PDM_ODM_T pDM_Odm,
struct rtl8192cd_priv *priv,
struct tx_desc *pdesc,
struct tx_insn *txcfg,
unsigned short aid
);
#endif
#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
#endif //#ifndef __ODMANTDIV_H__

629
backports/drivers/realtek/rtl8812au/hal/OUTSRC/odm_debug.c
View File

@@ -1,629 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "odm_precomp.h"
VOID
ODM_InitDebugSetting(
IN PDM_ODM_T pDM_Odm
)
{
pDM_Odm->DebugLevel = ODM_DBG_LOUD;
pDM_Odm->DebugComponents =
\
#if DBG
//BB Functions
// ODM_COMP_DIG |
// ODM_COMP_RA_MASK |
// ODM_COMP_DYNAMIC_TXPWR |
// ODM_COMP_FA_CNT |
// ODM_COMP_RSSI_MONITOR |
// ODM_COMP_CCK_PD |
// ODM_COMP_ANT_DIV |
// ODM_COMP_PWR_SAVE |
// ODM_COMP_PWR_TRAIN |
// ODM_COMP_RATE_ADAPTIVE |
// ODM_COMP_PATH_DIV |
// ODM_COMP_DYNAMIC_PRICCA |
// ODM_COMP_RXHP |
// ODM_COMP_MP |
// ODM_COMP_DYNAMIC_ATC |
//MAC Functions
// ODM_COMP_EDCA_TURBO |
// ODM_COMP_EARLY_MODE |
//RF Functions
// ODM_COMP_TX_PWR_TRACK |
// ODM_COMP_RX_GAIN_TRACK |
// ODM_COMP_CALIBRATION |
//Common
// ODM_COMP_COMMON |
// ODM_COMP_INIT |
// ODM_COMP_PSD |
#endif
0;
}
#if 0
/*------------------Declare variable-----------------------
// Define debug flag array for common debug print macro. */
u4Byte ODM_DBGP_Type[ODM_DBGP_TYPE_MAX];
/* Define debug print header for every service module. */
ODM_DBGP_HEAD_T ODM_DBGP_Head;
/*-----------------------------------------------------------------------------
* Function: DBGP_Flag_Init
*
* Overview: Refresh all debug print control flag content to zero.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 10/20/2006 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
extern void ODM_DBGP_Flag_Init(void)
{
u1Byte i;
for (i = 0; i < ODM_DBGP_TYPE_MAX; i++)
{
ODM_DBGP_Type[i] = 0;
}
#ifndef ADSL_AP_BUILD_WORKAROUND
#if DBG
// 2010/06/02 MH Free build driver can not out any debug message!!!
// Init Debug flag enable condition
ODM_DBGP_Type[FINIT] = \
// INIT_EEPROM |
// INIT_TxPower |
// INIT_IQK |
// INIT_RF |
0;
ODM_DBGP_Type[FDM] = \
// WA_IOT |
// DM_PWDB |
// DM_Monitor |
// DM_DIG |
// DM_EDCA_Turbo |
// DM_BT30 |
0;
ODM_DBGP_Type[FIOCTL] = \
// IOCTL_IRP |
// IOCTL_IRP_DETAIL |
// IOCTL_IRP_STATISTICS |
// IOCTL_IRP_HANDLE |
// IOCTL_BT_HCICMD |
// IOCTL_BT_HCICMD_DETAIL |
// IOCTL_BT_HCICMD_EXT |
// IOCTL_BT_EVENT |
// IOCTL_BT_EVENT_DETAIL |
// IOCTL_BT_EVENT_PERIODICAL |
// IOCTL_BT_TX_ACLDATA |
// IOCTL_BT_TX_ACLDATA_DETAIL |
// IOCTL_BT_RX_ACLDATA |
// IOCTL_BT_RX_ACLDATA_DETAIL |
// IOCTL_BT_TP |
// IOCTL_STATE |
// IOCTL_BT_LOGO |
// IOCTL_CALLBACK_FUN |
// IOCTL_PARSE_BT_PKT |
0;
ODM_DBGP_Type[FBT] = \
// BT_TRACE |
0;
ODM_DBGP_Type[FEEPROM] = \
// EEPROM_W |
// EFUSE_PG |
// EFUSE_READ_ALL |
// EFUSE_ANALYSIS |
// EFUSE_PG_DETAIL |
0;
ODM_DBGP_Type[FDBG_CTRL] = \
// DBG_CTRL_TRACE |
// DBG_CTRL_INBAND_NOISE |
0;
// 2011/07/20 MH Add for short cut
ODM_DBGP_Type[FSHORT_CUT] = \
// SHCUT_TX |
// SHCUT_RX |
0;
#endif
#endif
/* Define debug header of every service module. */
//ODM_DBGP_Head.pMANS = "\n\r[MANS] ";
//ODM_DBGP_Head.pRTOS = "\n\r[RTOS] ";
//ODM_DBGP_Head.pALM = "\n\r[ALM] ";
//ODM_DBGP_Head.pPEM = "\n\r[PEM] ";
//ODM_DBGP_Head.pCMPK = "\n\r[CMPK] ";
//ODM_DBGP_Head.pRAPD = "\n\r[RAPD] ";
//ODM_DBGP_Head.pTXPB = "\n\r[TXPB] ";
//ODM_DBGP_Head.pQUMG = "\n\r[QUMG] ";
} /* DBGP_Flag_Init */
#endif
#if 0
u4Byte GlobalDebugLevel = DBG_LOUD;
//
// 2009/06/22 MH Allow Fre build to print none debug info at init time.
//
#if DBG
u8Byte GlobalDebugComponents = \
// COMP_TRACE |
// COMP_DBG |
// COMP_INIT |
// COMP_OID_QUERY |
// COMP_OID_SET |
// COMP_RECV |
// COMP_SEND |
// COMP_IO |
// COMP_POWER |
// COMP_MLME |
// COMP_SCAN |
// COMP_SYSTEM |
// COMP_SEC |
// COMP_AP |
// COMP_TURBO |
// COMP_QOS |
// COMP_AUTHENTICATOR |
// COMP_BEACON |
// COMP_ANTENNA |
// COMP_RATE |
// COMP_EVENTS |
// COMP_FPGA |
// COMP_RM |
// COMP_MP |
// COMP_RXDESC |
// COMP_CKIP |
// COMP_DIG |
// COMP_TXAGC |
// COMP_HIPWR |
// COMP_HALDM |
// COMP_RSNA |
// COMP_INDIC |
// COMP_LED |
// COMP_RF |
// COMP_DUALMACSWITCH |
// COMP_EASY_CONCURRENT |
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
// COMP_HT |
// COMP_POWER_TRACKING |
// COMP_RX_REORDER |
// COMP_AMSDU |
// COMP_WPS |
// COMP_RATR |
// COMP_RESET |
// COMP_CMD |
// COMP_EFUSE |
// COMP_MESH_INTERWORKING |
// COMP_CCX |
// COMP_IOCTL |
// COMP_GP |
// COMP_TXAGG |
// COMP_BB_POWERSAVING |
// COMP_SWAS |
// COMP_P2P |
// COMP_MUX |
// COMP_FUNC |
// COMP_TDLS |
// COMP_OMNIPEEK |
// COMP_PSD |
0;
#else
u8Byte GlobalDebugComponents = 0;
#endif
#if (RT_PLATFORM==PLATFORM_LINUX)
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0))
EXPORT_SYMBOL(GlobalDebugComponents);
EXPORT_SYMBOL(GlobalDebugLevel);
#endif
#endif
/*------------------Declare variable-----------------------
// Define debug flag array for common debug print macro. */
u4Byte DBGP_Type[DBGP_TYPE_MAX];
/* Define debug print header for every service module. */
DBGP_HEAD_T DBGP_Head;
/*-----------------------------------------------------------------------------
* Function: DBGP_Flag_Init
*
* Overview: Refresh all debug print control flag content to zero.
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 10/20/2006 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
extern void DBGP_Flag_Init(void)
{
u1Byte i;
for (i = 0; i < DBGP_TYPE_MAX; i++)
{
DBGP_Type[i] = 0;
}
#if DBG
// 2010/06/02 MH Free build driver can not out any debug message!!!
// Init Debug flag enable condition
DBGP_Type[FINIT] = \
// INIT_EEPROM |
// INIT_TxPower |
// INIT_IQK |
// INIT_RF |
0;
DBGP_Type[FDM] = \
// WA_IOT |
// DM_PWDB |
// DM_Monitor |
// DM_DIG |
// DM_EDCA_Turbo |
// DM_BT30 |
0;
DBGP_Type[FIOCTL] = \
// IOCTL_IRP |
// IOCTL_IRP_DETAIL |
// IOCTL_IRP_STATISTICS |
// IOCTL_IRP_HANDLE |
// IOCTL_BT_HCICMD |
// IOCTL_BT_HCICMD_DETAIL |
// IOCTL_BT_HCICMD_EXT |
// IOCTL_BT_EVENT |
// IOCTL_BT_EVENT_DETAIL |
// IOCTL_BT_EVENT_PERIODICAL |
// IOCTL_BT_TX_ACLDATA |
// IOCTL_BT_TX_ACLDATA_DETAIL |
// IOCTL_BT_RX_ACLDATA |
// IOCTL_BT_RX_ACLDATA_DETAIL |
// IOCTL_BT_TP |
// IOCTL_STATE |
// IOCTL_BT_LOGO |
// IOCTL_CALLBACK_FUN |
// IOCTL_PARSE_BT_PKT |
0;
DBGP_Type[FBT] = \
// BT_TRACE |
0;
DBGP_Type[FEEPROM] = \
// EEPROM_W |
// EFUSE_PG |
// EFUSE_READ_ALL |
// EFUSE_ANALYSIS |
// EFUSE_PG_DETAIL |
0;
DBGP_Type[FDBG_CTRL] = \
// DBG_CTRL_TRACE |
// DBG_CTRL_INBAND_NOISE |
0;
// 2011/07/20 MH Add for short cut
DBGP_Type[FSHORT_CUT] = \
// SHCUT_TX |
// SHCUT_RX |
0;
#endif
/* Define debug header of every service module. */
DBGP_Head.pMANS = "\n\r[MANS] ";
DBGP_Head.pRTOS = "\n\r[RTOS] ";
DBGP_Head.pALM = "\n\r[ALM] ";
DBGP_Head.pPEM = "\n\r[PEM] ";
DBGP_Head.pCMPK = "\n\r[CMPK] ";
DBGP_Head.pRAPD = "\n\r[RAPD] ";
DBGP_Head.pTXPB = "\n\r[TXPB] ";
DBGP_Head.pQUMG = "\n\r[QUMG] ";
} /* DBGP_Flag_Init */
/*-----------------------------------------------------------------------------
* Function: DBG_PrintAllFlag
*
* Overview: Print All debug flag
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 12/10/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
extern void DBG_PrintAllFlag(void)
{
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 0 FQoS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 1 FTX\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 2 FRX\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 3 FSEC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 4 FMGNT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 5 FMLME\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 6 FRESOURCE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 7 FBEACON\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 8 FISR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 9 FPHY\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 11 FMP\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 12 FPWR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 13 FDM\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 14 FDBG_CTRL\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 15 FC2H\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("DBGFLAG 16 FBT\n"));
} // DBG_PrintAllFlag
extern void DBG_PrintAllComp(void)
{
u1Byte i;
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("GlobalDebugComponents Definition\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT0 COMP_TRACE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT1 COMP_DBG\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT2 COMP_INIT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT3 COMP_OID_QUERY\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT4 COMP_OID_SET\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT5 COMP_RECV\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT6 COMP_SEND\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT7 COMP_IO\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT8 COMP_POWER\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT9 COMP_MLME\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT10 COMP_SCAN\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT11 COMP_SYSTEM\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT12 COMP_SEC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT13 COMP_AP\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT14 COMP_TURBO\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT15 COMP_QOS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT16 COMP_AUTHENTICATOR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT17 COMP_BEACON\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT18 COMP_BEACON\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT19 COMP_RATE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT20 COMP_EVENTS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT21 COMP_FPGA\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT22 COMP_RM\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT23 COMP_MP\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT24 COMP_RXDESC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT25 COMP_CKIP\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT26 COMP_DIG\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT27 COMP_TXAGC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT28 COMP_HIPWR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT29 COMP_HALDM\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT30 COMP_RSNA\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT31 COMP_INDIC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT32 COMP_LED\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT33 COMP_RF\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT34 COMP_HT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT35 COMP_POWER_TRACKING\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT36 COMP_POWER_TRACKING\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT37 COMP_AMSDU\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT38 COMP_WPS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT39 COMP_RATR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT40 COMP_RESET\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT41 COMP_CMD\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT42 COMP_EFUSE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT43 COMP_MESH_INTERWORKING\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT43 COMP_CCX\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("GlobalDebugComponents = %"i64fmt"x\n", GlobalDebugComponents));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("Enable DBG COMP ="));
for (i = 0; i < 64; i++)
{
if (GlobalDebugComponents & ((u8Byte)0x1 << i) )
{
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT%02d |\n", i));
}
}
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("\n"));
} // DBG_PrintAllComp
/*-----------------------------------------------------------------------------
* Function: DBG_PrintFlagEvent
*
* Overview: Print dedicated debug flag event
*
* Input: NONE
*
* Output: NONE
*
* Return: NONE
*
* Revised History:
* When Who Remark
* 12/10/2008 MHC Create Version 0.
*
*---------------------------------------------------------------------------*/
extern void DBG_PrintFlagEvent(u1Byte DbgFlag)
{
switch(DbgFlag)
{
case FQoS:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 QoS_INIT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 QoS_VISTA\n"));
break;
case FTX:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 TX_DESC\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 TX_DESC_TID\n"));
break;
case FRX:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 RX_DATA\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 RX_PHY_STS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 RX_PHY_SS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 RX_PHY_SQ\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 RX_PHY_ASTS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 5 RX_ERR_LEN\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 6 RX_DEFRAG\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 7 RX_ERR_RATE\n"));
break;
case FSEC:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("NA\n"));
break;
case FMGNT:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("NA\n"));
break;
case FMLME:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 MEDIA_STS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 LINK_STS\n"));
break;
case FRESOURCE:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 OS_CHK\n"));
break;
case FBEACON:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 BCN_SHOW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 BCN_PEER\n"));
break;
case FISR:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 ISR_CHK\n"));
break;
case FPHY:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 PHY_BBR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 PHY_BBW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 PHY_RFR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 PHY_RFW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 PHY_MACR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 5 PHY_MACW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 6 PHY_ALLR\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 7 PHY_ALLW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 8 PHY_TXPWR\n"));
break;
case FMP:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 MP_RX\n"));
break;
case FEEPROM:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 EEPROM_W\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 EFUSE_PG\n"));
break;
case FPWR:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 LPS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 IPS\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 PWRSW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 PWRHW\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 4 PWRHAL\n"));
break;
case FDM:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 WA_IOT\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 DM_PWDB\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 DM_Monitor\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 3 DM_DIG\n"));
break;
case FDBG_CTRL:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 DBG_CTRL_TRACE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 DBG_CTRL_INBAND_NOISE\n"));
break;
case FC2H:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 C2H_Summary\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 C2H_PacketData\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 2 C2H_ContentData\n"));
break;
case FBT:
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 0 BT_TRACE\n"));
ODM_RT_TRACE(pDM_Odm,COMP_CMD, DBG_LOUD, ("BIT 1 BT_RFPoll\n"));
break;
default:
break;
}
} // DBG_PrintFlagEvent
extern void DBG_DumpMem(const u1Byte DbgComp,
const u1Byte DbgLevel,
pu1Byte pMem,
u2Byte Len)
{
u2Byte i;
for (i=0;i<((Len>>3) + 1);i++)
{
ODM_RT_TRACE(pDM_Odm,DbgComp, DbgLevel, ("%02X %02X %02X %02X %02X %02X %02X %02X\n",
*(pMem+(i*8)), *(pMem+(i*8+1)), *(pMem+(i*8+2)), *(pMem+(i*8+3)),
*(pMem+(i*8+4)), *(pMem+(i*8+5)), *(pMem+(i*8+6)), *(pMem+(i*8+7))));
}
}
#endif

892
backports/drivers/realtek/rtl8812au/hal/OUTSRC/odm_debug.h
View File

@@ -1,892 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_DBG_H__
#define __ODM_DBG_H__
//-----------------------------------------------------------------------------
// Define the debug levels
//
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
// So that, they can help SW engineer to develope or trace states changed
// and also help HW enginner to trace every operation to and from HW,
// e.g IO, Tx, Rx.
//
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
// which help us to debug SW or HW.
//
//-----------------------------------------------------------------------------
//
// Never used in a call to ODM_RT_TRACE()!
//
#define ODM_DBG_OFF 1
//
// Fatal bug.
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
//
#define ODM_DBG_SERIOUS 2
//
// Abnormal, rare, or unexpeted cases.
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
//
#define ODM_DBG_WARNING 3
//
// Normal case with useful information about current SW or HW state.
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
// SW protocol state change, dynamic mechanism state change and so on.
//
#define ODM_DBG_LOUD 4
//
// Normal case with detail execution flow or information.
//
#define ODM_DBG_TRACE 5
//-----------------------------------------------------------------------------
// Define the tracing components
//
//-----------------------------------------------------------------------------
//BB Functions
#define ODM_COMP_DIG BIT0
#define ODM_COMP_RA_MASK BIT1
#define ODM_COMP_DYNAMIC_TXPWR BIT2
#define ODM_COMP_FA_CNT BIT3
#define ODM_COMP_RSSI_MONITOR BIT4
#define ODM_COMP_CCK_PD BIT5
#define ODM_COMP_ANT_DIV BIT6
#define ODM_COMP_PWR_SAVE BIT7
#define ODM_COMP_PWR_TRAIN BIT8
#define ODM_COMP_RATE_ADAPTIVE BIT9
#define ODM_COMP_PATH_DIV BIT10
#define ODM_COMP_PSD BIT11
#define ODM_COMP_DYNAMIC_PRICCA BIT12
#define ODM_COMP_RXHP BIT13
#define ODM_COMP_MP BIT14
#define ODM_COMP_DYNAMIC_ATC BIT15
//MAC Functions
#define ODM_COMP_EDCA_TURBO BIT16
#define ODM_COMP_EARLY_MODE BIT17
//RF Functions
#define ODM_COMP_TX_PWR_TRACK BIT24
#define ODM_COMP_RX_GAIN_TRACK BIT25
#define ODM_COMP_CALIBRATION BIT26
//Common Functions
#define ODM_COMP_COMMON BIT30
#define ODM_COMP_INIT BIT31
/*------------------------Export Marco Definition---------------------------*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define RT_PRINTK DbgPrint
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define DbgPrint printk
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
#define RT_DISP(dbgtype, dbgflag, printstr)
#else
#define DbgPrint panic_printk
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
#endif
#ifndef ASSERT
#define ASSERT(expr)
#endif
#if DBG
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel || level == ODM_DBG_SERIOUS)) \
{ \
RT_PRINTK fmt; \
}
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \
if(!(expr)) { \
DbgPrint( "Assertion failed! %s at ......\n", #expr); \
DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \
RT_PRINTK fmt; \
ASSERT(FALSE); \
}
#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); }
#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); }
#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); }
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
int __i; \
pu1Byte __ptr = (pu1Byte)ptr; \
DbgPrint("[ODM] "); \
DbgPrint(title_str); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#else
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt)
#define ODM_dbg_enter()
#define ODM_dbg_exit()
#define ODM_dbg_trace(str)
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)
#endif
VOID
ODM_InitDebugSetting(
IN PDM_ODM_T pDM_Odm
);
#if 0
#if DBG
#define DbgPrint printk
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \
{ \
char *szTitle = _TitleString; \
pu1Byte pbtHexData = _HexData; \
u4Byte u4bHexDataLen = _HexDataLen; \
u4Byte __i; \
DbgPrint("%s", szTitle); \
for (__i=0;__i<u4bHexDataLen;__i++) \
{ \
if ((__i & 15) == 0) \
{ \
DbgPrint("\n"); \
} \
DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? " " : " ") ); \
} \
DbgPrint("\n"); \
}
// RT_PRINT_XXX macros: implemented for debugging purpose.
// Added by Annie, 2005-11-21.
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
if (((__i + 1) % 16) == 0) DbgPrint("\n"); \
} \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i, __j; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint("\n"); \
for( __i=0; __i<(int)_AddNum; __i++ ) \
{ \
for( __j=0; __j<6; __j++ ) \
DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-"); \
DbgPrint("\n"); \
} \
}
// Added by Annie, 2005-11-22.
#define MAX_STR_LEN 64
#define PRINTABLE(_ch) (_ch>=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
u1Byte buffer[MAX_STR_LEN]; \
int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
PlatformZeroMemory( buffer, MAX_STR_LEN ); \
PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length ); \
for( __i=0; __i<MAX_STR_LEN; __i++ ) \
{ \
if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
} \
buffer[length] = '\0'; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(": %d, <%s>\n", _Len, buffer); \
}
#else // of #if DBG
#define DbgPrint(...)
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
#endif // of #if DBG
#endif
#if 0
/* Define debug print header for every service module.*/
typedef struct tag_ODM_DBGP_Service_Module_Header_Name_Structure
{
const char *pMANS;
const char *pRTOS;
const char *pALM;
const char *pPEM;
const char *pCMPK;
const char *pRAPD;
const char *pTXPB;
const char *pQUMG;
}ODM_DBGP_HEAD_T;
/* Define different debug flag for dedicated service modules in debug flag array. */
// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
typedef enum tag_ODM_DBGP_Flag_Type_Definition
{
ODM_FTX = 0,
ODM_FRX ,
ODM_FPHY ,
ODM_FPWR ,
ODM_FDM ,
ODM_FC2H ,
ODM_FBT ,
ODM_DBGP_TYPE_MAX
}ODM_DBGP_FLAG_E;
// Define TX relative debug bit --> FTX
#define ODM_TX_DESC BIT0
#define ODM_TX_DESC_TID BIT1
#define ODM_TX_PATH BIT2
// Define RX relative debug bit --> FRX
#define ODM_RX_DATA BIT0
#define ODM_RX_PHY_STS BIT1
#define ODM_RX_PHY_SS BIT2
#define ODM_RX_PHY_SQ BIT3
#define ODM_RX_PHY_ASTS BIT4
#define ODM_RX_ERR_LEN BIT5
#define ODM_RX_DEFRAG BIT6
#define ODM_RX_ERR_RATE BIT7
#define ODM_RX_PATH BIT8
#define ODM_RX_BEACON BIT9
// Define PHY-BB/RF/MAC check module bit --> FPHY
#define ODM_PHY_BBR BIT0
#define ODM_PHY_BBW BIT1
#define ODM_PHY_RFR BIT2
#define ODM_PHY_RFW BIT3
#define ODM_PHY_MACR BIT4
#define ODM_PHY_MACW BIT5
#define ODM_PHY_ALLR BIT6
#define ODM_PHY_ALLW BIT7
#define ODM_PHY_TXPWR BIT8
#define ODM_PHY_PWRDIFF BIT9
#define ODM_PHY_SICR BIT10
#define ODM_PHY_SICW BIT11
extern u4Byte ODM_GlobalDebugLevel;
#if DBG
extern u8Byte ODM_GlobalDebugComponents;
#endif
#endif
#if 0
//-----------------------------------------------------------------------------
// Define the debug levels
//
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
// So that, they can help SW engineer to develope or trace states changed
// and also help HW enginner to trace every operation to and from HW,
// e.g IO, Tx, Rx.
//
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
// which help us to debug SW or HW.
//
//-----------------------------------------------------------------------------
//
// Never used in a call to ODM_RT_TRACE(pDM_Odm,)!
//
#define DBG_OFF 0
//
// Deprecated! Don't use it!
// TODO: fix related debug message!
//
//#define DBG_SEC 1
//
// Fatal bug.
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
//
#define DBG_SERIOUS 2
//
// Abnormal, rare, or unexpeted cases.
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
//
#define DBG_WARNING 3
//
// Normal case with useful information about current SW or HW state.
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
// SW protocol state change, dynamic mechanism state change and so on.
//
#define DBG_LOUD 4
//
// Normal case with detail execution flow or information.
//
#define DBG_TRACE 5
//-----------------------------------------------------------------------------
// Define the tracing components
//
//-----------------------------------------------------------------------------
#define COMP_TRACE BIT0 // For function call tracing.
#define COMP_DBG BIT1 // Only for temporary debug message.
#define COMP_INIT BIT2 // during driver initialization / halt / reset.
#define COMP_OID_QUERY BIT3 // Query OID.
#define COMP_OID_SET BIT4 // Set OID.
#define COMP_RECV BIT5 // Reveive part data path.
#define COMP_SEND BIT6 // Send part path.
#define COMP_IO BIT7 // I/O Related. Added by Annie, 2006-03-02.
#define COMP_POWER BIT8 // 802.11 Power Save mode or System/Device Power state related.
#define COMP_MLME BIT9 // 802.11 link related: join/start BSS, leave BSS.
#define COMP_SCAN BIT10 // For site survey.
#define COMP_SYSTEM BIT11 // For general platform function.
#define COMP_SEC BIT12 // For Security.
#define COMP_AP BIT13 // For AP mode related.
#define COMP_TURBO BIT14 // For Turbo Mode related. By Annie, 2005-10-21.
#define COMP_QOS BIT15 // For QoS.
#define COMP_AUTHENTICATOR BIT16 // For AP mode Authenticator. Added by Annie, 2006-01-30.
#define COMP_BEACON BIT17 // For Beacon related, by rcnjko.
#define COMP_ANTENNA BIT18 // For Antenna diversity related, by rcnjko.
#define COMP_RATE BIT19 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling
#define COMP_EVENTS BIT20 // Event handling
#define COMP_FPGA BIT21 // For FPGA verfication
#define COMP_RM BIT22 // For Radio Measurement.
#define COMP_MP BIT23 // For mass production test, by shien chang, 2006.07.13
#define COMP_RXDESC BIT24 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
#define COMP_CKIP BIT25 // For CCX 1 S13: CKIP. Added by Annie, 2006-08-14.
#define COMP_DIG BIT26 // For DIG, 2006.09.25, by rcnjko.
#define COMP_TXAGC BIT27 // For Tx power, 060928, by rcnjko.
#define COMP_HIPWR BIT28 // For High Power Mechanism, 060928, by rcnjko.
#define COMP_HALDM BIT29 // For HW Dynamic Mechanism, 061010, by rcnjko.
#define COMP_RSNA BIT30 // For RSNA IBSS , 061201, by CCW.
#define COMP_INDIC BIT31 // For link indication
#define COMP_LED BIT32 // For LED.
#define COMP_RF BIT33 // For RF.
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
#define COMP_HT BIT34 // For 802.11n HT related information. by Emily 2006-8-11
#define COMP_POWER_TRACKING BIT35 //FOR 8190 TX POWER TRACKING
#define COMP_RX_REORDER BIT36 // 8190 Rx Reorder
#define COMP_AMSDU BIT37 // For A-MSDU Debugging
#define COMP_WPS BIT38 //WPS Debug Message
#define COMP_RATR BIT39
#define COMP_RESET BIT40
// For debug command to print on dbgview!!
#define COMP_CMD BIT41
#define COMP_EFUSE BIT42
#define COMP_MESH_INTERWORKING BIT43
#define COMP_CCX BIT44 //CCX Debug Flag
#define COMP_IOCTL BIT45 // IO Control
#define COMP_GP BIT46 // For generic parser.
#define COMP_TXAGG BIT47
#define COMP_HVL BIT48 // For Ndis 6.2 Context Swirch and Hardware Virtualiztion Layer
#define COMP_TEST BIT49
#define COMP_BB_POWERSAVING BIT50
#define COMP_SWAS BIT51 // For SW Antenna Switch
#define COMP_P2P BIT52
#define COMP_MUX BIT53
#define COMP_FUNC BIT54
#define COMP_TDLS BIT55
#define COMP_OMNIPEEK BIT56
#define COMP_DUALMACSWITCH BIT60 // 2010/12/27 Add for Dual mac mode debug
#define COMP_EASY_CONCURRENT BIT61 // 2010/12/27 Add for easy cncurrent mode debug
#define COMP_PSD BIT63 //2011/3/9 Add for WLAN PSD for BT AFH
#define COMP_DFS BIT62
#define COMP_ALL UINT64_C(0xFFFFFFFFFFFFFFFF) // All components
// For debug print flag to use
/*------------------------------Define structure----------------------------*/
/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/
/* Defnie structure to store different debug flag variable. Every debug flag
is a UINT32 integer and you can assign 32 different events. */
typedef struct tag_DBGP_Debug_Flag_Structure
{
u4Byte Mans; /* Main Scheduler module. */
u4Byte Rtos; /* RTOS module. */
u4Byte Alarm; /* Alarm module. */
u4Byte Pm; /* Performance monitor module. */
}DBGP_FLAG_T;
/* Define debug print header for every service module.*/
typedef struct tag_DBGP_Service_Module_Header_Name_Structure
{
const char *pMANS;
const char *pRTOS;
const char *pALM;
const char *pPEM;
const char *pCMPK;
const char *pRAPD;
const char *pTXPB;
const char *pQUMG;
}DBGP_HEAD_T;
/* Define different debug flag for dedicated service modules in debug flag array. */
// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
typedef enum tag_DBGP_Flag_Type_Definition
{
FQoS = 0,
FTX = 1,
FRX = 2,
FSEC = 3,
FMGNT = 4,
FMLME = 5,
FRESOURCE = 6,
FBEACON = 7,
FISR = 8,
FPHY = 9,
FMP = 10,
FEEPROM = 11,
FPWR = 12,
FDM = 13,
FDBG_CTRL = 14,
FC2H = 15,
FBT = 16,
FINIT = 17,
FIOCTL = 18,
FSHORT_CUT = 19,
DBGP_TYPE_MAX
}DBGP_FLAG_E;
// Define Qos Relative debug flag bit --> FQoS
#define QoS_INIT BIT0
#define QoS_VISTA BIT1
// Define TX relative debug bit --> FTX
#define TX_DESC BIT0
#define TX_DESC_TID BIT1
#define TX_PATH BIT2
// Define RX relative debug bit --> FRX
#define RX_DATA BIT0
#define RX_PHY_STS BIT1
#define RX_PHY_SS BIT2
#define RX_PHY_SQ BIT3
#define RX_PHY_ASTS BIT4
#define RX_ERR_LEN BIT5
#define RX_DEFRAG BIT6
#define RX_ERR_RATE BIT7
#define RX_PATH BIT8
#define RX_BEACON BIT9
// Define Security relative debug bit --> FSEC
// Define MGNT relative debug bit --> FMGNT
// Define MLME relative debug bit --> FMLME
#define MEDIA_STS BIT0
#define LINK_STS BIT1
// Define OS resource check module bit --> FRESOURCE
#define OS_CHK BIT0
// Define beacon content check module bit --> FBEACON
#define BCN_SHOW BIT0
#define BCN_PEER BIT1
// Define ISR/IMR check module bit --> FISR
#define ISR_CHK BIT0
// Define PHY-BB/RF/MAC check module bit --> FPHY
#define PHY_BBR BIT0
#define PHY_BBW BIT1
#define PHY_RFR BIT2
#define PHY_RFW BIT3
#define PHY_MACR BIT4
#define PHY_MACW BIT5
#define PHY_ALLR BIT6
#define PHY_ALLW BIT7
#define PHY_TXPWR BIT8
#define PHY_PWRDIFF BIT9
#define PHY_SICR BIT10
#define PHY_SICW BIT11
// Define MPT driver check module bit --> FMP
#define MP_RX BIT0
#define MP_SWICH_CH BIT1
// Define EEPROM and EFUSE check module bit --> FEEPROM
#define EEPROM_W BIT0
#define EFUSE_PG BIT1
#define EFUSE_READ_ALL BIT2
#define EFUSE_ANALYSIS BIT3
#define EFUSE_PG_DETAIL BIT4
// Define power save check module bit --> FPWR
#define LPS BIT0
#define IPS BIT1
#define PWRSW BIT2
#define PWRHW BIT3
#define PWRHAL BIT4
// Define Dynamic Mechanism check module bit --> FDM
#define WA_IOT BIT0
#define DM_PWDB BIT1
#define DM_Monitor BIT2
#define DM_DIG BIT3
#define DM_EDCA_Turbo BIT4
#define DM_BT30 BIT5
// Define Dbg Control module bit --> FDBG_CTRL
#define DBG_CTRL_TRACE BIT0
#define DBG_CTRL_INBAND_NOISE BIT1
// Define FW C2H Cmd check module bit --> FC2H
#define C2H_Summary BIT0
#define C2H_PacketData BIT1
#define C2H_ContentData BIT2
// Define BT Cmd check module bit --> FBT
#define BT_TRACE BIT0
#define BT_RFPoll BIT1
// Define init check for module bit --> FINIT
#define INIT_EEPROM BIT0
#define INIT_TxPower BIT1
#define INIT_IQK BIT2
#define INIT_RF BIT3
// Define IOCTL Cmd check module bit --> FIOCTL
// section 1 : IRP related
#define IOCTL_IRP BIT0
#define IOCTL_IRP_DETAIL BIT1
#define IOCTL_IRP_STATISTICS BIT2
#define IOCTL_IRP_HANDLE BIT3
// section 2 : HCI command/event
#define IOCTL_BT_HCICMD BIT8
#define IOCTL_BT_HCICMD_DETAIL BIT9
#define IOCTL_BT_HCICMD_EXT BIT10
#define IOCTL_BT_EVENT BIT11
#define IOCTL_BT_EVENT_DETAIL BIT12
#define IOCTL_BT_EVENT_PERIODICAL BIT13
// section 3 : BT tx/rx data and throughput
#define IOCTL_BT_TX_ACLDATA BIT16
#define IOCTL_BT_TX_ACLDATA_DETAIL BIT17
#define IOCTL_BT_RX_ACLDATA BIT18
#define IOCTL_BT_RX_ACLDATA_DETAIL BIT19
#define IOCTL_BT_TP BIT20
// section 4 : BT connection state machine.
#define IOCTL_STATE BIT21
#define IOCTL_BT_LOGO BIT22
// section 5 : BT function trace
#define IOCTL_CALLBACK_FUN BIT24
#define IOCTL_PARSE_BT_PKT BIT25
#define IOCTL_BT_TX_PKT BIT26
#define IOCTL_BT_FLAG_MON BIT27
//
// Define init check for module bit --> FSHORT_CUT
// 2011/07/20 MH Add for short but definition.
//
#define SHCUT_TX BIT0
#define SHCUT_RX BIT1
/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define RT_PRINTK(fmt, args...) printk( "%s(): " fmt, __FUNCTION__, ## args);
#if DBG
#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt) \
if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define RT_TRACE_F(comp, level, fmt) \
if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define RT_ASSERT(expr,fmt) \
if(!(expr)) { \
printk( "Assertion failed! %s at ......\n", #expr); \
printk( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \
}
#define dbg_enter() { printk("==> %s\n", __FUNCTION__); }
#define dbg_exit() { printk("<== %s\n", __FUNCTION__); }
#define dbg_trace(str) { printk("%s:%s\n", __FUNCTION__, str); }
#else
#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt)
#define RT_TRACE_F(comp, level, fmt)
#define RT_ASSERT(expr, fmt)
#define dbg_enter()
#define dbg_exit()
#define dbg_trace(str)
#endif
#if DBG
#define DbgPrint printk
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \
{ \
char *szTitle = _TitleString; \
pu1Byte pbtHexData = _HexData; \
u4Byte u4bHexDataLen = _HexDataLen; \
u4Byte __i; \
DbgPrint("%s", szTitle); \
for (__i=0;__i<u4bHexDataLen;__i++) \
{ \
if ((__i & 15) == 0) \
{ \
DbgPrint("\n"); \
} \
DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? " " : " ") ); \
} \
DbgPrint("\n"); \
}
// RT_PRINT_XXX macros: implemented for debugging purpose.
// Added by Annie, 2005-11-21.
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
if (((__i + 1) % 16) == 0) DbgPrint("\n"); \
} \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i, __j; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint("\n"); \
for( __i=0; __i<(int)_AddNum; __i++ ) \
{ \
for( __j=0; __j<6; __j++ ) \
DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-"); \
DbgPrint("\n"); \
} \
}
// Added by Annie, 2005-11-22.
#define MAX_STR_LEN 64
#define PRINTABLE(_ch) (_ch>=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
u1Byte buffer[MAX_STR_LEN]; \
int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
PlatformZeroMemory( buffer, MAX_STR_LEN ); \
PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length ); \
for( __i=0; __i<MAX_STR_LEN; __i++ ) \
{ \
if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
} \
buffer[length] = '\0'; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(": %d, <%s>\n", _Len, buffer); \
}
#else // of #if DBG
#define DbgPrint(...)
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
#endif // of #if DBG
#endif // #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define DEBUG_PRINT 1
// Please add new OS's print API by yourself
//#if (RT_PLATFORM==PLATFORM_WINDOWS)
#if (DEBUG_PRINT == 1) && DBG
#define RT_DISP(dbgtype, dbgflag, printstr)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
DbgPrint printstr;\
}\
}
#define RT_DISP_ADDR(dbgtype, dbgflag, printstr, _Ptr)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint printstr; \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}\
}
#define RT_DISP_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" ");\
if (((__i + 1) % 16) == 0) DbgPrint("\n");\
} \
DbgPrint("\n"); \
}\
}
#define FunctionIn(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("==========> %s\n", __FUNCTION__))
#define FunctionOut(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("<========== %s\n", __FUNCTION__))
#else
#define RT_DISP(dbgtype, dbgflag, printstr)
#define RT_DISP_ADDR(dbgtype, dbgflag, printstr, _Ptr)
#define RT_DISP_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)
#define FunctionIn(_comp)
#define FunctionOut(_comp)
#endif
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export global variable----------------------------*/
extern u4Byte DBGP_Type[DBGP_TYPE_MAX];
extern DBGP_HEAD_T DBGP_Head;
/*------------------------Export global variable----------------------------*/
/*--------------------------Exported Function prototype---------------------*/
extern void DBGP_Flag_Init(void);
extern void DBG_PrintAllFlag(void);
extern void DBG_PrintAllComp(void);
extern void DBG_PrintFlagEvent(u1Byte DbgFlag);
extern void DBG_DumpMem(const u1Byte DbgComp,
const u1Byte DbgLevel,
pu1Byte pMem,
u2Byte Len);
/*--------------------------Exported Function prototype---------------------*/
extern u4Byte GlobalDebugLevel;
extern u8Byte GlobalDebugComponents;
#endif
#endif // __ODM_DBG_H__

723
backports/drivers/realtek/rtl8812au/hal/OUTSRC/odm_interface.c
View File

@@ -1,723 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "odm_precomp.h"
//
// ODM IO Relative API.
//
u1Byte
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
return RTL_R8(RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
return rtw_read8(Adapter,RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
return PlatformEFIORead1Byte(Adapter, RegAddr);
#endif
}
u2Byte
ODM_Read2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
return RTL_R16(RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
return rtw_read16(Adapter,RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
return PlatformEFIORead2Byte(Adapter, RegAddr);
#endif
}
u4Byte
ODM_Read4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
return RTL_R32(RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
return rtw_read32(Adapter,RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
return PlatformEFIORead4Byte(Adapter, RegAddr);
#endif
}
VOID
ODM_Write1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u1Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
RTL_W8(RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
rtw_write8(Adapter,RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformEFIOWrite1Byte(Adapter, RegAddr, Data);
#endif
}
VOID
ODM_Write2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u2Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
RTL_W16(RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
rtw_write16(Adapter,RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformEFIOWrite2Byte(Adapter, RegAddr, Data);
#endif
}
VOID
ODM_Write4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
RTL_W32(RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
rtw_write32(Adapter,RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformEFIOWrite4Byte(Adapter, RegAddr, Data);
#endif
}
VOID
ODM_SetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
#endif
}
u4Byte
ODM_GetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return PHY_QueryMacReg(pDM_Odm->priv, RegAddr, BitMask);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
return PHY_QueryMacReg(Adapter, RegAddr, BitMask);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
return PHY_QueryBBReg(pDM_Odm->Adapter, RegAddr, BitMask);
#endif
}
VOID
ODM_SetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);
#endif
}
u4Byte
ODM_GetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
return PHY_QueryBBReg(Adapter, RegAddr, BitMask);
#endif
}
VOID
ODM_SetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
PHY_SetRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, Data);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data);
#endif
}
u4Byte
ODM_GetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return PHY_QueryRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, 1);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask);
#endif
}
//
// ODM Memory relative API.
//
VOID
ODM_AllocateMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID *pPtr,
IN u4Byte length
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
*pPtr = kmalloc(length, GFP_ATOMIC);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
*pPtr = rtw_zvmalloc(length);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformAllocateMemory(Adapter, pPtr, length);
#endif
}
// length could be ignored, used to detect memory leakage.
VOID
ODM_FreeMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID pPtr,
IN u4Byte length
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
kfree(pPtr);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
rtw_vmfree(pPtr, length);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
//PADAPTER Adapter = pDM_Odm->Adapter;
PlatformFreeMemory(pPtr, length);
#endif
}
VOID
ODM_MoveMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID pDest,
IN PVOID pSrc,
IN u4Byte Length
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
_rtw_memcpy(pDest, pSrc, Length);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformMoveMemory(pDest, pSrc, Length);
#endif
}
s4Byte ODM_CompareMemory(
IN PDM_ODM_T pDM_Odm,
IN PVOID pBuf1,
IN PVOID pBuf2,
IN u4Byte length
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return memcmp(pBuf1,pBuf2,length);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
return _rtw_memcmp(pBuf1,pBuf2,length);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
return PlatformCompareMemory(pBuf1,pBuf2,length);
#endif
}
//
// ODM MISC relative API.
//
VOID
ODM_AcquireSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformAcquireSpinLock(Adapter, type);
#endif
}
VOID
ODM_ReleaseSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE )
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformReleaseSpinLock(Adapter, type);
#endif
}
//
// Work item relative API. FOr MP driver only~!
//
VOID
ODM_InitializeWorkItem(
IN PDM_ODM_T pDM_Odm,
IN PRT_WORK_ITEM pRtWorkItem,
IN RT_WORKITEM_CALL_BACK RtWorkItemCallback,
IN PVOID pContext,
IN const char* szID
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformInitializeWorkItem(Adapter, pRtWorkItem, RtWorkItemCallback, pContext, szID);
#endif
}
VOID
ODM_StartWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformStartWorkItem(pRtWorkItem);
#endif
}
VOID
ODM_StopWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformStopWorkItem(pRtWorkItem);
#endif
}
VOID
ODM_FreeWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformFreeWorkItem(pRtWorkItem);
#endif
}
VOID
ODM_ScheduleWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformScheduleWorkItem(pRtWorkItem);
#endif
}
VOID
ODM_IsWorkItemScheduled(
IN PRT_WORK_ITEM pRtWorkItem
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformIsWorkItemScheduled(pRtWorkItem);
#endif
}
//
// ODM Timer relative API.
//
VOID
ODM_StallExecution(
IN u4Byte usDelay
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
rtw_udelay_os(usDelay);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformStallExecution(usDelay);
#endif
}
VOID
ODM_delay_ms(IN u4Byte ms)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
delay_ms(ms);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
rtw_mdelay_os(ms);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
delay_ms(ms);
#endif
}
VOID
ODM_delay_us(IN u4Byte us)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
delay_us(us);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
rtw_udelay_os(us);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PlatformStallExecution(us);
#endif
}
VOID
ODM_sleep_ms(IN u4Byte ms)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
rtw_msleep_os(ms);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
#endif
}
VOID
ODM_sleep_us(IN u4Byte us)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
rtw_usleep_os(us);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
#endif
}
VOID
ODM_SetTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN u4Byte msDelay
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
mod_timer(pTimer, jiffies + (msDelay+9)/10);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
_set_timer(pTimer,msDelay ); //ms
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformSetTimer(Adapter, pTimer, msDelay);
#endif
}
VOID
ODM_InitializeTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN RT_TIMER_CALL_BACK CallBackFunc,
IN PVOID pContext,
IN const char* szID
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
pTimer->function = CallBackFunc;
pTimer->data = (unsigned long)pDM_Odm;
init_timer(pTimer);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
_init_timer(pTimer,Adapter->pnetdev,CallBackFunc,pDM_Odm);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformInitializeTimer(Adapter, pTimer, CallBackFunc,pContext,szID);
#endif
}
VOID
ODM_CancelTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
del_timer_sync(pTimer);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
_cancel_timer_ex(pTimer);
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformCancelTimer(Adapter, pTimer);
#endif
}
VOID
ODM_ReleaseTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
// <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm.
// Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail.
if (pTimer == 0)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>ODM_ReleaseTimer(), The timer is NULL! Please check it!\n"));
return;
}
PlatformReleaseTimer(Adapter, pTimer);
#endif
}
//
// ODM FW relative API.
//
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
VOID
ODM_FillH2CCmd(
IN PADAPTER Adapter,
IN u1Byte ElementID,
IN u4Byte CmdLen,
IN pu1Byte pCmdBuffer
)
{
if(IS_HARDWARE_TYPE_JAGUAR(Adapter))
{
switch(ElementID)
{
case ODM_H2C_RSSI_REPORT:
FillH2CCmd8812(Adapter, H2C_8812_RSSI_REPORT, CmdLen, pCmdBuffer);
break;
default:
break;
}
}
else if(IS_HARDWARE_TYPE_8192E(Adapter))
{
switch(ElementID)
{
case ODM_H2C_RSSI_REPORT:
FillH2CCmd8812(Adapter, H2C_8812_RSSI_REPORT, CmdLen, pCmdBuffer);
break;
default:
break;
}
}
else if(IS_HARDWARE_TYPE_8723B(Adapter))
{
//
// <Roger_TODO> We should take RTL8723B into consideration, 2012.10.08
//
switch(ElementID)
{
case ODM_H2C_RSSI_REPORT:
FillH2CCmd8723B(Adapter, H2C_8723B_RSSI_REPORT, CmdLen, pCmdBuffer);
break;
default:
break;
}
}
else if(IS_HARDWARE_TYPE_8188E(Adapter))
{
switch(ElementID)
{
case ODM_H2C_PSD_RESULT:
FillH2CCmd88E(Adapter, H2C_88E_PSD_RESULT, CmdLen, pCmdBuffer);
break;
case ODM_H2C_RSSI_REPORT:
if(IS_VENDOR_8188E_I_CUT_SERIES(Adapter))
FillH2CCmd88E(Adapter, H2C_88E_RSSI_REPORT, CmdLen, pCmdBuffer);
break;
default:
break;
}
}
else
{
switch(ElementID)
{
case ODM_H2C_RSSI_REPORT:
FillH2CCmd92C(Adapter, H2C_RSSI_REPORT, CmdLen, pCmdBuffer);
break;
case ODM_H2C_PSD_RESULT:
FillH2CCmd92C(Adapter, H2C_92C_PSD_RESULT, CmdLen, pCmdBuffer);
break;
default:
break;
}
}
}
#else
u4Byte
ODM_FillH2CCmd(
IN pu1Byte pH2CBuffer,
IN u4Byte H2CBufferLen,
IN u4Byte CmdNum,
IN pu4Byte pElementID,
IN pu4Byte pCmdLen,
IN pu1Byte* pCmbBuffer,
IN pu1Byte CmdStartSeq
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN)
//FillH2CCmd(pH2CBuffer, H2CBufferLen, CmdNum, pElementID, pCmdLen, pCmbBuffer, CmdStartSeq);
return FALSE;
#endif
return TRUE;
}
#endif

383
backports/drivers/realtek/rtl8812au/hal/OUTSRC/odm_interface.h
View File

@@ -1,383 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_INTERFACE_H__
#define __ODM_INTERFACE_H__
//
// =========== Constant/Structure/Enum/... Define
//
//
// =========== Macro Define
//
#define _reg_all(_name) ODM_##_name
#define _reg_ic(_name, _ic) ODM_##_name##_ic
#define _bit_all(_name) BIT_##_name
#define _bit_ic(_name, _ic) BIT_##_name##_ic
// _cat: implemented by Token-Pasting Operator.
#if 0
#define _cat(_name, _ic_type, _func) \
( \
_func##_all(_name) \
)
#endif
/*===================================
#define ODM_REG_DIG_11N 0xC50
#define ODM_REG_DIG_11AC 0xDDD
ODM_REG(DIG,_pDM_Odm)
=====================================*/
#define _reg_11N(_name) ODM_REG_##_name##_11N
#define _reg_11AC(_name) ODM_REG_##_name##_11AC
#define _bit_11N(_name) ODM_BIT_##_name##_11N
#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
#if 1 //TODO: enable it if we need to support run-time to differentiate between 92C_SERIES and JAGUAR_SERIES.
#define _cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \
_func##_11AC(_name) \
)
#endif
#if 0 // only sample code
#define _cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_RTL8192C)? _func##_ic(_name, _8192C): \
((_ic_type) & ODM_RTL8192D)? _func##_ic(_name, _8192D): \
((_ic_type) & ODM_RTL8192S)? _func##_ic(_name, _8192S): \
((_ic_type) & ODM_RTL8723A)? _func##_ic(_name, _8723A): \
((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \
_func##_ic(_name, _8195) \
)
#endif
// _name: name of register or bit.
// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)"
// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType.
#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg)
#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
typedef enum _ODM_H2C_CMD
{
ODM_H2C_RSSI_REPORT = 0,
ODM_H2C_PSD_RESULT=1,
ODM_H2C_PathDiv = 2,
ODM_MAX_H2CCMD
}ODM_H2C_CMD;
//
// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem.
// Suggest HW team to use thread instead of workitem. Windows also support the feature.
//
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
typedef void *PRT_WORK_ITEM ;
typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE;
typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext);
#if 0
typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE;
typedef struct _RT_WORK_ITEM
{
RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object.
PVOID Adapter; // Pointer to Adapter object.
PVOID pContext; // Parameter to passed to CallBackFunc().
RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem.
u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled.
PVOID pPlatformExt; // Pointer to platform-dependent extension.
BOOLEAN bFree;
char szID[36]; // An identity string of this workitem.
}RT_WORK_ITEM, *PRT_WORK_ITEM;
#endif
#endif
//
// =========== Extern Variable ??? It should be forbidden.
//
//
// =========== EXtern Function Prototype
//
u1Byte
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
u2Byte
ODM_Read2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
u4Byte
ODM_Read4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
VOID
ODM_Write1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u1Byte Data
);
VOID
ODM_Write2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u2Byte Data
);
VOID
ODM_Write4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte Data
);
VOID
ODM_SetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
VOID
ODM_SetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
VOID
ODM_SetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
//
// Memory Relative Function.
//
VOID
ODM_AllocateMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID *pPtr,
IN u4Byte length
);
VOID
ODM_FreeMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID pPtr,
IN u4Byte length
);
VOID
ODM_MoveMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID pDest,
IN PVOID pSrc,
IN u4Byte Length
);
s4Byte ODM_CompareMemory(
IN PDM_ODM_T pDM_Odm,
IN PVOID pBuf1,
IN PVOID pBuf2,
IN u4Byte length
);
//
// ODM MISC-spin lock relative API.
//
VOID
ODM_AcquireSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
);
VOID
ODM_ReleaseSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
);
//
// ODM MISC-workitem relative API.
//
VOID
ODM_InitializeWorkItem(
IN PDM_ODM_T pDM_Odm,
IN PRT_WORK_ITEM pRtWorkItem,
IN RT_WORKITEM_CALL_BACK RtWorkItemCallback,
IN PVOID pContext,
IN const char* szID
);
VOID
ODM_StartWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_StopWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_FreeWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_ScheduleWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_IsWorkItemScheduled(
IN PRT_WORK_ITEM pRtWorkItem
);
//
// ODM Timer relative API.
//
VOID
ODM_StallExecution(
IN u4Byte usDelay
);
VOID
ODM_delay_ms(IN u4Byte ms);
VOID
ODM_delay_us(IN u4Byte us);
VOID
ODM_sleep_ms(IN u4Byte ms);
VOID
ODM_sleep_us(IN u4Byte us);
VOID
ODM_SetTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN u4Byte msDelay
);
VOID
ODM_InitializeTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN RT_TIMER_CALL_BACK CallBackFunc,
IN PVOID pContext,
IN const char* szID
);
VOID
ODM_CancelTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
);
VOID
ODM_ReleaseTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
);
//
// ODM FW relative API.
//
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
VOID
ODM_FillH2CCmd(
IN PADAPTER Adapter,
IN u1Byte ElementID,
IN u4Byte CmdLen,
IN pu1Byte pCmdBuffer
);
#else
u4Byte
ODM_FillH2CCmd(
IN pu1Byte pH2CBuffer,
IN u4Byte H2CBufferLen,
IN u4Byte CmdNum,
IN pu4Byte pElementID,
IN pu4Byte pCmdLen,
IN pu1Byte* pCmbBuffer,
IN pu1Byte CmdStartSeq
);
#endif
#endif // __ODM_INTERFACE_H__

307
backports/drivers/realtek/rtl8812au/hal/OUTSRC/odm_precomp.h
View File

@@ -1,307 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_PRECOMP_H__
#define __ODM_PRECOMP_H__
#include "odm_types.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting.
#else
#define TEST_FALG___ 1
#endif
//2 Config Flags and Structs - defined by each ODM Type
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "../8192cd_cfg.h"
#include "../odm_inc.h"
#include "../8192cd.h"
#include "../8192cd_util.h"
#ifdef _BIG_ENDIAN_
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#else
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
#ifdef AP_BUILD_WORKAROUND
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
// Flags
#include "../8192cd_cfg.h" // OUTSRC needs ADSL config flags.
#include "../odm_inc.h" // OUTSRC needs some extra flags.
// Data Structure
#include "../common_types.h" // OUTSRC and rtl8192cd both needs basic type such as UINT8 and BIT0.
#include "../8192cd.h" // OUTSRC needs basic ADSL struct definition.
#include "../8192cd_util.h" // OUTSRC needs basic I/O function.
#ifdef _BIG_ENDIAN_
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#else
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
#ifdef ADSL_AP_BUILD_WORKAROUND
// NESTED_INC: Functions defined outside should not be included!! Marked by Annie, 2011-10-14.
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE)
//#include <drv_conf.h>
//#include <basic_types.h>
//#include <osdep_service.h>
//#include <drv_types.h>
//#include <rtw_byteorder.h>
//#include <hal_intf.h>
#define BEAMFORMING_SUPPORT 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "Mp_Precomp.h"
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
//2 Hardware Parameter Files
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#if (RTL8192C_SUPPORT==1)
#include "rtl8192c/Hal8192CEFWImg_AP.h"
#include "rtl8192c/Hal8192CEPHYImg_AP.h"
#include "rtl8192c/Hal8192CEMACImg_AP.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
#include "rtl8192c/Hal8192CEFWImg_ADSL.h"
#include "rtl8192c/Hal8192CEPHYImg_ADSL.h"
#include "rtl8192c/Hal8192CEMACImg_ADSL.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#if(RTL8192CE_SUPPORT ==1)
#include "rtl8192c/Hal8192CEFWImg_CE.h"
#include "rtl8192c/Hal8192CEPHYImg_CE.h"
#include "rtl8192c/Hal8192CEMACImg_CE.h"
#endif
#if(RTL8192CU_SUPPORT ==1)
#include "rtl8192c/Hal8192CUFWImg_CE.h"
#include "rtl8192c/Hal8192CUPHYImg_CE.h"
#include "rtl8192c/Hal8192CUMACImg_CE.h"
#endif
#if(RTL8192DE_SUPPORT ==1)
#include "rtl8192d/Hal8192DEFWImg_CE.h"
#include "rtl8192d/Hal8192DEPHYImg_CE.h"
#include "rtl8192d/Hal8192DEMACImg_CE.h"
#endif
#if(RTL8192DU_SUPPORT ==1)
#include "rtl8192d/Hal8192DUFWImg_CE.h"
#include "rtl8192d/Hal8192DUPHYImg_CE.h"
#include "rtl8192d/Hal8192DUMACImg_CE.h"
#endif
#if(RTL8723AS_SUPPORT==1)
#include "rtl8723a/Hal8723SHWImg_CE.h"
#endif
#if(RTL8723AU_SUPPORT==1)
#include "rtl8723a/Hal8723UHWImg_CE.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#endif
//2 OutSrc Header Files
#include "odm.h"
#include "odm_HWConfig.h"
#include "odm_debug.h"
#include "odm_RegDefine11AC.h"
#include "odm_RegDefine11N.h"
#include "odm_AntDiv.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#if (RTL8192C_SUPPORT==1)
#include "rtl8192c/HalDMOutSrc8192C_AP.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
#include "rtl8192c/HalDMOutSrc8192C_ADSL.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
//#include "hal_com.h"
#include "HalPhyRf.h"
#if (RTL8192C_SUPPORT==1)
#ifdef CONFIG_INTEL_PROXIM
#include "../proxim/intel_proxim.h"
#endif
#include "rtl8192c/HalDMOutSrc8192C_CE.h"
#include <rtl8192c_hal.h>
#endif
#if (RTL8192D_SUPPORT==1)
#include "rtl8192d/HalDMOutSrc8192D_CE.h"
#include "rtl8192d_hal.h"
#endif
#if (RTL8723A_SUPPORT==1)
#include "rtl8192c/HalDMOutSrc8192C_CE.h" //for IQK,LCK,Power-tracking
#include "rtl8723a_hal.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking
#include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training
#include "rtl8188e_hal.h"
#endif
#if (RTL8192E_SUPPORT==1)
#include "rtl8192e/HalPhyRf_8192e.h"//for IQK,LCK,Power-tracking
#include "rtl8192e_hal.h"
#endif
#if (RTL8812A_SUPPORT==1)
#include "rtl8812a/HalPhyRf_8812A.h"//for IQK,LCK,Power-tracking
#include "rtl8812a_hal.h"
#endif
#if (RTL8821A_SUPPORT==1)
#include "rtl8821a/HalPhyRf_8821A.h"//for IQK,LCK,Power-tracking
#include "rtl8812a/HalPhyRf_8812A.h"//for IQK,LCK,Power-tracking
#include "rtl8812a_hal.h"
#endif
#if (RTL8723B_SUPPORT==1)
#include "rtl8723b/HalPhyRf_8723B.h"//for IQK,LCK,Power-tracking
#include "rtl8723b_hal.h"
#endif
#endif
#include "odm_interface.h"
#include "odm_reg.h"
#if (RTL8192C_SUPPORT==1)
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "rtl8192c/Hal8192CHWImg_MAC.h"
#include "rtl8192c/Hal8192CHWImg_RF.h"
#include "rtl8192c/Hal8192CHWImg_BB.h"
#include "rtl8192c/Hal8192CHWImg_FW.h"
#endif
#include "rtl8192c/odm_RTL8192C.h"
#endif
#if (RTL8192D_SUPPORT==1)
#include "rtl8192d/odm_RTL8192D.h"
#endif
#if (RTL8723A_SUPPORT==1)
#include "rtl8723a/HalHWImg8723A_MAC.h"
#include "rtl8723a/HalHWImg8723A_RF.h"
#include "rtl8723a/HalHWImg8723A_BB.h"
#include "rtl8723a/HalHWImg8723A_FW.h"
#include "rtl8723a/odm_RegConfig8723A.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/HalHWImg8188E_MAC.h"
#include "rtl8188e/HalHWImg8188E_RF.h"
#include "rtl8188e/HalHWImg8188E_BB.h"
#include "rtl8188e/HalHWImg8188E_FW.h"
#include "rtl8188e/Hal8188EReg.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#include "rtl8188e/HalPhyRf_8188e.h"
#endif
#if (TESTCHIP_SUPPORT == 1)
#include "rtl8188e/HalHWImg8188E_TestChip_MAC.h"
#include "rtl8188e/HalHWImg8188E_TestChip_RF.h"
#include "rtl8188e/HalHWImg8188E_TestChip_BB.h"
#endif
#include "rtl8188e/odm_RegConfig8188E.h"
#include "rtl8188e/odm_RTL8188E.h"
#endif
#if (RTL8192E_SUPPORT==1)
#include "rtl8192e/HalHWImg8192E_MAC.h"
#include "rtl8192e/HalHWImg8192E_RF.h"
#include "rtl8192e/HalHWImg8192E_BB.h"
#include "rtl8192e/HalHWImg8192E_FW.h"
#include "rtl8192e/Hal8192EReg.h"
#include "rtl8192e/odm_RegConfig8192E.h"
#include "rtl8192e/odm_RTL8192E.h"
#endif
#if (RTL8723B_SUPPORT==1)
#include "rtl8723b/HalHWImg8723B_MAC.h"
#include "rtl8723b/HalHWImg8723B_RF.h"
#include "rtl8723b/HalHWImg8723B_BB.h"
#include "rtl8723b/HalHWImg8723B_FW.h"
#include "rtl8723b/HalHWImg8723B_MP.h"
#include "rtl8723b/Hal8723BReg.h"
#include "rtl8723b/odm_RTL8723B.h"
#include "rtl8723b/odm_RegConfig8723B.h"
#endif
#if (RTL8812A_SUPPORT==1)
#include "rtl8812a/HalHWImg8812A_MAC.h"
#include "rtl8812a/HalHWImg8812A_RF.h"
#include "rtl8812a/HalHWImg8812A_BB.h"
#include "rtl8812a/HalHWImg8812A_FW.h"
#include "rtl8812a/odm_RegConfig8812A.h"
#include "rtl8812a/odm_RTL8812A.h"
#if (TESTCHIP_SUPPORT == 1)
#include "rtl8812a/HalHWImg8812A_TestChip_MAC.h"
#include "rtl8812a/HalHWImg8812A_TestChip_RF.h"
#include "rtl8812a/HalHWImg8812A_TestChip_BB.h"
#endif
#endif
#if (RTL8821A_SUPPORT==1)
#include "rtl8821a/HalHWImg8821A_MAC.h"
#include "rtl8821a/HalHWImg8821A_RF.h"
#include "rtl8821a/HalHWImg8821A_BB.h"
#include "rtl8821a/HalHWImg8821A_FW.h"
#include "rtl8821a/odm_RegConfig8821A.h"
#include "rtl8821a/odm_RTL8821A.h"
#if (TESTCHIP_SUPPORT == 1)
#include "rtl8821a/HalHWImg8821A_TestChip_MAC.h"
#include "rtl8821a/HalHWImg8821A_TestChip_RF.h"
#include "rtl8821a/HalHWImg8821A_TestChip_BB.h"
#include "rtl8821a/HalHWImg8821A_TestChip_FW.h"
#endif
#endif
#endif // __ODM_PRECOMP_H__

122
backports/drivers/realtek/rtl8812au/hal/OUTSRC/odm_reg.h
View File

@@ -1,122 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// File Name: odm_reg.h
//
// Description:
//
// This file is for general register definition.
//
//
//============================================================
#ifndef __HAL_ODM_REG_H__
#define __HAL_ODM_REG_H__
//
// Register Definition
//
//MAC REG
#define ODM_BB_RESET 0x002
#define ODM_DUMMY 0x4fe
#define RF_T_METER_OLD 0x24
#define RF_T_METER_NEW 0x42
#define ODM_EDCA_VO_PARAM 0x500
#define ODM_EDCA_VI_PARAM 0x504
#define ODM_EDCA_BE_PARAM 0x508
#define ODM_EDCA_BK_PARAM 0x50C
#define ODM_TXPAUSE 0x522
//BB REG
#define ODM_FPGA_PHY0_PAGE8 0x800
#define ODM_PSD_SETTING 0x808
#define ODM_AFE_SETTING 0x818
#define ODM_TXAGC_B_24_54 0x834
#define ODM_TXAGC_B_MCS32_5 0x838
#define ODM_TXAGC_B_MCS0_MCS3 0x83c
#define ODM_TXAGC_B_MCS4_MCS7 0x848
#define ODM_TXAGC_B_MCS8_MCS11 0x84c
#define ODM_ANALOG_REGISTER 0x85c
#define ODM_RF_INTERFACE_OUTPUT 0x860
#define ODM_TXAGC_B_MCS12_MCS15 0x868
#define ODM_TXAGC_B_11_A_2_11 0x86c
#define ODM_AD_DA_LSB_MASK 0x874
#define ODM_ENABLE_3_WIRE 0x88c
#define ODM_PSD_REPORT 0x8b4
#define ODM_R_ANT_SELECT 0x90c
#define ODM_CCK_ANT_SELECT 0xa07
#define ODM_CCK_PD_THRESH 0xa0a
#define ODM_CCK_RF_REG1 0xa11
#define ODM_CCK_MATCH_FILTER 0xa20
#define ODM_CCK_RAKE_MAC 0xa2e
#define ODM_CCK_CNT_RESET 0xa2d
#define ODM_CCK_TX_DIVERSITY 0xa2f
#define ODM_CCK_FA_CNT_MSB 0xa5b
#define ODM_CCK_FA_CNT_LSB 0xa5c
#define ODM_CCK_NEW_FUNCTION 0xa75
#define ODM_OFDM_PHY0_PAGE_C 0xc00
#define ODM_OFDM_RX_ANT 0xc04
#define ODM_R_A_RXIQI 0xc14
#define ODM_R_A_AGC_CORE1 0xc50
#define ODM_R_A_AGC_CORE2 0xc54
#define ODM_R_B_AGC_CORE1 0xc58
#define ODM_R_AGC_PAR 0xc70
#define ODM_R_HTSTF_AGC_PAR 0xc7c
#define ODM_TX_PWR_TRAINING_A 0xc90
#define ODM_TX_PWR_TRAINING_B 0xc98
#define ODM_OFDM_FA_CNT1 0xcf0
#define ODM_OFDM_PHY0_PAGE_D 0xd00
#define ODM_OFDM_FA_CNT2 0xda0
#define ODM_OFDM_FA_CNT3 0xda4
#define ODM_OFDM_FA_CNT4 0xda8
#define ODM_TXAGC_A_6_18 0xe00
#define ODM_TXAGC_A_24_54 0xe04
#define ODM_TXAGC_A_1_MCS32 0xe08
#define ODM_TXAGC_A_MCS0_MCS3 0xe10
#define ODM_TXAGC_A_MCS4_MCS7 0xe14
#define ODM_TXAGC_A_MCS8_MCS11 0xe18
#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
//RF REG
#define ODM_GAIN_SETTING 0x00
#define ODM_CHANNEL 0x18
//Ant Detect Reg
#define ODM_DPDT 0x300
//PSD Init
#define ODM_PSDREG 0x808
//92D Path Div
#define PATHDIV_REG 0xB30
#define PATHDIV_TRI 0xBA0
//
// Bitmap Definition
//
#define BIT_FA_RESET BIT0
#endif

265
backports/drivers/realtek/rtl8812au/hal/OUTSRC/odm_types.h
View File

@@ -1,265 +0,0 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_TYPES_H__
#define __ODM_TYPES_H__
//
// Define Different SW team support
//
#define ODM_AP 0x01 //BIT0
#define ODM_ADSL 0x02 //BIT1
#define ODM_CE 0x04 //BIT2
#define ODM_WIN 0x08 //BIT3
#define DM_ODM_SUPPORT_TYPE ODM_CE
// Deifne HW endian support
#define ODM_ENDIAN_BIG 0
#define ODM_ENDIAN_LITTLE 1
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define RT_PCI_INTERFACE 1
#define RT_USB_INTERFACE 2
#define RT_SDIO_INTERFACE 3
#endif
typedef enum _HAL_STATUS{
HAL_STATUS_SUCCESS,
HAL_STATUS_FAILURE,
/*RT_STATUS_PENDING,
RT_STATUS_RESOURCE,
RT_STATUS_INVALID_CONTEXT,
RT_STATUS_INVALID_PARAMETER,
RT_STATUS_NOT_SUPPORT,
RT_STATUS_OS_API_FAILED,*/
}HAL_STATUS,*PHAL_STATUS;
#if( (DM_ODM_SUPPORT_TYPE == ODM_AP) ||(DM_ODM_SUPPORT_TYPE == ODM_ADSL) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
#define VISTA_USB_RX_REVISE 0
//
// Declare for ODM spin lock defintion temporarily fro compile pass.
//
typedef enum _RT_SPINLOCK_TYPE{
RT_TX_SPINLOCK = 1,
RT_RX_SPINLOCK = 2,
RT_RM_SPINLOCK = 3,
RT_CAM_SPINLOCK = 4,
RT_SCAN_SPINLOCK = 5,
RT_LOG_SPINLOCK = 7,
RT_BW_SPINLOCK = 8,
RT_CHNLOP_SPINLOCK = 9,
RT_RF_OPERATE_SPINLOCK = 10,
RT_INITIAL_SPINLOCK = 11,
RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30.
#if VISTA_USB_RX_REVISE
RT_USBRX_CONTEXT_SPINLOCK = 13,
RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR
#endif
//Shall we define Ndis 6.2 SpinLock Here ?
RT_PORT_SPINLOCK=16,
RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09.
RT_BTData_SPINLOCK=25,
RT_WAPI_OPTION_SPINLOCK=26,
RT_WAPI_RX_SPINLOCK=27,
// add for 92D CCK control issue
RT_CCK_PAGEA_SPINLOCK = 28,
RT_BUFFER_SPINLOCK = 29,
RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
RT_GEN_TEMP_BUF_SPINLOCK = 31,
RT_AWB_SPINLOCK = 32,
RT_FW_PS_SPINLOCK = 33,
RT_HW_TIMER_SPIN_LOCK = 34,
RT_MPT_WI_SPINLOCK = 35,
RT_P2P_SPIN_LOCK = 36, // Protect P2P context
RT_DBG_SPIN_LOCK = 37,
RT_IQK_SPINLOCK = 38,
RT_PENDED_OID_SPINLOCK = 39,
RT_CHNLLIST_SPINLOCK = 40,
RT_INDIC_SPINLOCK = 41, //protect indication
}RT_SPINLOCK_TYPE;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define STA_INFO_T RT_WLAN_STA
#define PSTA_INFO_T PRT_WLAN_STA
// typedef unsigned long u4Byte,*pu4Byte;
#define CONFIG_HW_ANTENNA_DIVERSITY
#define CONFIG_SW_ANTENNA_DIVERSITY
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
// To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
#define ADSL_AP_BUILD_WORKAROUND
#define AP_BUILD_WORKAROUND
//
#ifdef CONFIG_ANT_SWITCH
#define CONFIG_HW_ANTENNA_DIVERSITY
#if ( defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_NOT_SUPPORT_ANTDIV
#elif( !defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_2G_SUPPORT_ANTDIV
#elif( defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_5G_SUPPORT_ANTDIV
#elif( !defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_2G5G_SUPPORT_ANTDIV
#endif
#endif
#ifdef AP_BUILD_WORKAROUND
#include "../typedef.h"
#else
typedef void VOID,*PVOID;
typedef unsigned char BOOLEAN,*PBOOLEAN;
typedef unsigned char u1Byte,*pu1Byte;
typedef unsigned short u2Byte,*pu2Byte;
typedef unsigned int u4Byte,*pu4Byte;
typedef unsigned long long u8Byte,*pu8Byte;
typedef char s1Byte,*ps1Byte;
typedef short s2Byte,*ps2Byte;
typedef long s4Byte,*ps4Byte;
typedef long long s8Byte,*ps8Byte;
#endif
typedef struct rtl8192cd_priv *prtl8192cd_priv;
typedef struct stat_info STA_INFO_T,*PSTA_INFO_T;
typedef struct timer_list RT_TIMER, *PRT_TIMER;
typedef void * RT_TIMER_CALL_BACK;
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#define _TRUE 1
#define _FALSE 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
// To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
#define ADSL_AP_BUILD_WORKAROUND
#define ADSL_BUILD_WORKAROUND
//
typedef unsigned char BOOLEAN,*PBOOLEAN;
typedef unsigned char u1Byte,*pu1Byte;
typedef unsigned short u2Byte,*pu2Byte;
typedef unsigned int u4Byte,*pu4Byte;
typedef unsigned long long u8Byte,*pu8Byte;
typedef char s1Byte,*ps1Byte;
typedef short s2Byte,*ps2Byte;
typedef long s4Byte,*ps4Byte;
typedef long long s8Byte,*ps8Byte;
typedef struct rtl8192cd_priv *prtl8192cd_priv;
typedef struct stat_info STA_INFO_T,*PSTA_INFO_T;
typedef struct timer_list RT_TIMER, *PRT_TIMER;
typedef void * RT_TIMER_CALL_BACK;
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#define _TRUE 1
#define _FALSE 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include <drv_types.h>
#if 0
typedef u8 u1Byte, *pu1Byte;
typedef u16 u2Byte,*pu2Byte;
typedef u32 u4Byte,*pu4Byte;
typedef u64 u8Byte,*pu8Byte;
typedef s8 s1Byte,*ps1Byte;
typedef s16 s2Byte,*ps2Byte;
typedef s32 s4Byte,*ps4Byte;
typedef s64 s8Byte,*ps8Byte;
#else
#define u1Byte u8
#define pu1Byte u8*
#define u2Byte u16
#define pu2Byte u16*
#define u4Byte u32
#define pu4Byte u32*
#define u8Byte u64
#define pu8Byte u64*
#define s1Byte s8
#define ps1Byte s8*
#define s2Byte s16
#define ps2Byte s16*
#define s4Byte s32
#define ps4Byte s32*
#define s8Byte s64
#define ps8Byte s64*
#endif
#ifdef CONFIG_USB_HCI
#define DEV_BUS_TYPE RT_USB_INTERFACE
#elif defined(CONFIG_PCI_HCI)
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#elif defined(CONFIG_SDIO_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#elif defined(CONFIG_GSPI_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#endif
#if defined(CONFIG_LITTLE_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#elif defined (CONFIG_BIG_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#endif
typedef struct timer_list RT_TIMER, *PRT_TIMER;
typedef void * RT_TIMER_CALL_BACK;
#define STA_INFO_T struct sta_info
#define PSTA_INFO_T struct sta_info *
#define TRUE _TRUE
#define FALSE _FALSE
#define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value)
#define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value)
#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value)
//define useless flag to avoid compile warning
#define USE_WORKITEM 0
#define FOR_BRAZIL_PRETEST 0
#define FPGA_TWO_MAC_VERIFICATION 0
#define RTL8881A_SUPPORT 0
#endif
#endif // __ODM_TYPES_H__

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
u1Byte
ODM_GetAutoChannelSelectResult(
IN PVOID pDM_VOID,
IN u1Byte Band
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PACS pACS = &pDM_Odm->DM_ACS;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(Band == ODM_BAND_2_4G) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_2G(%d)\n", pACS->CleanChannel_2G));
return (u1Byte)pACS->CleanChannel_2G;
} else {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_5G(%d)\n", pACS->CleanChannel_5G));
return (u1Byte)pACS->CleanChannel_5G;
}
#else
return (u1Byte)pACS->CleanChannel_2G;
#endif
}
VOID
odm_AutoChannelSelectSetting(
IN PVOID pDM_VOID,
IN BOOLEAN IsEnable
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u2Byte period = 0x2710;// 40ms in default
u2Byte NHMType = 0x7;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSetting()=========> \n"));
if(IsEnable) {
//20 ms
period = 0x1388;
NHMType = 0x1;
}
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
//PHY parameters initialize for ac series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, period); //0x990[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms
//ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, NHMType); //0x994[9:8]=3 enable CCX
} else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
//PHY parameters initialize for n series
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, period); //0x894[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms
//ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, NHMType); //0x890[9:8]=3 enable CCX
}
#endif
}
VOID
odm_AutoChannelSelectInit(
IN PVOID pDM_VOID
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PACS pACS = &pDM_Odm->DM_ACS;
u1Byte i;
if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
return;
if(pACS->bForceACSResult)
return;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectInit()=========> \n"));
pACS->CleanChannel_2G = 1;
pACS->CleanChannel_5G = 36;
for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i) {
pACS->Channel_Info_2G[0][i] = 0;
pACS->Channel_Info_2G[1][i] = 0;
}
if(pDM_Odm->SupportICType & (ODM_IC_11AC_SERIES|ODM_RTL8192D)) {
for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i) {
pACS->Channel_Info_5G[0][i] = 0;
pACS->Channel_Info_5G[1][i] = 0;
}
}
#endif
}
VOID
odm_AutoChannelSelectReset(
IN PVOID pDM_VOID
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PACS pACS = &pDM_Odm->DM_ACS;
if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
return;
if(pACS->bForceACSResult)
return;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectReset()=========> \n"));
odm_AutoChannelSelectSetting(pDM_Odm,TRUE);// for 20ms measurement
Phydm_NHMCounterStatisticsReset(pDM_Odm);
#endif
}
VOID
odm_AutoChannelSelect(
IN PVOID pDM_VOID,
IN u1Byte Channel
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PACS pACS = &pDM_Odm->DM_ACS;
u1Byte ChannelIDX = 0, SearchIDX = 0;
u2Byte MaxScore=0;
if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Return: SupportAbility ODM_BB_NHM_CNT is disabled\n"));
return;
}
if(pACS->bForceACSResult) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Force 2G clean channel = %d, 5G clean channel = %d\n",
pACS->CleanChannel_2G, pACS->CleanChannel_5G));
return;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel = %d=========> \n", Channel));
Phydm_GetNHMCounterStatistics(pDM_Odm);
odm_AutoChannelSelectSetting(pDM_Odm,FALSE);
if(Channel >=1 && Channel <=14) {
ChannelIDX = Channel - 1;
pACS->Channel_Info_2G[1][ChannelIDX]++;
if(pACS->Channel_Info_2G[1][ChannelIDX] >= 2)
pACS->Channel_Info_2G[0][ChannelIDX] = (pACS->Channel_Info_2G[0][ChannelIDX] >> 1) +
(pACS->Channel_Info_2G[0][ChannelIDX] >> 2) + (pDM_Odm->NHM_cnt_0>>2);
else
pACS->Channel_Info_2G[0][ChannelIDX] = pDM_Odm->NHM_cnt_0;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): NHM_cnt_0 = %d \n", pDM_Odm->NHM_cnt_0));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n", ChannelIDX, pACS->Channel_Info_2G[0][ChannelIDX], ChannelIDX, pACS->Channel_Info_2G[1][ChannelIDX]));
for(SearchIDX = 0; SearchIDX < ODM_MAX_CHANNEL_2G; SearchIDX++) {
if(pACS->Channel_Info_2G[1][SearchIDX] != 0) {
if(pACS->Channel_Info_2G[0][SearchIDX] >= MaxScore) {
MaxScore = pACS->Channel_Info_2G[0][SearchIDX];
pACS->CleanChannel_2G = SearchIDX+1;
}
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("(1)odm_AutoChannelSelect(): 2G: CleanChannel_2G = %d, MaxScore = %d \n",
pACS->CleanChannel_2G, MaxScore));
} else if(Channel >= 36) {
// Need to do
pACS->CleanChannel_5G = Channel;
}
#endif
}

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMACS_H__
#define __PHYDMACS_H__
#define ACS_VERSION "1.0"
#define ODM_MAX_CHANNEL_2G 14
#define ODM_MAX_CHANNEL_5G 24
typedef struct _ACS_ {
BOOLEAN bForceACSResult;
u1Byte CleanChannel_2G;
u1Byte CleanChannel_5G;
u2Byte Channel_Info_2G[2][ODM_MAX_CHANNEL_2G]; //Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times
u2Byte Channel_Info_5G[2][ODM_MAX_CHANNEL_5G];
} ACS, *PACS;
VOID
odm_AutoChannelSelectInit(
IN PVOID pDM_VOID
);
VOID
odm_AutoChannelSelectReset(
IN PVOID pDM_VOID
);
VOID
odm_AutoChannelSelect(
IN PVOID pDM_VOID,
IN u1Byte Channel
);
u1Byte
ODM_GetAutoChannelSelectResult(
IN PVOID pDM_VOID,
IN u1Byte Band
);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMANTDECT_H__
#define __PHYDMANTDECT_H__
#define ANTDECT_VERSION "2.0" //2014.11.04
#if(defined(CONFIG_ANT_DETECTION))
//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))
//ANT Test
#define ANTTESTALL 0x00 //Ant A or B will be Testing
#define ANTTESTA 0x01 //Ant A will be Testing
#define ANTTESTB 0x02 //Ant B will be testing
#define MAX_ANTENNA_DETECTION_CNT 10
typedef struct _ANT_DETECTED_INFO {
BOOLEAN bAntDetected;
u4Byte dBForAntA;
u4Byte dBForAntB;
u4Byte dBForAntO;
} ANT_DETECTED_INFO, *PANT_DETECTED_INFO;
typedef enum tag_SW_Antenna_Switch_Definition {
Antenna_A = 1,
Antenna_B = 2,
Antenna_MAX = 3,
} DM_SWAS_E;
//1 [1. Single Tone Method] ===================================================
VOID
ODM_SingleDualAntennaDefaultSetting(
IN PVOID pDM_VOID
);
BOOLEAN
ODM_SingleDualAntennaDetection(
IN PVOID pDM_VOID,
IN u1Byte mode
);
//1 [2. Scan AP RSSI Method] ==================================================
#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink
BOOLEAN
ODM_SwAntDivCheckBeforeLink(
IN PVOID pDM_VOID
);
//1 [3. PSD Method] ==========================================================
VOID
ODM_SingleDualAntennaDetection_PSD(
IN PVOID pDM_VOID
);
#endif
VOID
odm_SwAntDetectInit(
IN PVOID pDM_VOID
);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMANTDIV_H__
#define __PHYDMANTDIV_H__
#define ANTDIV_VERSION "2.0" //2014.11.04
//1 ============================================================
//1 Definition
//1 ============================================================
#define MAIN_ANT 1 //Ant A or Ant Main
#define AUX_ANT 2 //AntB or Ant Aux
#define MAX_ANT 3 // 3 for AP using
#define ANT1_2G 0 // = ANT2_5G
#define ANT2_2G 1 // = ANT1_5G
//Antenna Diversty Control Type
#define ODM_AUTO_ANT 0
#define ODM_FIX_MAIN_ANT 1
#define ODM_FIX_AUX_ANT 2
#define ODM_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)
#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E)
#define ODM_OLD_IC_ANTDIV_SUPPORT (ODM_RTL8723A|ODM_RTL8192C|ODM_RTL8192D)
#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A)
#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
#define ODM_ANTDIV_2G BIT0
#define ODM_ANTDIV_5G BIT1
#define ANTDIV_ON 1
#define ANTDIV_OFF 0
#define FAT_ON 1
#define FAT_OFF 0
#define TX_BY_DESC 1
#define REG 0
#define RSSI_METHOD 0
#define EVM_METHOD 1
#define CRC32_METHOD 2
#define INIT_ANTDIV_TIMMER 0
#define CANCEL_ANTDIV_TIMMER 1
#define RELEASE_ANTDIV_TIMMER 2
#define CRC32_FAIL 1
#define CRC32_OK 0
#define Evm_RSSI_TH_High 25
#define Evm_RSSI_TH_Low 20
#define NORMAL_STATE_MIAN 1
#define NORMAL_STATE_AUX 2
#define TRAINING_STATE 3
#define FORCE_RSSI_DIFF 10
#define CSI_ON 1
#define CSI_OFF 0
#define DIVON_CSIOFF 1
#define DIVOFF_CSION 2
#define BDC_DIV_TRAIN_STATE 0
#define BDC_BFer_TRAIN_STATE 1
#define BDC_DECISION_STATE 2
#define BDC_BF_HOLD_STATE 3
#define BDC_DIV_HOLD_STATE 4
#define BDC_MODE_1 1
#define BDC_MODE_2 2
#define BDC_MODE_3 3
#define BDC_MODE_4 4
#define BDC_MODE_NULL 0xff
#define SWAW_STEP_PEAK 0
#define SWAW_STEP_DETERMINE 1
//1 ============================================================
//1 structure
//1 ============================================================
typedef struct _SW_Antenna_Switch_ {
u1Byte Double_chk_flag;
u1Byte try_flag;
s4Byte PreRSSI;
u1Byte CurAntenna;
u1Byte PreAntenna;
u1Byte RSSI_Trying;
u1Byte TestMode;
u1Byte bTriggerAntennaSwitch;
u1Byte SelectAntennaMap;
u1Byte RSSI_target;
u1Byte reset_idx;
u2Byte Single_Ant_Counter;
u2Byte Dual_Ant_Counter;
u2Byte Aux_FailDetec_Counter;
u2Byte Retry_Counter;
// Before link Antenna Switch check
u1Byte SWAS_NoLink_State;
u4Byte SWAS_NoLink_BK_Reg860;
u4Byte SWAS_NoLink_BK_Reg92c;
u4Byte SWAS_NoLink_BK_Reg948;
BOOLEAN ANTA_ON; //To indicate Ant A is or not
BOOLEAN ANTB_ON; //To indicate Ant B is on or not
BOOLEAN Pre_Aux_FailDetec;
BOOLEAN RSSI_AntDect_bResult;
u1Byte Ant5G;
u1Byte Ant2G;
s4Byte RSSI_sum_A;
s4Byte RSSI_sum_B;
s4Byte RSSI_cnt_A;
s4Byte RSSI_cnt_B;
u8Byte lastTxOkCnt;
u8Byte lastRxOkCnt;
u8Byte TXByteCnt_A;
u8Byte TXByteCnt_B;
u8Byte RXByteCnt_A;
u8Byte RXByteCnt_B;
u1Byte TrafficLoad;
u1Byte Train_time;
u1Byte Train_time_flag;
RT_TIMER SwAntennaSwitchTimer;
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
RT_TIMER SwAntennaSwitchTimer_8723B;
u4Byte PktCnt_SWAntDivByCtrlFrame;
BOOLEAN bSWAntDivByCtrlFrame;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if USE_WORKITEM
RT_WORK_ITEM SwAntennaSwitchWorkitem;
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
RT_WORK_ITEM SwAntennaSwitchWorkitem_8723B;
#endif
#endif
#endif
/* CE Platform use
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
_timer SwAntennaSwitchTimer;
u8Byte lastTxOkCnt;
u8Byte lastRxOkCnt;
u8Byte TXByteCnt_A;
u8Byte TXByteCnt_B;
u8Byte RXByteCnt_A;
u8Byte RXByteCnt_B;
u1Byte DoubleComfirm;
u1Byte TrafficLoad;
//SW Antenna Switch
#endif
*/
#ifdef CONFIG_HW_ANTENNA_DIVERSITY
//Hybrid Antenna Diversity
u4Byte CCK_Ant1_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte CCK_Ant2_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte OFDM_Ant1_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte OFDM_Ant2_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte RSSI_Ant1_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte RSSI_Ant2_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte TxAnt[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte TargetSTA;
u1Byte antsel;
u1Byte RxIdleAnt;
#endif
} SWAT_T, *pSWAT_T;
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
typedef struct _BF_DIV_COEX_ {
BOOLEAN w_BFer_Client[ODM_ASSOCIATE_ENTRY_NUM];
BOOLEAN w_BFee_Client[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte BDCcoexType_wBfer;
u1Byte num_Txbfee_Client;
u1Byte num_Txbfer_Client;
u1Byte BDC_Try_counter;
u1Byte BDC_Hold_counter;
u1Byte BDC_Mode;
u1Byte BDC_active_Mode;
u1Byte BDC_state;
u1Byte BDC_RxIdleUpdate_counter;
u1Byte num_Client;
u1Byte pre_num_Client;
u1Byte num_BfTar;
u1Byte num_DivTar;
BOOLEAN bAll_DivSta_Idle;
BOOLEAN bAll_BFSta_Idle;
BOOLEAN BDC_Try_flag;
BOOLEAN BF_pass;
BOOLEAN DIV_pass;
} BDC_T,*pBDC_T;
#endif
#endif
typedef struct _FAST_ANTENNA_TRAINNING_ {
u1Byte Bssid[6];
u1Byte antsel_rx_keep_0;
u1Byte antsel_rx_keep_1;
u1Byte antsel_rx_keep_2;
u1Byte antsel_rx_keep_3;
u4Byte antSumRSSI[7];
u4Byte antRSSIcnt[7];
u4Byte antAveRSSI[7];
u1Byte FAT_State;
u4Byte TrainIdx;
u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte RxIdleAnt;
u1Byte AntDiv_OnOff;
BOOLEAN bBecomeLinked;
u4Byte MinMaxRSSI;
u1Byte idx_AntDiv_counter_2G;
u1Byte idx_AntDiv_counter_5G;
u1Byte AntDiv_2G_5G;
u4Byte CCK_counter_main;
u4Byte CCK_counter_aux;
u4Byte OFDM_counter_main;
u4Byte OFDM_counter_aux;
#ifdef ODM_EVM_ENHANCE_ANTDIV
u4Byte MainAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MainAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
BOOLEAN EVM_method_enable;
u1Byte TargetAnt_EVM;
u1Byte TargetAnt_CRC32;
u1Byte TargetAnt_enhance;
u1Byte pre_TargetAnt_enhance;
u2Byte Main_MPDU_OK_cnt;
u2Byte Aux_MPDU_OK_cnt;
u4Byte CRC32_Ok_Cnt;
u4Byte CRC32_Fail_Cnt;
u4Byte MainCRC32_Ok_Cnt;
u4Byte AuxCRC32_Ok_Cnt;
u4Byte MainCRC32_Fail_Cnt;
u4Byte AuxCRC32_Fail_Cnt;
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
u4Byte CCK_CtrlFrame_Cnt_main;
u4Byte CCK_CtrlFrame_Cnt_aux;
u4Byte OFDM_CtrlFrame_Cnt_main;
u4Byte OFDM_CtrlFrame_Cnt_aux;
u4Byte MainAnt_CtrlFrame_Sum;
u4Byte AuxAnt_CtrlFrame_Sum;
u4Byte MainAnt_CtrlFrame_Cnt;
u4Byte AuxAnt_CtrlFrame_Cnt;
#endif
BOOLEAN fix_ant_bfee;
} FAT_T,*pFAT_T;
//1 ============================================================
//1 enumeration
//1 ============================================================
typedef enum _FAT_STATE {
FAT_NORMAL_STATE = 0,
FAT_TRAINING_STATE = 1,
} FAT_STATE_E, *PFAT_STATE_E;
typedef enum _ANT_DIV_TYPE {
NO_ANTDIV = 0xFF,
CG_TRX_HW_ANTDIV = 0x01,
CGCS_RX_HW_ANTDIV = 0x02,
FIXED_HW_ANTDIV = 0x03,
CG_TRX_SMART_ANTDIV = 0x04,
CGCS_RX_SW_ANTDIV = 0x05,
S0S1_SW_ANTDIV = 0x06 //8723B intrnal switch S0 S1
} ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
//1 ============================================================
//1 function prototype
//1 ============================================================
VOID
ODM_StopAntennaSwitchDm(
IN PVOID pDM_VOID
);
VOID
ODM_SetAntConfig(
IN PVOID pDM_VOID,
IN u1Byte antSetting // 0=A, 1=B, 2=C, ....
);
#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
VOID ODM_SwAntDivRestAfterLink(
IN PVOID pDM_VOID
);
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
VOID
ODM_UpdateRxIdleAnt(
IN PVOID pDM_VOID,
IN u1Byte Ant
);
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
ODM_SW_AntDiv_Callback(
IN PRT_TIMER pTimer
);
VOID
ODM_SW_AntDiv_WorkitemCallback(
IN PVOID pContext
);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
VOID
ODM_SW_AntDiv_Callback(
void *FunctionContext
);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
odm_S0S1_SwAntDivByCtrlFrame(
IN PVOID pDM_VOID,
IN u1Byte Step
);
VOID
odm_AntselStatisticsOfCtrlFrame(
IN PVOID pDM_VOID,
IN u1Byte antsel_tr_mux,
IN u4Byte RxPWDBAll
);
VOID
odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(
IN PVOID pDM_VOID,
IN PVOID p_phy_info_void,
IN PVOID p_pkt_info_void
);
/*
VOID
odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(
IN PVOID pDM_VOID,
IN PVOID p_phy_info_void,
IN PVOID p_pkt_info_void
);
*/
#endif
#endif
#ifdef ODM_EVM_ENHANCE_ANTDIV
VOID
odm_EVM_FastAntTrainingCallback(
IN PVOID pDM_VOID
);
#endif
VOID
odm_HW_AntDiv(
IN PVOID pDM_VOID
);
#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )
VOID
odm_FastAntTraining(
IN PVOID pDM_VOID
);
VOID
odm_FastAntTrainingCallback(
IN PVOID pDM_VOID
);
VOID
odm_FastAntTrainingWorkItemCallback(
IN PVOID pDM_VOID
);
#endif
VOID
ODM_AntDivInit(
IN PVOID pDM_VOID
);
VOID
ODM_AntDiv(
IN PVOID pDM_VOID
);
VOID
odm_AntselStatistics(
IN PVOID pDM_VOID,
IN u1Byte antsel_tr_mux,
IN u4Byte MacId,
IN u4Byte utility,
IN u1Byte method
);
/*
VOID
ODM_Process_RSSIForAntDiv(
IN OUT PVOID pDM_VOID,
IN PVOID p_phy_info_void,
IN PVOID p_pkt_info_void
);
*/
VOID
ODM_Process_RSSIForAntDiv(
IN OUT PVOID pDM_VOID,
IN PVOID p_phy_info_void,
IN PVOID p_pkt_info_void
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
ODM_SetTxAntByTxInfo(
IN PVOID pDM_VOID,
IN pu1Byte pDesc,
IN u1Byte macId
);
#elif(DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
ODM_SetTxAntByTxInfo(
struct rtl8192cd_priv *priv,
struct tx_desc *pdesc,
unsigned short aid
);
#endif
VOID
ODM_AntDiv_Config(
IN PVOID pDM_VOID
);
VOID
ODM_UpdateRxIdleAnt_8723B(
IN PVOID pDM_VOID,
IN u1Byte Ant,
IN u4Byte DefaultAnt,
IN u4Byte OptionalAnt
);
VOID
ODM_AntDivTimers(
IN PVOID pDM_VOID,
IN u1Byte state
);
#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
VOID
ODM_AntDivReset(
IN PVOID pDM_VOID
);
VOID
odm_AntennaDiversityInit(
IN PVOID pDM_VOID
);
VOID
odm_AntennaDiversity(
IN PVOID pDM_VOID
);
#endif //#ifndef __ODMANTDIV_H__

323
backports/drivers/realtek/rtl8812au/hal/OUTSRC/phydm_CfoTracking.c Normal file
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@@ -0,0 +1,323 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
VOID
odm_SetCrystalCap(
IN PVOID pDM_VOID,
IN u1Byte CrystalCap
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
BOOLEAN bEEPROMCheck;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
bEEPROMCheck = (pHalData->EEPROMVersion >= 0x01)?TRUE:FALSE;
#else
bEEPROMCheck = TRUE;
#endif
if(pCfoTrack->CrystalCap == CrystalCap)
return;
pCfoTrack->CrystalCap = CrystalCap;
if(pDM_Odm->SupportICType & ODM_RTL8192D) {
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x000000F0, CrystalCap & 0x0F);
ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0xF0000000, ((CrystalCap & 0xF0) >> 4));
} else if(pDM_Odm->SupportICType & ODM_RTL8188E) {
// write 0x24[22:17] = 0x24[16:11] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x007ff800, (CrystalCap | (CrystalCap << 6)));
} else if(pDM_Odm->SupportICType & ODM_RTL8812) {
// write 0x2C[30:25] = 0x2C[24:19] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap | (CrystalCap << 6)));
} else if (((pDM_Odm->SupportICType & ODM_RTL8723A) && bEEPROMCheck) ||
(pDM_Odm->SupportICType & ODM_RTL8723B) ||(pDM_Odm->SupportICType & ODM_RTL8192E) ||
(pDM_Odm->SupportICType & ODM_RTL8821)) {
// 0x2C[23:18] = 0x2C[17:12] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x00FFF000, (CrystalCap | (CrystalCap << 6)));
} else if(pDM_Odm->SupportICType & ODM_RTL8821B) {
// write 0x28[6:1] = 0x24[30:25] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7E000000, CrystalCap);
ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7E, CrystalCap);
} else if(pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B)) {
// write 0x2C[26:21] = 0x2C[20:15] = CrystalCap
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x07FF8000, (CrystalCap | (CrystalCap << 6)));
} else {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): Use default setting.\n"));
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6)));
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): CrystalCap = 0x%x\n", CrystalCap));
}
u1Byte
odm_GetDefaultCrytaltalCap(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u1Byte CrystalCap = 0x20;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
CrystalCap = pHalData->CrystalCap;
#else
prtl8192cd_priv priv = pDM_Odm->priv;
if(priv->pmib->dot11RFEntry.xcap > 0)
CrystalCap = priv->pmib->dot11RFEntry.xcap;
#endif
CrystalCap = CrystalCap & 0x3f;
return CrystalCap;
}
VOID
odm_SetATCStatus(
IN PVOID pDM_VOID,
IN BOOLEAN ATCStatus
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
if(pCfoTrack->bATCStatus == ATCStatus)
return;
ODM_SetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm), ATCStatus);
pCfoTrack->bATCStatus = ATCStatus;
}
BOOLEAN
odm_GetATCStatus(
IN PVOID pDM_VOID
)
{
BOOLEAN ATCStatus;
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
ATCStatus = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm));
return ATCStatus;
}
VOID
ODM_CfoTrackingReset(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
//u1Byte CrystalCap;
pCfoTrack->DefXCap = odm_GetDefaultCrytaltalCap(pDM_Odm);
pCfoTrack->bAdjust = TRUE;
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap);
odm_SetATCStatus(pDM_Odm, TRUE);
#else
if(pCfoTrack->CrystalCap > pCfoTrack->DefXCap) {
for(CrystalCap = pCfoTrack->CrystalCap; CrystalCap >= pCfoTrack->DefXCap; CrystalCap--)
odm_SetCrystalCap(pDM_Odm, CrystalCap);
} else {
for(CrystalCap = pCfoTrack->CrystalCap; CrystalCap <= pCfoTrack->DefXCap; CrystalCap++)
odm_SetCrystalCap(pDM_Odm, CrystalCap);
}
#endif
}
VOID
ODM_CfoTrackingInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
pCfoTrack->DefXCap = pCfoTrack->CrystalCap = odm_GetDefaultCrytaltalCap(pDM_Odm);
pCfoTrack->bATCStatus = odm_GetATCStatus(pDM_Odm);
pCfoTrack->bAdjust = TRUE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========> \n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): bATCStatus = %d, CrystalCap = 0x%x \n",pCfoTrack->bATCStatus, pCfoTrack->DefXCap));
}
VOID
ODM_CfoTracking(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
int CFO_kHz_A, CFO_kHz_B, CFO_ave = 0;
int CFO_ave_diff;
int CrystalCap = (int)pCfoTrack->CrystalCap;
u1Byte Adjust_Xtal = 1;
//4 Support ability
if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Return: SupportAbility ODM_BB_CFO_TRACKING is disabled\n"));
return;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking()=========> \n"));
if(!pDM_Odm->bLinked || !pDM_Odm->bOneEntryOnly) {
//4 No link or more than one entry
ODM_CfoTrackingReset(pDM_Odm);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Reset: bLinked = %d, bOneEntryOnly = %d\n",
pDM_Odm->bLinked, pDM_Odm->bOneEntryOnly));
} else {
//3 1. CFO Tracking
//4 1.1 No new packet
if(pCfoTrack->packetCount == pCfoTrack->packetCount_pre) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): packet counter doesn't change\n"));
return;
}
pCfoTrack->packetCount_pre = pCfoTrack->packetCount;
//4 1.2 Calculate CFO
CFO_kHz_A = (int)(pCfoTrack->CFO_tail[0] * 3125) / 1280;
CFO_kHz_B = (int)(pCfoTrack->CFO_tail[1] * 3125) / 1280;
if(pDM_Odm->RFType < ODM_2T2R)
CFO_ave = CFO_kHz_A;
else
CFO_ave = (int)(CFO_kHz_A + CFO_kHz_B) >> 1;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): CFO_kHz_A = %dkHz, CFO_kHz_B = %dkHz, CFO_ave = %dkHz\n",
CFO_kHz_A, CFO_kHz_B, CFO_ave));
//4 1.3 Avoid abnormal large CFO
CFO_ave_diff = (pCfoTrack->CFO_ave_pre >= CFO_ave)?(pCfoTrack->CFO_ave_pre - CFO_ave):(CFO_ave - pCfoTrack->CFO_ave_pre);
if(CFO_ave_diff > 20 && pCfoTrack->largeCFOHit == 0 && !pCfoTrack->bAdjust) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): first large CFO hit\n"));
pCfoTrack->largeCFOHit = 1;
return;
} else
pCfoTrack->largeCFOHit = 0;
pCfoTrack->CFO_ave_pre = CFO_ave;
//4 1.4 Dynamic Xtal threshold
if(pCfoTrack->bAdjust == FALSE) {
if(CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH))
pCfoTrack->bAdjust = TRUE;
} else {
if(CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW))
pCfoTrack->bAdjust = FALSE;
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
//4 1.5 BT case: Disable CFO tracking
if(pDM_Odm->bBtEnabled) {
pCfoTrack->bAdjust = FALSE;
odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable CFO tracking for BT!!\n"));
}
//4 1.6 Big jump
if(pCfoTrack->bAdjust) {
if(CFO_ave > CFO_TH_XTAL_LOW)
Adjust_Xtal = Adjust_Xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2);
else if(CFO_ave < (-CFO_TH_XTAL_LOW))
Adjust_Xtal = Adjust_Xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap offset = %d\n", Adjust_Xtal));
}
#endif
//4 1.7 Adjust Crystal Cap.
if(pCfoTrack->bAdjust) {
if(CFO_ave > CFO_TH_XTAL_LOW)
CrystalCap = CrystalCap + Adjust_Xtal;
else if(CFO_ave < (-CFO_TH_XTAL_LOW))
CrystalCap = CrystalCap - Adjust_Xtal;
if(CrystalCap > 0x3f)
CrystalCap = 0x3f;
else if (CrystalCap < 0)
CrystalCap = 0;
odm_SetCrystalCap(pDM_Odm, (u1Byte)CrystalCap);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n",
pCfoTrack->CrystalCap, pCfoTrack->DefXCap));
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
return;
//3 2. Dynamic ATC switch
if(CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC) {
odm_SetATCStatus(pDM_Odm, FALSE);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable ATC!!\n"));
} else {
odm_SetATCStatus(pDM_Odm, TRUE);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Enable ATC!!\n"));
}
#endif
}
}
VOID
ODM_ParsingCFO(
IN PVOID pDM_VOID,
IN PVOID pPktinfo_VOID,
IN s1Byte* pcfotail
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PODM_PACKET_INFO_T pPktinfo = (PODM_PACKET_INFO_T)pPktinfo_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
u1Byte i;
if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING))
return;
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(pPktinfo->bPacketMatchBSSID)
#else
if(pPktinfo->StationID != 0)
#endif
{
//3 Update CFO report for path-A & path-B
// Only paht-A and path-B have CFO tail and short CFO
for(i = ODM_RF_PATH_A; i <= ODM_RF_PATH_B; i++) {
pCfoTrack->CFO_tail[i] = (int)pcfotail[i];
}
//3 Update packet counter
if(pCfoTrack->packetCount == 0xffffffff)
pCfoTrack->packetCount = 0;
else
pCfoTrack->packetCount++;
}
}

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