shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 19:30:30 +09:00
Code Issues Packages Projects Releases Wiki Activity

drm/rockchip: lvds: optimized power on/off sequences

Browse Source 
we can power off the bandgap to reduce power consumption.

Change-Id: I13be04116cce098e5a3606659a64bc4d96093b44
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2018-11-16 10:32:24 +08:00
committed by Tao Huang
parent 7ecb69d8af
commit 27a168dc32
2 changed files with 8 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/drm/rockchip/rockchip_lvds.c
View File

@@ -245,9 +245,10 @@ static int innov1_lvds_power_on(struct rockchip_lvds *lvds)
if (lvds->output == DISPLAY_OUTPUT_RGB) {
/* enable lane */
lvds_writel(lvds, MIPIPHY_REG0, 0x7f);
lvds_msk_reg(lvds, MIPIPHY_REG0, 0x7c, 0x7c);
val = v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) |
v_LANE3_EN(1) | v_LANECLK_EN(1) | v_PLL_PWR_OFF(1);
v_LANE3_EN(1) | v_LANECLK_EN(1) | v_PLL_PWR_OFF(1) |
v_LVDS_BGPD(0);
lvds_writel(lvds, MIPIPHY_REGEB, val);
/* set ttl mode and reset phy config */
@@ -288,7 +289,8 @@ static int innov1_lvds_power_on(struct rockchip_lvds *lvds)
/* enable lvds lane and power on pll */
lvds_writel(lvds, MIPIPHY_REGEB,
v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) |
v_LANE3_EN(1) | v_LANECLK_EN(1) | v_PLL_PWR_OFF(0));
v_LANE3_EN(1) | v_LANECLK_EN(1) | v_PLL_PWR_OFF(0) |
v_LVDS_BGPD(0));
/* enable lvds */
lvds_msk_reg(lvds, MIPIPHY_REGE3,
@@ -318,7 +320,8 @@ static void innov1_lvds_power_off(struct rockchip_lvds *lvds)
/* disable lvds lane and power off pll */
lvds_writel(lvds, MIPIPHY_REGEB,
v_LANE0_EN(0) | v_LANE1_EN(0) | v_LANE2_EN(0) |
v_LANE3_EN(0) | v_LANECLK_EN(0) | v_PLL_PWR_OFF(1));
v_LANE3_EN(0) | v_LANECLK_EN(0) | v_PLL_PWR_OFF(1) |
v_LVDS_BGPD(1));
/* power down lvds pll and bandgap */
lvds_msk_reg(lvds, MIPIPHY_REG1,

1
drivers/gpu/drm/rockchip/rockchip_lvds.h
View File

@@ -196,6 +196,7 @@
#define MIPIPHY_REGE8 0x03a0
#define MIPIPHY_REGEB 0x03ac
#define v_LVDS_BGPD(x) BITS_MASK(x, 1, 0)
#define v_PLL_PWR_OFF(x) BITS_MASK(x, 1, 2)
#define v_LANECLK_EN(x) BITS_MASK(x, 1, 3)
#define v_LANE3_EN(x) BITS_MASK(x, 1, 4)