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BACKPORT: FROMLIST: clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228

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commit c420c1e4db ("clk: rockchip: Prevent calculating mmc phase
if clock rate is zero") catches one gremlin again for clk-rk3228.c
that the parent of SDMMC phase clock should be sclk_sdmmc0, but not
sclk_sdmmc. However, I don't like the name of sclk_sdmmc0, so I now
rename it to be sclk_sdmmc.

Change-Id: I1cf16aa1c639ce4776347b40a36bde241c800c03
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry-picked from https://patchwork.kernel.org/patch/10298427/)
This commit is contained in:
Shawn Lin
2018-03-21 10:46:05 +08:00
committed by Tao Huang
parent a4b0a0f6bf
commit 29b6b16557
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3228.c
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@@ -367,7 +367,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 15, GFLAGS),
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK2928_CLKGATE_CON(2), 11, GFLAGS),