video: rockchip: mpp: add control to query hw_id

Change-Id: I246f9484e5f6a9d8ed65bd4962d1472e717c3aa3
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>

drivers/video/rockchip/mpp/mpp_common.c

@@ -742,6 +742,17 @@ static int mpp_process_request(struct mpp_session *session,
 		if (put_user(hw_support, (u32 __user *)req->data))
 			return -EFAULT;
 	} break;
+	case MPP_CMD_QUERY_HW_ID: {
+		struct mpp_hw_info *hw_info;
+
+		mpp = session->mpp;
+		if (!mpp)
+			return -EINVAL;
+		hw_info = mpp->var->hw_info;
+		mpp_debug(DEBUG_IOCTL, "hw_id %08x\n", hw_info->hw_id);
+		if (put_user(hw_info->hw_id, (u32 __user *)req->data))
+			return -EFAULT;
+	} break;
 	case MPP_CMD_INIT_CLIENT_TYPE: {
 		u32 client_type;
 

drivers/video/rockchip/mpp/mpp_common.h

@@ -75,6 +75,7 @@ enum MPP_DRIVER_TYPE {
 enum MPP_DEV_COMMAND_TYPE {
 	MPP_CMD_QUERY_BASE		= 0,
 	MPP_CMD_QUERY_HW_SUPPORT	= MPP_CMD_QUERY_BASE + 0,
+	MPP_CMD_QUERY_HW_ID		= MPP_CMD_QUERY_BASE + 1,
 
 	MPP_CMD_INIT_BASE		= 0x100,
 	MPP_CMD_INIT_CLIENT_TYPE	= MPP_CMD_INIT_BASE + 0,
@@ -124,6 +125,9 @@ struct mpp_grf_info {
 struct mpp_hw_info {
 	/* register number */
 	u32 reg_num;
+	/* hardware id */
+	u32 regidx_id;
+	u32 hw_id;
 	/* start index of register */
 	u32 regidx_start;
 	/* end index of register */

drivers/video/rockchip/mpp/mpp_rkvdec.c

@@ -45,14 +45,17 @@
 #define	RKVDEC_SESSION_MAX_BUFFERS	40
 /* The maximum registers number of all the version */
 #define HEVC_DEC_REG_NUM		68
+#define HEVC_DEC_REG_HW_ID_INDEX	0
 #define HEVC_DEC_REG_START_INDEX	0
 #define HEVC_DEC_REG_END_INDEX		67
 
 #define RKVDEC_V1_REG_NUM		78
+#define RKVDEC_V1_REG_HW_ID_INDEX	0
 #define RKVDEC_V1_REG_START_INDEX	0
 #define RKVDEC_V1_REG_END_INDEX		77
 
 #define RKVDEC_V2_REG_NUM		109
+#define RKVDEC_V2_REG_HW_ID_INDEX	0
 #define RKVDEC_V2_REG_START_INDEX	0
 #define RKVDEC_V2_REG_END_INDEX		108
 
@@ -187,6 +190,7 @@ struct rkvdec_dev {
  */
 static struct mpp_hw_info rk_hevcdec_hw_info = {
 	.reg_num = HEVC_DEC_REG_NUM,
+	.regidx_id = HEVC_DEC_REG_HW_ID_INDEX,
 	.regidx_start = HEVC_DEC_REG_START_INDEX,
 	.regidx_end = HEVC_DEC_REG_END_INDEX,
 	.regidx_en = RKVDEC_REG_INT_EN_INDEX,
@@ -194,6 +198,7 @@ static struct mpp_hw_info rk_hevcdec_hw_info = {
 
 static struct mpp_hw_info rkvdec_v1_hw_info = {
 	.reg_num = RKVDEC_V1_REG_NUM,
+	.regidx_id = RKVDEC_V1_REG_HW_ID_INDEX,
 	.regidx_start = RKVDEC_V1_REG_START_INDEX,
 	.regidx_end = RKVDEC_V1_REG_END_INDEX,
 	.regidx_en = RKVDEC_REG_INT_EN_INDEX,
@@ -991,6 +996,7 @@ static int rkvdec_debugfs_init(struct mpp_dev *mpp)
 
 static int rkvdec_init(struct mpp_dev *mpp)
 {
+	struct mpp_hw_info *hw_info;
 	struct rkvdec_dev *dec = to_rkvdec_dev(mpp);
 
 	mutex_init(&dec->sip_reset_lock);
@@ -1050,6 +1056,10 @@ static int rkvdec_init(struct mpp_dev *mpp)
 		dec->rst_core = NULL;
 	}
 
+	/* read hardware id*/
+	hw_info = mpp->var->hw_info;
+	hw_info->hw_id = mpp_read(mpp, hw_info->regidx_id);
+
 	return 0;
 }
 

drivers/video/rockchip/mpp/mpp_vdpu1.c

@@ -31,6 +31,7 @@
 #define	VDPU1_SESSION_MAX_BUFFERS	40
 /* The maximum registers number of all the version */
 #define VDPU1_REG_NUM			60
+#define VDPU1_REG_HW_ID_INDEX		0
 #define VDPU1_REG_START_INDEX		0
 #define VDPU1_REG_END_INDEX		59
 
@@ -118,6 +119,7 @@ struct vdpu_dev {
 
 static struct mpp_hw_info vdpu_v1_hw_info = {
 	.reg_num = VDPU1_REG_NUM,
+	.regidx_id = VDPU1_REG_HW_ID_INDEX,
 	.regidx_start = VDPU1_REG_START_INDEX,
 	.regidx_end = VDPU1_REG_END_INDEX,
 	.regidx_en = VDPU1_REG_DEC_INT_EN_INDEX,
@@ -125,6 +127,7 @@ static struct mpp_hw_info vdpu_v1_hw_info = {
 
 static struct mpp_hw_info vdpu_pp_v1_hw_info = {
 	.reg_num = VDPU1_REG_PP_NUM,
+	.regidx_id = VDPU1_REG_HW_ID_INDEX,
 	.regidx_start = VDPU1_REG_PP_START_INDEX,
 	.regidx_end = VDPU1_REG_PP_END_INDEX,
 	.regidx_en = VDPU1_REG_DEC_INT_EN_INDEX,
@@ -463,6 +466,7 @@ static int vdpu_debugfs_init(struct mpp_dev *mpp)
 
 static int vdpu_init(struct mpp_dev *mpp)
 {
+	struct mpp_hw_info *hw_info;
 	struct vdpu_dev *dec = to_vdpu_dev(mpp);
 
 	mpp->grf_info = &mpp->srv->grf_infos[MPP_DRIVER_VDPU1];
@@ -489,6 +493,10 @@ static int vdpu_init(struct mpp_dev *mpp)
 		dec->rst_h = NULL;
 	}
 
+	/* read hardware id*/
+	hw_info = mpp->var->hw_info;
+	hw_info->hw_id = mpp_read(mpp, hw_info->regidx_id);
+
 	return 0;
 }
 

drivers/video/rockchip/mpp/mpp_vepu1.c

@@ -30,6 +30,7 @@
 #define	VEPU1_SESSION_MAX_BUFFERS	20
 /* The maximum registers number of all the version */
 #define VEPU1_REG_NUM			164
+#define VEPU1_REG_HW_ID_INDEX		0
 #define VEPU1_REG_START_INDEX		0
 #define VEPU1_REG_END_INDEX		163
 
@@ -95,6 +96,7 @@ struct vepu_dev {
 
 static struct mpp_hw_info vepu_v1_hw_info = {
 	.reg_num = VEPU1_REG_NUM,
+	.regidx_id = VEPU1_REG_HW_ID_INDEX,
 	.regidx_start = VEPU1_REG_START_INDEX,
 	.regidx_end = VEPU1_REG_END_INDEX,
 	.regidx_en = VEPU1_REG_ENC_EN_INDEX,
@@ -383,6 +385,7 @@ static int vepu_debugfs_init(struct mpp_dev *mpp)
 
 static int vepu_init(struct mpp_dev *mpp)
 {
+	struct mpp_hw_info *hw_info;
 	struct vepu_dev *enc = to_vepu_dev(mpp);
 
 	mpp->grf_info = &mpp->srv->grf_infos[MPP_DRIVER_VEPU1];
@@ -409,6 +412,10 @@ static int vepu_init(struct mpp_dev *mpp)
 		enc->rst_h = NULL;
 	}
 
+	/* read hardware id*/
+	hw_info = mpp->var->hw_info;
+	hw_info->hw_id = mpp_read(mpp, hw_info->regidx_id);
+
 	return 0;
 }