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drm/rockchip: vop: move 1to4 reg configs to vo0_grf domain

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For rk3576, vopl supports eDP/HDMI/MIPI by the 1to4
module, which can transfer 1 pixle/cycle data from
vopl to 4 pixle/cycle data for HDMI/MIPI controllers.

Change-Id: I0da688d53c92a93e55778da2cce17596a22f540e
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
This commit is contained in:
Damon Ding
2024-01-29 10:27:11 +08:00
committed by Tao Huang
parent ba3a77c3b7
commit 2a859346b0
4 changed files with 47 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@@ -263,6 +263,7 @@ struct vop {
uint32_t *regsbak;
void __iomem *regs;
struct regmap *grf;
struct regmap *vo0_grf;
/* physical map length of vop register */
uint32_t len;
@@ -3575,13 +3576,25 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
VOP_CTRL_SET(vop, edp_en, 1);
VOP_CTRL_SET(vop, edp_pin_pol, val);
VOP_CTRL_SET(vop, edp_dclk_pol, dclk_inv);
VOP_CTRL_SET(vop, inf_out_en, 1);
VOP_GRF_SET(vop, vo0_grf, grf_edp_ch_sel, 1);
break;
case DRM_MODE_CONNECTOR_HDMIA:
VOP_CTRL_SET(vop, hdmi_en, 1);
VOP_CTRL_SET(vop, hdmi_pin_pol, val);
VOP_CTRL_SET(vop, hdmi_dclk_pol, 1);
VOP_CTRL_SET(vop, inf_out_en, 1);
VOP_GRF_SET(vop, vo0_grf, grf_hdmi_ch_sel, 1);
VOP_GRF_SET(vop, vo0_grf, grf_hdmi_pin_pol, val);
VOP_GRF_SET(vop, vo0_grf, grf_hdmi_1to4_en, val);
break;
case DRM_MODE_CONNECTOR_DSI:
/*
* RK3576 DSI CTRL hsync/vsync polarity is positive and can't update,
* so set VOP hsync/vsync polarity as positive by default.
*/
if (vop->version == VOP_VERSION(2, 0xd))
val = BIT(HSYNC_POSITIVE) | BIT(VSYNC_POSITIVE);
VOP_CTRL_SET(vop, mipi_en, 1);
VOP_CTRL_SET(vop, mipi_pin_pol, val);
VOP_CTRL_SET(vop, mipi_dclk_pol, dclk_inv);
@@ -3590,6 +3603,11 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
VOP_CTRL_SET(vop, data01_swap,
!!(s->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) ||
vop->dual_channel_swap);
VOP_CTRL_SET(vop, inf_out_en, 1);
VOP_GRF_SET(vop, vo0_grf, grf_mipi_ch_sel, 1);
VOP_GRF_SET(vop, vo0_grf, grf_mipi_mode, 1);
VOP_GRF_SET(vop, vo0_grf, grf_mipi_pin_pol, val);
VOP_GRF_SET(vop, vo0_grf, grf_mipi_1to4_en, 1);
break;
case DRM_MODE_CONNECTOR_DisplayPort:
VOP_CTRL_SET(vop, dp_dclk_pol, 0);
@@ -5256,6 +5274,7 @@ static int vop_bind(struct device *dev, struct device *master, void *data)
}
vop->grf = syscon_regmap_lookup_by_phandle_optional(dev->of_node, "rockchip,grf");
vop->vo0_grf = syscon_regmap_lookup_by_phandle_optional(dev->of_node, "rockchip,vo0-grf");
vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
if (IS_ERR(vop->hclk)) {

16
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -432,8 +432,6 @@ struct vop_ctrl {
/* ebc vop */
struct vop_reg enable;
struct vop_reg inf_out_en;
struct vop_reg mipi_1to4_en;
struct vop_reg hdmi_1to4_en;
struct vop_reg out_dresetn;
};
@@ -1219,6 +1217,19 @@ struct vop_grf_ctrl {
struct vop_reg grf_hdmi0_pin_pol;
struct vop_reg grf_hdmi1_pin_pol;
struct vop_reg grf_vopl_sel;
/*
* For rk3576, vopl supports eDP/HDMI/MIPI by the 1to4
* module, which can transfer 1 pixle/cycle data from
* vopl to 4 pixle/cycle data for HDMI/MIPI controllers.
*/
struct vop_reg grf_edp_ch_sel;
struct vop_reg grf_hdmi_ch_sel;
struct vop_reg grf_mipi_ch_sel;
struct vop_reg grf_hdmi_pin_pol;
struct vop_reg grf_hdmi_1to4_en;
struct vop_reg grf_mipi_mode;
struct vop_reg grf_mipi_pin_pol;
struct vop_reg grf_mipi_1to4_en;
};
struct vop_data {
@@ -1230,6 +1241,7 @@ struct vop_data {
const struct vop_csc_table *csc_table;
const struct vop_hdr_table *hdr_table;
const struct vop_grf_ctrl *grf;
const struct vop_grf_ctrl *vo0_grf;
unsigned int win_size;
uint32_t version;
struct vop_rect max_input;

16
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@@ -2008,10 +2008,6 @@ static const struct vop_ctrl rk3576_lit_ctrl_data = {
.dclk_pol = VOP_REG(EBC_VOP_DSP_CTRL0, 0x1, 4),
.rgb_pin_pol = VOP_REG(EBC_VOP_DSP_CTRL0, 0x7, 5),
.standby = VOP_REG(EBC_VOP_DSP_CTRL0, 0x1, 15),
.mipi_1to4_en = VOP_REG(EBC_VOP_DSP_CTRL0, 0x1, 24),
.mipi_pin_pol = VOP_REG(EBC_VOP_DSP_CTRL0, 0x3, 25),
.hdmi_1to4_en = VOP_REG(EBC_VOP_DSP_CTRL0, 0x1, 28),
.hdmi_pin_pol = VOP_REG(EBC_VOP_DSP_CTRL0, 0x3, 29),
.out_dresetn = VOP_REG(EBC_VOP_DSP_CTRL0, 0x1, 31),
.dsp_interlace = VOP_REG(EBC_VOP_DSP_CTRL1, 0x1, 0),
@@ -2095,6 +2091,17 @@ static const struct vop_win_data rk3576_lit_win_data[] = {
.type = DRM_PLANE_TYPE_PRIMARY },
};
static const struct vop_grf_ctrl rk3576_lit_vo0_grf_ctrl = {
.grf_edp_ch_sel = VOP_REG(RK3576_VO0_GRF_SOC_CON9, 0x1, 10),
.grf_hdmi_ch_sel = VOP_REG(RK3576_VO0_GRF_SOC_CON9, 0x1, 9),
.grf_mipi_ch_sel = VOP_REG(RK3576_VO0_GRF_SOC_CON9, 0x1, 8),
.grf_hdmi_pin_pol = VOP_REG(RK3576_VO0_GRF_SOC_CON13, 0x3, 5),
.grf_hdmi_1to4_en = VOP_REG(RK3576_VO0_GRF_SOC_CON13, 0x1, 4),
.grf_mipi_mode = VOP_REG(RK3576_VO0_GRF_SOC_CON13, 0x1, 3),
.grf_mipi_pin_pol = VOP_REG(RK3576_VO0_GRF_SOC_CON13, 0x3, 1),
.grf_mipi_1to4_en = VOP_REG(RK3576_VO0_GRF_SOC_CON13, 0x1, 1),
};
static const struct vop_grf_ctrl rk3576_lit_grf_ctrl = {
.grf_dclk_inv = VOP_REG(RK3576_IOC_GRF_MISC_CON8, 0x1, 9),
.grf_vopl_sel = VOP_REG(RK3576_IOC_GRF_MISC_CON8, 0x1, 11),
@@ -2108,6 +2115,7 @@ static const struct vop_data rk3576_vop_lit = {
.max_output = {1920, 1920},
.ctrl = &rk3576_lit_ctrl_data,
.intr = &rk3576_lit_intr,
.vo0_grf = &rk3576_lit_vo0_grf_ctrl,
.grf = &rk3576_lit_grf_ctrl,
.win = rk3576_lit_win_data,
.win_size = ARRAY_SIZE(rk3576_lit_win_data),

2
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -1908,6 +1908,8 @@
#define EBC_VOP_INT_CLR 0x0164
#define EBC_VOP_INT_STATUS 0x0168
#define RK3576_VO0_GRF_SOC_CON9 0x0024
#define RK3576_VO0_GRF_SOC_CON13 0x0034
#define RK3576_IOC_GRF_MISC_CON8 0x6420
#endif /* _ROCKCHIP_VOP_REG_H */