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phy/rockchip: samsung-hdptx: add support for RBR and HBR pe/vs configurations in DP mode

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For RK3588/RK3576, eDP IP can support not only eDP v1.3 but also
DP v1.2.

According to the SI test result, the new RBR and HBR pe/vs
configurations can better meet the DP v1.2 signal specification
requirements.

Change-Id: I3dfc1facebe0bf5fb7bc1d35b9fd397aefa71948
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
This commit is contained in:
Damon Ding
2025-01-16 15:46:16 +08:00
committed by Tao Huang
parent 62667f80c0
commit 2aa5aff468
1 changed files with 69 additions and 2 deletions
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71
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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@@ -333,6 +333,7 @@ struct rockchip_hdptx_phy {
struct regmap *regmap;
struct regmap *grf;
u32 lane_polarity_invert[4];
bool dp_mode;
};
enum {
@@ -543,6 +544,62 @@ static struct tx_drv_ctrl tx_drv_ctrl_r432[4][4] = {
}
};
static struct tx_drv_ctrl tx_drv_ctrl_rbr_dp_mode[4][4] = {
/* voltage swing 0, pre-emphasis 0->3 */
{
{ 0x2, 0x0, 0x2, 0x2, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
{ 0x4, 0x3, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x7, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0xd, 0xb, 0x1, 0x1, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 1, pre-emphasis 0->2 */
{
{ 0x4, 0x0, 0x4, 0x4, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
{ 0x9, 0x5, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0xc, 0x9, 0x2, 0x2, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 2, pre-emphasis 0->1 */
{
{ 0x8, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
{ 0xc, 0x5, 0x3, 0x3, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 3, pre-emphasis 0 */
{
{ 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
}
};
static struct tx_drv_ctrl tx_drv_ctrl_hbr_dp_mode[4][4] = {
/* voltage swing 0, pre-emphasis 0->3 */
{
{ 0x2, 0x0, 0x1, 0x1, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
{ 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0x9, 0x8, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0xd, 0xc, 0x1, 0x1, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 1, pre-emphasis 0->2 */
{
{ 0x6, 0x1, 0x2, 0x2, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
{ 0xa, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
{ 0xc, 0x9, 0x2, 0x2, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 2, pre-emphasis 0->1 */
{
{ 0x9, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
{ 0xd, 0x6, 0x3, 0x3, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
},
/* voltage swing 3, pre-emphasis 0 */
{
{ 0xc, 0x1, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
}
};
/* pll configurations for link rate R216/R243/R324/R432 */
static const struct tx_pll_ctrl tx_pll_ctrl_extra[4] = {
{ 0x5a, 0x01, 0x32, 0x00, 0x00, 0x00, 0x01, 0x04, 0x0d, 0x1d }, /* R216 */
@@ -597,6 +654,10 @@ static int rockchip_grf_write(struct regmap *grf, unsigned int reg,
static int rockchip_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode,
int submode)
{
struct rockchip_hdptx_phy *hdptx = phy_get_drvdata(phy);
hdptx->dp_mode = (submode == PHY_SUBMODE_DP);
return 0;
}
@@ -651,7 +712,10 @@ static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx,
switch (dp->link_rate) {
case 1620:
ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]];
if (hdptx->dp_mode)
ctrl = &tx_drv_ctrl_rbr_dp_mode[dp->voltage[lane]][dp->pre[lane]];
else
ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]];
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
LN_TX_SER_40BIT_EN_RBR,
FIELD_PREP(LN_TX_SER_40BIT_EN_RBR, 0x1));
@@ -676,7 +740,10 @@ static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx,
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR, ctrl->tx_jeq_odd_ctrl));
break;
case 2700:
ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]];
if (hdptx->dp_mode)
ctrl = &tx_drv_ctrl_hbr_dp_mode[dp->voltage[lane]][dp->pre[lane]];
else
ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]];
regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44),
LN_TX_SER_40BIT_EN_HBR,
FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1));