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fixed: rk3288 pm clkgating pll pd

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This commit is contained in:
xxx
2014-03-22 22:12:44 +08:00
parent 3e7a8bc24e
commit 2b0c069273
7 changed files with 219 additions and 63 deletions
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20
arch/arm/boot/dts/rk3288-clocks.dtsi Normal file → Executable file
View File

@@ -180,6 +180,7 @@
compatible = "rockchip,rk-clock-regs";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0000 0x3ff>;
ranges;
/* PLL control regs */
@@ -2006,6 +2007,7 @@
"clk_acc_efuse", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0fff 0x0fff>;
#clock-cells = <1>;
};
@@ -2039,6 +2041,7 @@
"clk_uart2_div", "uart2_frac",
"clk_uart3_div", "uart3_frac";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
@@ -2070,6 +2073,7 @@
"clk_uart4_div", "uart4_frac",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x000f 0x000f>;
#clock-cells = <1>;
};
@@ -2103,6 +2107,7 @@
"clk_edp_24m", "clk_edp",
"clk_isp", "clk_isp_jpe";
rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
#clock-cells = <1>;
};
@@ -2137,6 +2142,7 @@
"reserved", "reserved", /*"g_clk_ddrphy0", "g_clk_ddrphy1",*/
"clk_jtag", "reserved"; /*"testclk_gate_en";*/
rockchip,suspend-clkgating-setting=<0x7000 0xf000>;
#clock-cells = <1>;
};
@@ -2168,6 +2174,7 @@
"g_hdmi_hdcp_clk", "g_ps2c_clk",
"usbphy_480m", "g_mipidsi_24m";
rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
#clock-cells = <1>;
};
@@ -2200,6 +2207,7 @@
"g_pclk_uart4", "g_pclk_i2c2",
"g_pclk_i2c3", "g_pclk_i2c4";
rockchip,suspend-clkgating-setting=<0x0003 0x0003>;
#clock-cells = <1>;
};
@@ -2232,6 +2240,7 @@
"g_h_emem_peri", "g_hclk_mem_peri",
"g_hclk_nandc0", "g_hclk_nandc1";
rockchip,suspend-clkgating-setting=<0x0c00 0xc000>;
#clock-cells = <1>;
};
@@ -2265,6 +2274,7 @@
"g_aclk_peri_mmu", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
#clock-cells = <1>;
};
@@ -2296,6 +2306,7 @@
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
@@ -2328,6 +2339,7 @@
"g_aclk_dmac1", "g_aclk_strc_sys",
"g_p_ddrupctl0", "g_pclk_publ0";
rockchip,suspend-clkgating-setting=<0xe0f0 0xe0f0>;
#clock-cells = <1>;
};
@@ -2360,6 +2372,7 @@
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0033 0x0033>;
#clock-cells = <1>;
};
@@ -2392,6 +2405,7 @@
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0ff1 0x0ff1>;
#clock-cells = <1>;
};
@@ -2424,6 +2438,7 @@
"g_clk_wifi", "aclk_hevc",
"clk_hevc_cabac", "clk_hevc_core";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
@@ -2456,6 +2471,7 @@
"g_p_alive_niu", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0xffff 0xffff>;
#clock-cells = <1>;
};
@@ -2488,6 +2504,7 @@
"g_aclk_vio1_niu", "g_aclk_vio2_niu",
"g_aclk_vip", "g_hclk_vip";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
@@ -2520,6 +2537,7 @@
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};
@@ -2552,6 +2570,7 @@
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x01f 0x01f>;
#clock-cells = <1>;
};
@@ -2585,6 +2604,7 @@
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0 0x0>;
#clock-cells = <1>;
};

5
arch/arm/boot/dts/rk3288.dtsi
View File

@@ -10,6 +10,7 @@
/ {
compatible = "rockchip,rk3288";
rockchip,sram = <&sram>;
interrupt-parent = <&gic>;
aliases {
@@ -1015,11 +1016,11 @@
rockchip_suspend {
rockchip,ctrbits = <
(0
// RKPM_CTR_PWR_DMNS
//|RKPM_CTR_PWR_DMNS
//|RKPM_CTR_GTCLKS
//|RKPM_CTR_PLLS
//|RKPM_CTR_SYSCLK_DIV
|RKPM_CTR_NORIDLE_MD
//|RKPM_CTR_NORIDLE_MD
)
>;
rockchip,pmic-gpios=<

7
arch/arm/mach-rockchip/pm-pie.c Executable file → Normal file
View File

@@ -59,8 +59,8 @@ void PIE_FUNC(rkpm_sram_printch_pie)(char byte)
if(DATA(pm_sram_ops).printch)
DATA(pm_sram_ops).printch(byte);
if (byte == '\n')
FUNC(rkpm_sram_printch_pie)('\r');
// if (byte == '\n')
//FUNC(rkpm_sram_printch_pie)('\r');
}
void PIE_FUNC(rkpm_sram_printhex_pie)(unsigned int hex)
@@ -129,6 +129,9 @@ void PIE_FUNC(rkpm_sram_suspend_arg)(void *arg)
}
static void rkpm_pie_init(void)
{
if(rockchip_pie_chunk)
{
rkpm_set_pie_info(kern_to_pie(rockchip_pie_chunk, &DATA(pm_sram_ops))
,fn_to_pie(rockchip_pie_chunk, &FUNC(rkpm_sram_suspend_arg)));
}
}

105
arch/arm/mach-rockchip/pm-rk3288.c Executable file → Normal file
View File

@@ -20,7 +20,7 @@
#include <linux/rockchip/iomap.h>
#include "pm.h"
//#define CPU 3288
#define CPU 3288
//#include "sram.h"
#include "pm-pie.c"
@@ -269,7 +269,10 @@ static u32 slp_uart_data[RK3288_UART_NUM][10];
if(b_addr==NULL || ch>=RK3288_UART_NUM)
return;
if(ch==2)
{
idx=RK3288_CLKGATE_PCLK_UART2;
b_addr=RK_DEBUG_UART_VIRT;
}
gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
@@ -1167,17 +1170,13 @@ static void gpio_get_dts_info(struct device_node *parent)
}
/*******************************clk gating config*******************************************/
#define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
#define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
static u32 clk_ungt_msk[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
static u32 clk_ungt_msk_1[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
static u32 clk_ungt_save[RK3288_CRU_CLKGATES_CON_CNT]; //first clk gating value saveing
@@ -1225,23 +1224,27 @@ void PIE_FUNC(gtclks_sram_resume)(void)
static void gtclks_suspend(void)
{
int i;
// rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
// ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
{
clk_ungt_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
//if(i!=4||i!=0)
CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
#if 0
rkpm_ddr_printch('\n');
rkpm_ddr_printhex(clk_ungt_save[i]);
rkpm_ddr_printch('-');
rkpm_ddr_printhex(clk_ungt_msk[i]);
rkpm_ddr_printch('-');
rkpm_ddr_printhex(cru_readl(RK3188_CRU_CLKGATES_CON(i))) ;
if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
clk_ungt_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
//if(RK3288_CRU_CLKGATES_CON(i)<0x170||RK3288_CRU_CLKGATES_CON(i)>0x194)
{
CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
}
#if 0
rkpm_ddr_printch('\n');
#endif
rkpm_ddr_printhex(RK3288_CRU_CLKGATES_CON(i));
rkpm_ddr_printch('-');
rkpm_ddr_printhex(clk_ungt_msk[i]);
rkpm_ddr_printch('-');
rkpm_ddr_printhex(cru_readl(RK3288_CRU_CLKGATES_CON(i))) ;
if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
rkpm_ddr_printch('\n');
#endif
}
}
@@ -1251,8 +1254,10 @@ static void gtclks_resume(void)
int i;
for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
{
cru_writel(clk_ungt_save[i]|0xffff0000,RK3288_CRU_CLKGATES_CON(i));
cru_writel(clk_ungt_save[i]|0xffff0000,RK3288_CRU_CLKGATES_CON(i));
}
//rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
// ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
}
/********************************pll power down***************************************/
@@ -1327,8 +1332,12 @@ static inline void plls_resume(u32 pll_id)
{
u32 pllcon0, pllcon1, pllcon2;
if(plls_con3_save[pll_id]||RK3288_PLL_PWR_DN_MSK)
return ;
// rkpm_ddr_printascii("ddr");
// rkpm_ddr_printhex(pll_id);
if(!(plls_con3_save[pll_id]&&RK3288_PLL_PWR_DN_MSK))
return ;
//rkpm_ddr_printascii("res\n");
//enter slowmode
cru_writel(RK3288_PLL_MODE_SLOW(pll_id), RK3288_CRU_MODE_CON);
@@ -1362,6 +1371,11 @@ static u32 clk_sel0,clk_sel1, clk_sel10,clk_sel26,clk_sel36, clk_sel37;
static void pm_plls_suspend(void)
{
//rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
//rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
//rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
clk_sel0=cru_readl(RK3288_CRU_CLKSELS_CON(0));
clk_sel1=cru_readl(RK3288_CRU_CLKSELS_CON(1));
clk_sel10=cru_readl(RK3288_CRU_CLKSELS_CON(10));
@@ -1445,6 +1459,10 @@ static void pm_plls_resume(void)
plls_resume(NPLL_ID);
cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
//rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
// rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
//rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
}
static __sramdata u32 sysclk_clksel0_con,sysclk_clksel1_con,sysclk_clksel10_con,sysclk_mode_con;
@@ -1495,19 +1513,23 @@ void PIE_FUNC(sysclk_resume)(u32 sel_clk)
static void clks_gating_suspend_init(void)
{
// get clk gating info
p_rkpm_clkgt_last_set= kern_to_pie(rockchip_pie_chunk, &DATA(rkpm_clkgt_last_set[0]));
if(rockchip_pie_chunk)
p_rkpm_clkgt_last_set= kern_to_pie(rockchip_pie_chunk, &DATA(rkpm_clkgt_last_set[0]));
else
p_rkpm_clkgt_last_set=&clk_ungt_msk_1[0];
if(clk_suspend_clkgt_info_get(clk_ungt_msk,p_rkpm_clkgt_last_set, RK3288_CRU_CLKGATES_CON_CNT)
==RK3188_CRU_CLKGATES_CON(0))
==RK3288_CRU_CLKGATES_CON(0))
{
rkpm_set_ops_gtclks(gtclks_suspend,gtclks_resume);
rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_suspend)),
fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_resume)));
if(rockchip_pie_chunk)
rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_suspend)),
fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_resume)));
PM_LOG("%s:clkgt info ok\n",__FUNCTION__);
}
rkpm_set_sram_ops_sysclk(fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_suspend))
if(rockchip_pie_chunk)
rkpm_set_sram_ops_sysclk(fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_suspend))
,fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_resume)));
}
@@ -1577,12 +1599,12 @@ static void rkpm_prepare(void)
// rkpm_ddr_printhex(temp);
#endif
// dump GPIO INTEN for debug
//rk30_pm_dump_inten();
rk30_pm_dump_inten();
}
static void rkpm_finish(void)
{
//rk30_pm_dump_irq();
rk30_pm_dump_irq();
}
@@ -1625,21 +1647,18 @@ static void __init rk3288_suspend_init(void)
return ;
}
PM_LOG("%s: pm_ctrbits =%x\n",__FUNCTION__,pm_ctrbits);
#if 0
if(of_property_read_u32_array(parent,"rockchip,pmic-gpios",gpios_data,ARRAY_SIZE(gpios_data)))
{
PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
return ;
}
#endif
rkpm_set_ctrbits(pm_ctrbits);
clks_gating_suspend_init();
rkpm_set_ops_plls(pm_plls_suspend,pm_plls_resume);
//rkpm_set_ops_prepare_finish(rkpm_prepare,rkpm_finish);
// rkpm_set_ops_regs_pread(interface_ctr_reg_pread);
rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk, &FUNC(sram_printch)));
rkpm_set_ops_plls(pm_plls_suspend,pm_plls_resume);
rkpm_set_ops_prepare_finish(rkpm_prepare,rkpm_finish);
//rkpm_set_ops_regs_pread(interface_ctr_reg_pread);
if(rockchip_pie_chunk)
rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk, &FUNC(sram_printch)));
rkpm_set_ops_printch(ddr_printch);
}

28
arch/arm/mach-rockchip/pm.c Executable file → Normal file
View File

@@ -16,12 +16,20 @@ void rkpm_ddr_reg_offset_dump(void __iomem * base_addr,u32 _offset)
void rkpm_ddr_regs_dump(void __iomem * base_addr,u32 start_offset,u32 end_offset)
{
u32 i;
u32 line=0;
rkpm_ddr_printascii("start from:");
rkpm_ddr_printhex((u32)(base_addr +start_offset));
rkpm_ddr_printch('\n');
for(i=start_offset;i<=end_offset;)
{
rkpm_ddr_printhex(readl_relaxed((void *)(base_addr + i)));
if((i!=0&!(i%6))||i==end_offset)
rkpm_ddr_printch('\n');
rkpm_ddr_printhex(readl_relaxed((base_addr + i)));
line++;
if((line%4==0)||i==end_offset)
rkpm_ddr_printch('\n');
else
rkpm_ddr_printch('-');
i+=4;
}
@@ -318,9 +326,8 @@ void rkpm_ddr_printch(char byte)
{
if(pm_ops.printch)
pm_ops.printch(byte);
if (byte == '\n')
rkpm_ddr_printch('\r');
//if (byte == '\n')
//rkpm_ddr_printch('\r');
}
void rkpm_ddr_printascii(const char *s)
{
@@ -403,8 +410,13 @@ static int rkpm_enter(suspend_state_t state)
pm_log = false;
if(rkpm_chk_jdg_ctrbit(RKPM_CTR_NORIDLE_MD))
if(rkpm_chk_jdg_ctrbit(RKPM_CTR_NORIDLE_MD)&&p_suspend_pie_cb)
call_with_stack(p_suspend_pie_cb,&rkpm_jdg_sram_ctrbits, rockchip_sram_stack);
else
{
dsb();
wfi();
}
pm_log = true;

12
arch/arm/mach-rockchip/pm.h Executable file → Normal file
View File

@@ -1,5 +1,5 @@
#ifndef __MACH_ROCKCHIP_PM1_H
#define __MACH_ROCKCHIP_PM1_H
#ifndef __MACH_ROCKCHIP_PM_H
#define __MACH_ROCKCHIP_PM_H
#include <dt-bindings/suspend/rockchip-pm.h>
@@ -91,10 +91,16 @@ struct rkpm_gpios_info_st{
#define reg_readl(base) readl_relaxed(base)
#define reg_writel(v, base) do { writel_relaxed(v, base); dsb(); } while (0)
#if 0
#define PM_ERR(fmt, args...) printk(KERN_ERR fmt, ##args)
#define PM_LOG(fmt, args...) printk(KERN_ERR fmt, ##args)
#define PM_WARNING(fmt, args...) printk(KERN_WARNING fmt, ##args)
#else
#define PM_ERR(fmt, args...) printk(fmt, ##args)
#define PM_LOG(fmt, args...) printk(fmt, ##args)
#define PM_WARNING(fmt, args...) printk(fmt, ##args)
#endif
/*********************************pm control******************************************/
extern void rkpm_ddr_reg_offset_dump(void __iomem * base_addr,u32 _offset);

105
arch/arm/mach-rockchip/rk3288.c Executable file → Normal file
View File

@@ -388,17 +388,112 @@ static int __init rk3288_pie_init(void)
rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk, &__pie_common_start[0]);
rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk, (char *) DATA(sram_stack) + sizeof(DATA(sram_stack)));
return 0;
}
arch_initcall(rk3288_pie_init);
#ifdef CONFIG_PM
#include "pm-rk3288.c"
int rk3288_sys_set_power_domain(enum pmu_power_domain pd, bool on)
{
u32 clks_ungating[RK3288_CRU_CLKGATES_CON_CNT];
u32 clks_save[RK3288_CRU_CLKGATES_CON_CNT];
u32 i,ret;
for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
{
clks_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
clks_ungating[i]=0;
}
switch(pd)
{
case PD_GPU:
clks_ungating[5]=0x1<<7;
break;
case PD_VIDEO:
clks_ungating[3]=0x1<<11|0x1<<10|0x1<<9;
break;
case PD_VIO:
clks_ungating[3]=0x1<<0|0x1<<2|0x1<<5|0x1<<4|0x1<<1|0x1<<3|0x1<<12|0x1<<13
|0x1<<14|0x1<<15|0x1<<12|0x1<<11;
break;
case PD_HEVC:
clks_ungating[13]=0x1<<15|0x1<<14|0x1<<13;
break;
#if 0
case PD_CS:
clks_ungating[12]=0x1<<11|0x1<10|0x1<<9|0x1<<8;
break;
#endif
default:
break;
}
for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
{
if(clks_ungating[i])
cru_writel(clks_ungating[i]<<16,RK3288_CRU_CLKGATES_CON(i));
}
ret=rk3288_pmu_set_power_domain(pd,on);
for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
{
if(clks_ungating[i])
cru_writel(clks_save[i]|0xffff0000,RK3288_CRU_CLKGATES_CON(i));
}
return ret;
}
static u32 rk_pmu_pwrdn_st;
static inline void rk_pm_soc_pd_suspend(void)
{
rk_pmu_pwrdn_st = pmu_readl(RK3288_PMU_PWR_STATE);
if(!(rk_pmu_pwrdn_st&BIT(pmu_pd_map[IDLE_REQ_GPU])))
rk3288_sys_set_power_domain(IDLE_REQ_GPU, false);
if(!(rk_pmu_pwrdn_st&BIT(pmu_pd_map[IDLE_REQ_HEVC])))
rk3288_sys_set_power_domain(IDLE_REQ_HEVC, false);
if(!(rk_pmu_pwrdn_st&BIT(pmu_pd_map[IDLE_REQ_VIO])))
rk3288_sys_set_power_domain(IDLE_REQ_VIO, false);
if(!(rk_pmu_pwrdn_st&BIT(pmu_pd_map[IDLE_REQ_VIDEO])))
rk3288_sys_set_power_domain(IDLE_REQ_VIDEO, false);
rkpm_ddr_printascii("pd state:");
rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWR_STATE));
rkpm_ddr_printascii("\n");
}
static inline void rk_pm_soc_pd_resume(void)
{
if(!(rk_pmu_pwrdn_st&BIT(pmu_pd_map[IDLE_REQ_GPU])))
rk3288_sys_set_power_domain(IDLE_REQ_GPU, false);
if(!(rk_pmu_pwrdn_st&BIT(pmu_pd_map[IDLE_REQ_HEVC])))
rk3288_sys_set_power_domain(IDLE_REQ_HEVC, false);
if(!(rk_pmu_pwrdn_st&BIT(pmu_pd_map[IDLE_REQ_VIO])))
rk3288_sys_set_power_domain(IDLE_REQ_VIO, false);
if(!(rk_pmu_pwrdn_st&BIT(pmu_pd_map[IDLE_REQ_VIDEO])))
rk3288_sys_set_power_domain(IDLE_REQ_VIDEO, false);
rkpm_ddr_printascii("pd state:");
rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWR_STATE));
rkpm_ddr_printascii("\n");
}
//extern bool console_suspend_enabled;
static void __init rk3288_init_suspend(void)
{
return;
rockchip_suspend_init();
rkpm_pie_init();
rk3288_suspend_init();
return;
printk("%s\n",__FUNCTION__);
rockchip_suspend_init();
//rkpm_pie_init();
rk3288_suspend_init();
// rkpm_set_ops_pwr_dmns(rk_pm_soc_pd_suspend,rk_pm_soc_pd_resume);
//console_suspend_enabled=0;
//pm_suspend(PM_SUSPEND_MEM);
}
#endif