Documentation: dt: add bindings for rockchip-cpufreq

Add the device tree bindings document for ROCKCHIP CPUFreq driver.
The operating-points-v2 binding allows us to provide an opp-supported-hw
property for each OPP to define when it is available and an
opp-microvolt-<name> property to choose a suitable voltage for OPP.

This driver reads SoC version and leakage values from eFuse and
provides them as matching data to the opp framework.

Change-Id: I10f959edd46668bedf3be4835bb5ec63e089808d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

Documentation/devicetree/bindings/cpufreq/cpufreq-rockchip.txt

@@ -0,0 +1,50 @@
+Binding for Rockchip's CPUFreq driver
+===============================
+
+Rockchip's CPUFreq driver attempts to read SoC version and leakage values
+from eFuse, then supplies the OPP framework with 'prop' and 'supported
+hardware' information respectively. This is based on operating-points-v2,
+but the driver can also create the "cpufreq-dt" platform_device to
+compatibility with operating-points.
+
+For more information about the expected DT format [See: ../opp/opp.txt].
+
+Optional properties:
+In 'operating-points-v2' table:
+- leakage-voltage-sel: The property is an array of 3-tuples items, and
+               each item consists of leakage and voltage selector like
+               <min-leakage max-leakage volt-selector>.
+               min-leakage: minimum leakage in mA, ranges from 1 to 254
+               max-leakage: maximum leakage in mA, ranges from 1 to 254
+               voltage-selector: a sequence number which is used to math
+               opp-microvolt-L<number> roperty in OPP node
+- nvmem-cells: A phandle to the soc_version and cpu_leakage data provided
+               by a nvmem device.
+- nvmem-cell-names: Should be "soc_version" and "cpu_leakage"
+
+Examples:
+
+cpus {
+	cpu@0 {
+		operating-points-v2 = <&cluster0_opp>;
+	};
+}
+
+cluster0_opp: opp_table0 {
+	compatible = "operating-points-v2";
+	opp-shared;
+	leakage-voltage-sel = <
+		1   24   0
+		25  254  1
+	>;
+	nvmem-cells = <&cpu_leakage>;
+	nvmem-cell-names = "cpu_leakage";
+
+	opp@216000000 {
+		opp-hz = /bits/ 64 <216000000>;
+		opp-microvolt = <950000 950000 1350000>;
+		opp-microvolt-L0 = <1050000 1050000 1350000>;
+		opp-microvolt-L1 = <950000 950000 1350000>;
+		opp-suspend;
+	}
+};