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hdr: fix g12a hlg function no effect

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PD#161765: hdr: fix hlg function no effect

1. adjust g12a hdr code structure
2. fix hlg function no effect
3. optimize hdr effect

Change-Id: I954b29fbfea6cc8c45c1624af1cab0190ee2af3f
Signed-off-by: MingLiang Dong <mingliang.dong@amlogic.com>
This commit is contained in:
MingLiang Dong
2018-06-07 11:43:48 +08:00
committed by Yixun Lan
parent 43844952aa
commit 2c3038de4a
6 changed files with 499 additions and 521 deletions
Download Patch File Download Diff File Expand all files Collapse all files

114
drivers/amlogic/media/enhancement/amvecm/amcsc.c
View File

@@ -4324,6 +4324,12 @@ static int hdr_process(
};
int i, j;
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
hdr_func(VD1_HDR, HDR_SDR);
hdr_func(OSD1_HDR, HDR_BYPASS);
return need_adjust_contrast_saturation;
}
if (master_info->present_flag & 1) {
pr_csc("\tMaster_display_colour available.\n");
print_primaries_info(master_info);
@@ -4553,6 +4559,12 @@ static int hlg_process(
};
int i, j;
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
hdr_func(VD1_HDR, HDR_SDR);
hdr_func(OSD1_HDR, HDR_BYPASS);
return need_adjust_contrast_saturation;
}
if (master_info->present_flag & 1) {
pr_csc("\tMaster_display_colour available.\n");
print_primaries_info(master_info);
@@ -4765,6 +4777,17 @@ static void bypass_hdr_process(
EOTF_COEFF_RIGHTSHIFT
};
int i, j;
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
hdr_func(VD1_HDR, HDR_BYPASS);
if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) &&
((vinfo->hdr_info.hdr_support & 0xc) &&
(vinfo->viu_color_fmt != COLOR_FMT_RGB444)))
hdr_func(OSD1_HDR, SDR_HDR);
else
hdr_func(OSD1_HDR, HDR_BYPASS);
return;
}
/*vpp matrix mux read*/
vpp_set_mtx_en_read();
if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) {
@@ -5379,6 +5402,11 @@ static void hlg_hdr_process(
};
int i, j;
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
hdr_func(VD1_HDR, HLG_HDR);
hdr_func(OSD1_HDR, SDR_HDR);
return;
}
/*vpp matrix mux read*/
vpp_set_mtx_en_read();
if ((get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB)
@@ -5615,9 +5643,12 @@ static void sdr_hdr_process(
struct vinfo_s *vinfo,
struct vframe_master_display_colour_s *master_info)
{
if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXL) ||
(get_cpu_type() == MESON_CPU_MAJOR_ID_GXM) ||
(get_cpu_type() == MESON_CPU_MAJOR_ID_GXLX)) {
if (vinfo->viu_color_fmt != COLOR_FMT_RGB444) {
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
hdr_func(VD1_HDR, SDR_HDR);
hdr_func(OSD1_HDR, SDR_HDR);
return;
}
/*vpp matrix mux read*/
vpp_set_mtx_en_read();
/* OSD convert to 709 limited to match SDR video */
@@ -5701,10 +5732,8 @@ static void sdr_hdr_process(
CSC_ON);
/*vpp matrix mux write*/
vpp_set_mtx_en_write();
} else if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB) ||
(get_cpu_type() == MESON_CPU_MAJOR_ID_TXL)) {
} else
bypass_hdr_process(csc_type, vinfo, master_info);
}
}
static int vpp_eye_protection_process(
@@ -6056,16 +6085,12 @@ static int vpp_matrix_update(
if (get_hdr_type() & HLG_FLAG)
need_adjust_contrast_saturation =
hlg_process(csc_type, vinfo, p);
else {
if (get_cpu_type() ==
MESON_CPU_MAJOR_ID_G12A) {
hdr2sdr_func(VD1_HDR);
hdrbypass_func(OSD1_HDR);
} else
need_adjust_contrast_saturation
= hdr_process(csc_type,
vinfo, p);
}
else
need_adjust_contrast_saturation
= hdr_process(csc_type, vinfo, p);
pr_csc("hdr_process_mode = 0x%x\n"
"hlg_process_mode = 0x%x.\n",
hdr_process_mode, hlg_process_mode);
}
} else if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) &&
(hdr_process_mode == 0) &&
@@ -6085,6 +6110,9 @@ static int vpp_matrix_update(
hlg_hdr_process(csc_type, vinfo, p);
else
bypass_hdr_process(csc_type, vinfo, p);
pr_csc("hdr_process_mode = 0x%x\n"
"hlg_process_mode = 0x%x.\n",
hdr_process_mode, hlg_process_mode);
}
} else if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) &&
(hdr_process_mode == 1) && (hlg_process_mode == 0)) {
@@ -6104,6 +6132,9 @@ static int vpp_matrix_update(
else
need_adjust_contrast_saturation =
hdr_process(csc_type, vinfo, p);
pr_csc("hdr_process_mode = 0x%x\n"
"hlg_process_mode = 0x%x.\n",
hdr_process_mode, hlg_process_mode);
}
} else if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) &&
(hdr_process_mode == 0) && (hlg_process_mode == 0)) {
@@ -6117,44 +6148,36 @@ static int vpp_matrix_update(
SIG_HLG_MODE)) ||
(cur_csc_type <
VPP_MATRIX_BT2020YUV_BT2020RGB)) {
if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) {
hdrbypass_func(VD1_HDR);
hdrbypass_func(OSD1_HDR);
} else
bypass_hdr_process(csc_type, vinfo, p);
bypass_hdr_process(csc_type, vinfo, p);
pr_csc("bypass_hdr_process: 0x%x, 0x%x.\n",
hdr_process_mode, hlg_process_mode);
}
} else {
if ((csc_type < VPP_MATRIX_BT2020YUV_BT2020RGB) &&
sdr_process_mode) {
if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) {
sdr2hdr_func(VD1_HDR);
sdr2hdr_func(OSD1_HDR);
} else
sdr_process_mode)
/* for gxl and gxm SDR to HDR process */
sdr_hdr_process(csc_type, vinfo, p);
} else {
if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) {
hdrbypass_func(VD1_HDR);
hdrbypass_func(OSD1_HDR);
} else {
else {
/* for gxtvbb and gxl HDR bypass process */
if (((vinfo->hdr_info.hdr_support &
HDR_SUPPORT) ||
(vinfo->hdr_info.hdr_support &
HLG_SUPPORT)) &&
(csc_type <
VPP_MATRIX_BT2020YUV_BT2020RGB)
&& tx_op_color_primary)
set_bt2020csc_process(csc_type,
vinfo, p);
else
bypass_hdr_process(csc_type,
vinfo, p);
}
if (((vinfo->hdr_info.hdr_support &
HDR_SUPPORT) ||
(vinfo->hdr_info.hdr_support &
HLG_SUPPORT)) &&
(csc_type <
VPP_MATRIX_BT2020YUV_BT2020RGB)
&& tx_op_color_primary)
set_bt2020csc_process(csc_type,
vinfo, p);
else
bypass_hdr_process(csc_type,
vinfo, p);
pr_csc("csc_type = 0x%x\n"
"sdr_process_mode = 0x%x.\n",
csc_type, sdr_process_mode);
}
}
if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) {
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
if (vinfo->viu_color_fmt != COLOR_FMT_RGB444)
mtx_setting(POST2_MTX, MATRIX_NULL, MTX_OFF);
else
@@ -6342,6 +6365,7 @@ int amvecm_matrix_process(
CSC_FLAG_CHECK_OUTPUT);
last_vf = NULL;
fg_vf_sw_dbg = 4;
dbg_vf = NULL;
}
if (null_vf_cnt <= null_vf_max)
null_vf_cnt++;

10
drivers/amlogic/media/enhancement/amvecm/amcsc.h
View File

@@ -131,16 +131,6 @@ extern int tx_op_color_primary;
extern int amvecm_matrix_process(
struct vframe_s *vf, struct vframe_s *vf_rpt, int flags);
extern int amvecm_hdr_dbg(u32 sel);
#ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
#define VSYNC_WR_MPEG_REG(adr, val) WRITE_VPP_REG(adr, val)
#define VSYNC_RD_MPEG_REG(adr) READ_VPP_REG(adr)
#define VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \
WRITE_VPP_REG_BITS(adr, val, start, len)
#else
extern int VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len);
extern u32 VSYNC_RD_MPEG_REG(u32 adr);
extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val);
#endif
extern u32 get_video_enabled(void);
extern void get_hdr_source_type(void);

3
drivers/amlogic/media/enhancement/amvecm/amvecm.c
View File

@@ -1048,9 +1048,6 @@ static long amvecm_ioctl(struct file *file,
struct ve_pq_table_s *vpp_pq_load_table = NULL;
int i = 0;
i = sizeof(struct ve_pq_load_s);
pr_info("sizeof(struct ve_pq_load_s) = %d", i);
pr_amvecm_dbg("[amvecm..] %s: cmd_nr = 0x%x\n",
__func__, _IOC_NR(cmd));

867
drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.c
View File

File diff suppressed because it is too large Load Diff

15
drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.h
View File

@@ -58,9 +58,13 @@ enum hdr_lut_sel {
};
enum hdr_process_sel {
HDR_SDR = 0x1,
SDR_HDR = 0x2,
HDR_BYPASS = 0x4,
HDR_BYPASS = 0x1,
HDR_SDR = 0x2,
SDR_HDR = 0x4,
HLG_BYPASS = 0x8,
HLG_SDR = 0x10,
HLG_HDR = 0x20,
HDRPLUS_SDR = 0x40,
HDR_p_MAX
};
@@ -103,9 +107,8 @@ typedef int64_t(*MenuFun)(int64_t);
void eotf_float_gen(int64_t *o_out, MenuFun eotf);
void oetf_float_gen(int64_t *bin_e, MenuFun oetf);
void nolinear_lut_gen(int64_t *bin_c, MenuFun cgain);
extern void hdrbypass_func(enum hdr_module_sel module_sel);
extern void hdr2sdr_func(enum hdr_module_sel module_sel);
extern void sdr2hdr_func(enum hdr_module_sel module_sel);
extern void hdr_func(enum hdr_module_sel module_sel,
enum hdr_process_sel hdr_process_select);
/*G12A vpp matrix*/
enum vpp_matrix_e {
VD1_MTX = 0x1,

11
include/linux/amlogic/media/amvecm/amvecm.h
View File

@@ -326,5 +326,16 @@ extern int metadata_read_u32(uint32_t *value);
extern int metadata_wait(struct vframe_s *vf);
extern int metadata_sync(uint32_t frame_id, uint64_t pts);
extern void amvecm_wakeup_queue(void);
#ifndef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA
#define VSYNC_WR_MPEG_REG(adr, val) WRITE_VPP_REG(adr, val)
#define VSYNC_RD_MPEG_REG(adr) READ_VPP_REG(adr)
#define VSYNC_WR_MPEG_REG_BITS(adr, val, start, len) \
WRITE_VPP_REG_BITS(adr, val, start, len)
#else
extern int VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len);
extern u32 VSYNC_RD_MPEG_REG(u32 adr);
extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val);
#endif
#endif /* AMVECM_H */