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video: sr: add the missing bit mask for sr core1 [1/1]
PD#SWPL-2948 Problem: Miss the sr core1 bit mask to cause display abnormal Solution: Add the bit mask for sr core1 Verify: Test pass by x301 Change-Id: I742d86b610a9748adad7c143d7a85c6796d3c8f7 Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
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@@ -6426,7 +6426,7 @@ SET_FILTER:
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VPP_VD1_POSTBLEND |
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VPP_PREBLEND_EN |
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VPP_POSTBLEND_EN |
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7);
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0xf);
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vpp_misc_save &=
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((1 << 29) | VPP_CM_ENABLE |
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(0x1ff << VPP_VD2_ALPHA_BIT) |
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@@ -6436,7 +6436,7 @@ SET_FILTER:
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VPP_VD1_POSTBLEND |
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VPP_PREBLEND_EN |
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VPP_POSTBLEND_EN |
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7);
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0xf);
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if (vpp_misc_set != vpp_misc_save) {
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/* vd1 need always enable pre bld */
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if (vpp_misc_set & VPP_VD1_POSTBLEND)
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