video: sr: add the missing bit mask for sr core1 [1/1]

PD#SWPL-2948

Problem:
Miss the sr core1 bit mask to cause display abnormal

Solution:
Add the bit mask for sr core1

Verify:
Test pass by x301

Change-Id: I742d86b610a9748adad7c143d7a85c6796d3c8f7
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
This commit is contained in:
Brian Zhu
2018-12-07 14:21:43 +08:00
committed by Dongjin Kim
parent b5771273c2
commit 2c9dae4eb4

View File

@@ -6426,7 +6426,7 @@ SET_FILTER:
VPP_VD1_POSTBLEND |
VPP_PREBLEND_EN |
VPP_POSTBLEND_EN |
7);
0xf);
vpp_misc_save &=
((1 << 29) | VPP_CM_ENABLE |
(0x1ff << VPP_VD2_ALPHA_BIT) |
@@ -6436,7 +6436,7 @@ SET_FILTER:
VPP_VD1_POSTBLEND |
VPP_PREBLEND_EN |
VPP_POSTBLEND_EN |
7);
0xf);
if (vpp_misc_set != vpp_misc_save) {
/* vd1 need always enable pre bld */
if (vpp_misc_set & VPP_VD1_POSTBLEND)