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clk: rockchip: add register offset of the cores select parent

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The cores select parent register is special on RK3588.

Change-Id: I1cfd07064ae7092030a6b9d234049e6cf07a23e8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2021-05-07 17:19:03 +08:00
parent 7af20071ed
commit 2d49bdb0be
2 changed files with 23 additions and 8 deletions
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28
drivers/clk/rockchip/clk-cpu.c
View File

@@ -176,10 +176,16 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
rockchip_boost_add_core_div(cpuclk->pll_hw, alt_prate);
/* select alternate parent */
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
reg_data->mux_core_mask,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->core_reg[0]);
if (reg_data->mux_core_reg)
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
reg_data->mux_core_mask,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->mux_core_reg);
else
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
reg_data->mux_core_mask,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->core_reg[0]);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
@@ -212,10 +218,16 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
* primary parent by the extra dividers that were needed for the alt.
*/
writel(HIWORD_UPDATE(reg_data->mux_core_main,
reg_data->mux_core_mask,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->core_reg[0]);
if (reg_data->mux_core_reg)
writel(HIWORD_UPDATE(reg_data->mux_core_main,
reg_data->mux_core_mask,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->mux_core_reg);
else
writel(HIWORD_UPDATE(reg_data->mux_core_main,
reg_data->mux_core_mask,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->core_reg[0]);
/* remove dividers */
for (i = 0; i < reg_data->num_cores; i++) {

3
drivers/clk/rockchip/clk.h
View File

@@ -437,6 +437,8 @@ struct rockchip_cpuclk_rate_table {
* @div_core_shift[]: cores divider offset used to divide the pll value
* @div_core_mask[]: cores divider mask
* @num_cores: number of cpu cores
* @mux_core_reg: register offset of the cores select parent
* @mux_core_alt: mux value to select alternate parent
* @mux_core_main: mux value to select main parent of core
* @mux_core_shift: offset of the core multiplexer
* @mux_core_mask: core multiplexer mask
@@ -446,6 +448,7 @@ struct rockchip_cpuclk_reg_data {
u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];
u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];
int num_cores;
int mux_core_reg;
u8 mux_core_alt;
u8 mux_core_main;
u8 mux_core_shift;