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clk: rockchip: rk3288: add the condition of the call register_syscore_ops

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The pwm clk parent is GPLL,PWM clk not allowed to change freq,
so the GPLL not allowed change mode and freq  when pwm is used.
If have trust is need't rk3288_clk_suspend and rk3288_clk_resume.

Change-Id: I4845fda89d7ae7713e8c0e94747c3f4dfd140c6a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2018-05-08 09:34:12 +08:00
committed by Tao Huang
parent 2c55a33bc8
commit 2d64f3c03b
1 changed files with 4 additions and 1 deletions
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5
drivers/clk/rockchip/clk-rk3288.c
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@@ -19,6 +19,7 @@
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include "clk.h"
#include <asm/psci.h>
#define RK3288_GRF_SOC_CON(x) (0x244 + x * 4)
#define RK3288_GRF_SOC_STATUS1 0x284
@@ -981,7 +982,9 @@ static void __init rk3288_clk_init(struct device_node *np)
rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST,
rk3288_clk_shutdown);
register_syscore_ops(&rk3288_clk_syscore_ops);
if (!psci_smp_available())
register_syscore_ops(&rk3288_clk_syscore_ops);
rockchip_clk_of_add_provider(np, ctx);