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drm/rockchip: vop2: add support rk3588 gamma

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Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I6be46a12d73890c61578f1dae7a88b9cb4271dfb
This commit is contained in:
Sandy Huang
2021-11-11 09:27:35 +08:00
parent aabb8a69f7
commit 2d67ec5094
3 changed files with 12 additions and 3 deletions
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1
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -701,6 +701,7 @@ struct vop2_video_port_regs {
struct vop_reg edpi_wms_hold_en;
struct vop_reg edpi_te_en;
struct vop_reg edpi_wms_fs;
struct vop_reg gamma_update_en;
};
struct vop2_power_domain_regs {

8
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -2742,7 +2742,9 @@ static void vop2_crtc_load_lut(struct drm_crtc *crtc)
vp_enable_gamma_nr++;
}
if (vop2->data->nr_gammas && vp_enable_gamma_nr >= vop2->data->nr_gammas) {
if (vop2->data->nr_gammas &&
vp_enable_gamma_nr >= vop2->data->nr_gammas &&
vp->gamma_lut_active == false) {
DRM_INFO("only support %d gamma\n", vop2->data->nr_gammas);
return;
}
@@ -2755,13 +2757,14 @@ static void vop2_crtc_load_lut(struct drm_crtc *crtc)
#define CTRL_GET(name) VOP_MODULE_GET(vop2, vp, name)
readx_poll_timeout(CTRL_GET, dsp_lut_en, dle, !dle, 5, 33333);
VOP_CTRL_SET(vop2, gamma_port_sel, vp->id);
for (i = 0; i < vp->gamma_lut_len; i++)
vop2_write_lut(vop2, i << 2, vp->lut[i]);
spin_lock(&vop2->reg_lock);
VOP_MODULE_SET(vop2, vp, dsp_lut_en, 1);
VOP_CTRL_SET(vop2, gamma_port_sel, vp->id);
VOP_MODULE_SET(vop2, vp, gamma_update_en, 1);
vop2_cfg_done(crtc);
vp->gamma_lut_active = true;
@@ -5892,7 +5895,6 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
VOP_GRF_SET(vop2, grf, grf_hdmi0_en, 1);
VOP_GRF_SET(vop2, vo1_grf, grf_hdmi0_pin_pol, val);
VOP_CTRL_SET(vop2, hdmi0_en, 1);
VOP_CTRL_SET(vop2, hdmi0_en, 1);
VOP_CTRL_SET(vop2, hdmi0_mux, vp_data->id);
VOP_CTRL_SET(vop2, hdmi_pin_pol, val);

6
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -865,6 +865,7 @@ static const struct vop2_video_port_regs rk3588_vop_vp0_regs = {
.dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
.dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
.dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
.gamma_update_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 22),
.dsp_lut_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 28),
.standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
.dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 30),
@@ -952,6 +953,7 @@ static const struct vop2_video_port_regs rk3588_vop_vp1_regs = {
.dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
.dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18),
.dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20),
.gamma_update_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 22),
.dsp_lut_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 28),
.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
.dclk_core_div = VOP_REG(RK3568_VP1_CLK_CTRL, 0x3, 0),
@@ -1032,6 +1034,7 @@ static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
.dither_down_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 17),
.dither_down_sel = VOP_REG(RK3568_VP2_DSP_CTRL, 0x3, 18),
.dither_down_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 20),
.gamma_update_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 22),
.dsp_lut_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 28),
.standby = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31),
.dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 31),
@@ -1083,6 +1086,7 @@ static const struct vop2_video_port_regs rk3588_vop_vp3_regs = {
.dither_down_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 17),
.dither_down_sel = VOP_REG(RK3588_VP3_DSP_CTRL, 0x3, 18),
.dither_down_mode = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 20),
.gamma_update_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 22),
.dsp_lut_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 28),
.standby = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 31),
.dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 30),
@@ -2637,6 +2641,7 @@ static const struct vop2_ctrl rk3588_vop_ctrl = {
.rgb_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 3),
.dp0_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 8),
.dp1_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 12),
.gamma_port_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 12),
.win_vp_id[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 16),
.win_vp_id[ROCKCHIP_VOP2_CLUSTER1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 18),
.win_vp_id[ROCKCHIP_VOP2_CLUSTER2] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 20),
@@ -2684,6 +2689,7 @@ static const struct vop2_data rk3588_vop = {
.nr_vps = 4,
.nr_mixers = 7,
.nr_layers = 8,
.nr_gammas = 4,
.nr_pds = 7,
.max_input = { 4096, 4320 },
.max_output = { 4096, 4320 },