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staging: xillybus: Removed read barrier at beginning of ISR

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The comment (also removed) explains why it was there in the first place, but
that doesn't make much sense.

Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Eli Billauer
2014-08-16 18:58:01 +03:00
committed by Greg Kroah-Hartman
parent 9959078c96
commit 2d7f1d1c37
1 changed files with 0 additions and 8 deletions
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8
drivers/staging/xillybus/xillybus_core.c
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@@ -133,17 +133,9 @@ irqreturn_t xillybus_isr(int irq, void *data)
unsigned int msg_channel, msg_bufno, msg_data, msg_dir;
struct xilly_channel *channel;
/*
* The endpoint structure is altered during periods when it's
* guaranteed no interrupt will occur, but in theory, the cache
* lines may not be updated. So a memory barrier is issued.
*/
smp_rmb();
buf = ep->msgbuf_addr;
buf_size = ep->msg_buf_size/sizeof(u32);
ep->ephw->hw_sync_sgl_for_cpu(ep,
ep->msgbuf_dma_addr,
ep->msg_buf_size,