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https://github.com/hardkernel/linux.git
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Revert "iommu/vt-d: Retrieve IOMMU perfmon capability information"
This reverts commit586e19c88awhich is commita6a5006dadupstream. This commit is pulled in due to dependency for:8c91a4bfc7("iommu: Fix compilation without CONFIG_IOMMU_INTEL") But the patch itself is part of a patchset, should not only include one, and it lead to boot hang on on Kernel 6.1.83+ with Dell PowerEdge R770 and Intel Xeon 6710E, so revert it for stable 6.1.112 Signed-off-by: Jack Wang <jinpu.wang@ionos.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Jack Wang
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
de0456460f
commit
2da76b4d08
@@ -96,15 +96,4 @@ config INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON
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passing intel_iommu=sm_on to the kernel. If not sure, please use
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the default value.
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config INTEL_IOMMU_PERF_EVENTS
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def_bool y
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bool "Intel IOMMU performance events"
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depends on INTEL_IOMMU && PERF_EVENTS
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help
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Selecting this option will enable the performance monitoring
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infrastructure in the Intel IOMMU. It collects information about
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key events occurring during operation of the remapping hardware,
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to aid performance tuning and debug. These are available on modern
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processors which support Intel VT-d 4.0 and later.
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endif # INTEL_IOMMU
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@@ -8,4 +8,3 @@ obj-$(CONFIG_INTEL_IOMMU_SVM) += svm.o
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ifdef CONFIG_INTEL_IOMMU
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obj-$(CONFIG_IRQ_REMAP) += irq_remapping.o
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endif
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obj-$(CONFIG_INTEL_IOMMU_PERF_EVENTS) += perfmon.o
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@@ -34,7 +34,6 @@
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#include "../irq_remapping.h"
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#include "perf.h"
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#include "trace.h"
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#include "perfmon.h"
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typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *);
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struct dmar_res_callback {
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@@ -1105,9 +1104,6 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd)
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if (sts & DMA_GSTS_QIES)
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iommu->gcmd |= DMA_GCMD_QIE;
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if (alloc_iommu_pmu(iommu))
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pr_debug("Cannot alloc PMU for iommu (seq_id = %d)\n", iommu->seq_id);
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raw_spin_lock_init(&iommu->register_lock);
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/*
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@@ -1135,7 +1131,6 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd)
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err_sysfs:
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iommu_device_sysfs_remove(&iommu->iommu);
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err_unmap:
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free_iommu_pmu(iommu);
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unmap_iommu(iommu);
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error_free_seq_id:
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ida_free(&dmar_seq_ids, iommu->seq_id);
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@@ -1151,8 +1146,6 @@ static void free_iommu(struct intel_iommu *iommu)
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iommu_device_sysfs_remove(&iommu->iommu);
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}
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free_iommu_pmu(iommu);
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if (iommu->irq) {
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if (iommu->pr_irq) {
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free_irq(iommu->pr_irq, iommu);
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@@ -125,11 +125,6 @@
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#define DMAR_MTRR_PHYSMASK8_REG 0x208
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#define DMAR_MTRR_PHYSBASE9_REG 0x210
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#define DMAR_MTRR_PHYSMASK9_REG 0x218
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#define DMAR_PERFCAP_REG 0x300
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#define DMAR_PERFCFGOFF_REG 0x310
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#define DMAR_PERFOVFOFF_REG 0x318
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#define DMAR_PERFCNTROFF_REG 0x31c
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#define DMAR_PERFEVNTCAP_REG 0x380
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#define DMAR_VCCAP_REG 0xe30 /* Virtual command capability register */
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#define DMAR_VCMD_REG 0xe00 /* Virtual command register */
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#define DMAR_VCRSP_REG 0xe10 /* Virtual command response register */
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@@ -153,7 +148,6 @@
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*/
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#define cap_esrtps(c) (((c) >> 63) & 1)
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#define cap_esirtps(c) (((c) >> 62) & 1)
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#define cap_ecmds(c) (((c) >> 61) & 1)
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#define cap_fl5lp_support(c) (((c) >> 60) & 1)
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#define cap_pi_support(c) (((c) >> 59) & 1)
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#define cap_fl1gp_support(c) (((c) >> 56) & 1)
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@@ -185,8 +179,7 @@
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* Extended Capability Register
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*/
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#define ecap_pms(e) (((e) >> 51) & 0x1)
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#define ecap_rps(e) (((e) >> 49) & 0x1)
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#define ecap_rps(e) (((e) >> 49) & 0x1)
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#define ecap_smpwc(e) (((e) >> 48) & 0x1)
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#define ecap_flts(e) (((e) >> 47) & 0x1)
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#define ecap_slts(e) (((e) >> 46) & 0x1)
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@@ -217,22 +210,6 @@
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#define ecap_max_handle_mask(e) (((e) >> 20) & 0xf)
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#define ecap_sc_support(e) (((e) >> 7) & 0x1) /* Snooping Control */
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/*
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* Decoding Perf Capability Register
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*/
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#define pcap_num_cntr(p) ((p) & 0xffff)
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#define pcap_cntr_width(p) (((p) >> 16) & 0x7f)
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#define pcap_num_event_group(p) (((p) >> 24) & 0x1f)
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#define pcap_filters_mask(p) (((p) >> 32) & 0x1f)
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#define pcap_interrupt(p) (((p) >> 50) & 0x1)
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/* The counter stride is calculated as 2 ^ (x+10) bytes */
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#define pcap_cntr_stride(p) (1ULL << ((((p) >> 52) & 0x7) + 10))
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/*
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* Decoding Perf Event Capability Register
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*/
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#define pecap_es(p) ((p) & 0xfffffff)
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/* Virtual command interface capability */
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#define vccap_pasid(v) (((v) & DMA_VCS_PAS)) /* PASID allocation */
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@@ -584,22 +561,6 @@ struct dmar_domain {
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iommu core */
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};
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struct iommu_pmu {
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struct intel_iommu *iommu;
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u32 num_cntr; /* Number of counters */
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u32 num_eg; /* Number of event group */
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u32 cntr_width; /* Counter width */
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u32 cntr_stride; /* Counter Stride */
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u32 filter; /* Bitmask of filter support */
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void __iomem *base; /* the PerfMon base address */
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void __iomem *cfg_reg; /* counter configuration base address */
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void __iomem *cntr_reg; /* counter 0 address*/
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void __iomem *overflow; /* overflow status register */
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u64 *evcap; /* Indicates all supported events */
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u32 **cntr_evcap; /* Supported events of each counter. */
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};
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struct intel_iommu {
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void __iomem *reg; /* Pointer to hardware regs, virtual addr */
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u64 reg_phys; /* physical address of hw register set */
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@@ -647,8 +608,6 @@ struct intel_iommu {
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struct dmar_drhd_unit *drhd;
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void *perf_statistic;
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struct iommu_pmu *pmu;
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};
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/* PCI domain-device relationship */
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@@ -1,172 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Support Intel IOMMU PerfMon
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* Copyright(c) 2023 Intel Corporation.
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*/
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#define pr_fmt(fmt) "DMAR: " fmt
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#define dev_fmt(fmt) pr_fmt(fmt)
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#include <linux/dmar.h>
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#include "iommu.h"
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#include "perfmon.h"
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static inline void __iomem *
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get_perf_reg_address(struct intel_iommu *iommu, u32 offset)
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{
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u32 off = dmar_readl(iommu->reg + offset);
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return iommu->reg + off;
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}
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int alloc_iommu_pmu(struct intel_iommu *iommu)
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{
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struct iommu_pmu *iommu_pmu;
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int i, j, ret;
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u64 perfcap;
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u32 cap;
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if (!ecap_pms(iommu->ecap))
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return 0;
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/* The IOMMU PMU requires the ECMD support as well */
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if (!cap_ecmds(iommu->cap))
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return -ENODEV;
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perfcap = dmar_readq(iommu->reg + DMAR_PERFCAP_REG);
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/* The performance monitoring is not supported. */
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if (!perfcap)
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return -ENODEV;
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/* Sanity check for the number of the counters and event groups */
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if (!pcap_num_cntr(perfcap) || !pcap_num_event_group(perfcap))
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return -ENODEV;
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/* The interrupt on overflow is required */
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if (!pcap_interrupt(perfcap))
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return -ENODEV;
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iommu_pmu = kzalloc(sizeof(*iommu_pmu), GFP_KERNEL);
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if (!iommu_pmu)
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return -ENOMEM;
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iommu_pmu->num_cntr = pcap_num_cntr(perfcap);
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iommu_pmu->cntr_width = pcap_cntr_width(perfcap);
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iommu_pmu->filter = pcap_filters_mask(perfcap);
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iommu_pmu->cntr_stride = pcap_cntr_stride(perfcap);
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iommu_pmu->num_eg = pcap_num_event_group(perfcap);
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iommu_pmu->evcap = kcalloc(iommu_pmu->num_eg, sizeof(u64), GFP_KERNEL);
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if (!iommu_pmu->evcap) {
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ret = -ENOMEM;
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goto free_pmu;
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}
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/* Parse event group capabilities */
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for (i = 0; i < iommu_pmu->num_eg; i++) {
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u64 pcap;
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pcap = dmar_readq(iommu->reg + DMAR_PERFEVNTCAP_REG +
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i * IOMMU_PMU_CAP_REGS_STEP);
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iommu_pmu->evcap[i] = pecap_es(pcap);
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}
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iommu_pmu->cntr_evcap = kcalloc(iommu_pmu->num_cntr, sizeof(u32 *), GFP_KERNEL);
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if (!iommu_pmu->cntr_evcap) {
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ret = -ENOMEM;
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goto free_pmu_evcap;
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}
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for (i = 0; i < iommu_pmu->num_cntr; i++) {
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iommu_pmu->cntr_evcap[i] = kcalloc(iommu_pmu->num_eg, sizeof(u32), GFP_KERNEL);
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if (!iommu_pmu->cntr_evcap[i]) {
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ret = -ENOMEM;
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goto free_pmu_cntr_evcap;
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}
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/*
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* Set to the global capabilities, will adjust according
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* to per-counter capabilities later.
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*/
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for (j = 0; j < iommu_pmu->num_eg; j++)
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iommu_pmu->cntr_evcap[i][j] = (u32)iommu_pmu->evcap[j];
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}
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iommu_pmu->cfg_reg = get_perf_reg_address(iommu, DMAR_PERFCFGOFF_REG);
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iommu_pmu->cntr_reg = get_perf_reg_address(iommu, DMAR_PERFCNTROFF_REG);
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iommu_pmu->overflow = get_perf_reg_address(iommu, DMAR_PERFOVFOFF_REG);
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/*
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* Check per-counter capabilities. All counters should have the
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* same capabilities on Interrupt on Overflow Support and Counter
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* Width.
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*/
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for (i = 0; i < iommu_pmu->num_cntr; i++) {
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cap = dmar_readl(iommu_pmu->cfg_reg +
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i * IOMMU_PMU_CFG_OFFSET +
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IOMMU_PMU_CFG_CNTRCAP_OFFSET);
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if (!iommu_cntrcap_pcc(cap))
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continue;
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/*
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* It's possible that some counters have a different
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* capability because of e.g., HW bug. Check the corner
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* case here and simply drop those counters.
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*/
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if ((iommu_cntrcap_cw(cap) != iommu_pmu->cntr_width) ||
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!iommu_cntrcap_ios(cap)) {
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iommu_pmu->num_cntr = i;
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pr_warn("PMU counter capability inconsistent, counter number reduced to %d\n",
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iommu_pmu->num_cntr);
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}
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/* Clear the pre-defined events group */
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for (j = 0; j < iommu_pmu->num_eg; j++)
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iommu_pmu->cntr_evcap[i][j] = 0;
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/* Override with per-counter event capabilities */
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for (j = 0; j < iommu_cntrcap_egcnt(cap); j++) {
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cap = dmar_readl(iommu_pmu->cfg_reg + i * IOMMU_PMU_CFG_OFFSET +
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IOMMU_PMU_CFG_CNTREVCAP_OFFSET +
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(j * IOMMU_PMU_OFF_REGS_STEP));
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iommu_pmu->cntr_evcap[i][iommu_event_group(cap)] = iommu_event_select(cap);
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/*
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* Some events may only be supported by a specific counter.
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* Track them in the evcap as well.
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*/
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iommu_pmu->evcap[iommu_event_group(cap)] |= iommu_event_select(cap);
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}
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}
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iommu_pmu->iommu = iommu;
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iommu->pmu = iommu_pmu;
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return 0;
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free_pmu_cntr_evcap:
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for (i = 0; i < iommu_pmu->num_cntr; i++)
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kfree(iommu_pmu->cntr_evcap[i]);
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kfree(iommu_pmu->cntr_evcap);
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free_pmu_evcap:
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kfree(iommu_pmu->evcap);
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free_pmu:
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kfree(iommu_pmu);
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return ret;
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}
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void free_iommu_pmu(struct intel_iommu *iommu)
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{
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struct iommu_pmu *iommu_pmu = iommu->pmu;
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if (!iommu_pmu)
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return;
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if (iommu_pmu->evcap) {
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int i;
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for (i = 0; i < iommu_pmu->num_cntr; i++)
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kfree(iommu_pmu->cntr_evcap[i]);
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kfree(iommu_pmu->cntr_evcap);
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}
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kfree(iommu_pmu->evcap);
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kfree(iommu_pmu);
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iommu->pmu = NULL;
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}
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@@ -1,40 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* PERFCFGOFF_REG, PERFFRZOFF_REG
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* PERFOVFOFF_REG, PERFCNTROFF_REG
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*/
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#define IOMMU_PMU_NUM_OFF_REGS 4
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#define IOMMU_PMU_OFF_REGS_STEP 4
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#define IOMMU_PMU_CFG_OFFSET 0x100
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#define IOMMU_PMU_CFG_CNTRCAP_OFFSET 0x80
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#define IOMMU_PMU_CFG_CNTREVCAP_OFFSET 0x84
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#define IOMMU_PMU_CFG_SIZE 0x8
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#define IOMMU_PMU_CFG_FILTERS_OFFSET 0x4
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#define IOMMU_PMU_CAP_REGS_STEP 8
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#define iommu_cntrcap_pcc(p) ((p) & 0x1)
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#define iommu_cntrcap_cw(p) (((p) >> 8) & 0xff)
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#define iommu_cntrcap_ios(p) (((p) >> 16) & 0x1)
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#define iommu_cntrcap_egcnt(p) (((p) >> 28) & 0xf)
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#define iommu_event_select(p) ((p) & 0xfffffff)
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#define iommu_event_group(p) (((p) >> 28) & 0xf)
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#ifdef CONFIG_INTEL_IOMMU_PERF_EVENTS
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int alloc_iommu_pmu(struct intel_iommu *iommu);
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void free_iommu_pmu(struct intel_iommu *iommu);
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#else
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static inline int
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alloc_iommu_pmu(struct intel_iommu *iommu)
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{
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return 0;
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}
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static inline void
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free_iommu_pmu(struct intel_iommu *iommu)
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{
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}
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#endif /* CONFIG_INTEL_IOMMU_PERF_EVENTS */
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