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video/rockchip: rga: remove ^m
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com> Change-Id: I2d3945442ef45b6baa9be9d286c1d7b4c70918c8
This commit is contained in:
Yu Qiaowei
@@ -1,201 +1,201 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/memory.h>
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#include "RGA_API.h"
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#include "rga.h"
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//#include "rga_angle.h"
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#define IS_YUV_420(format) \
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((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \
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(format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP))
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#define IS_YUV_422(format) \
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((format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \
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(format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))
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#define IS_YUV(format) \
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((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \
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(format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP) | \
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(format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \
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(format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))
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extern rga_service_info rga_service;
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void
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matrix_cal(const struct rga_req *msg, TILE_INFO *tile)
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{
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uint64_t x_time, y_time;
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uint64_t sina, cosa;
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int s_act_w, s_act_h, d_act_w, d_act_h;
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s_act_w = msg->src.act_w;
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s_act_h = msg->src.act_h;
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d_act_w = msg->dst.act_w;
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d_act_h = msg->dst.act_h;
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if (s_act_w == 1) s_act_w += 1;
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if (s_act_h == 1) s_act_h += 1;
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if (d_act_h == 1) d_act_h += 1;
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if (d_act_w == 1) d_act_w += 1;
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x_time = ((s_act_w - 1)<<16) / (d_act_w - 1);
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y_time = ((s_act_h - 1)<<16) / (d_act_h - 1);
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sina = msg->sina;
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cosa = msg->cosa;
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switch(msg->rotate_mode)
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{
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/* 16.16 x 16.16 */
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/* matrix[] is 64 bit wide */
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case 1 :
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tile->matrix[0] = cosa*x_time;
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tile->matrix[1] = -sina*y_time;
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tile->matrix[2] = sina*x_time;
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tile->matrix[3] = cosa*y_time;
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break;
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case 2 :
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tile->matrix[0] = -(x_time<<16);
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tile->matrix[1] = 0;
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tile->matrix[2] = 0;
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tile->matrix[3] = (y_time<<16);
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break;
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case 3 :
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tile->matrix[0] = (x_time<<16);
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tile->matrix[1] = 0;
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tile->matrix[2] = 0;
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tile->matrix[3] = -(y_time<<16);
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break;
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default :
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tile->matrix[0] = (uint64_t)1<<32;
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tile->matrix[1] = 0;
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tile->matrix[2] = 0;
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tile->matrix[3] = (uint64_t)1<<32;
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break;
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}
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}
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int32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1)
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{
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struct rga_req *mp;
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uint32_t w_ratio, h_ratio;
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uint32_t stride;
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uint32_t daw, dah;
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uint32_t pl;
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daw = dah = 0;
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mp = msg1;
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if(msg->dst.act_w == 0)
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{
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printk("%s, [%d] rga dst act_w is zero\n", __FUNCTION__, __LINE__);
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return -EINVAL;
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}
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if (msg->dst.act_h == 0)
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{
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printk("%s, [%d] rga dst act_w is zero\n", __FUNCTION__, __LINE__);
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return -EINVAL;
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}
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w_ratio = (msg->src.act_w << 16) / msg->dst.act_w;
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h_ratio = (msg->src.act_h << 16) / msg->dst.act_h;
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memcpy(msg1, msg, sizeof(struct rga_req));
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msg->dst.format = msg->src.format;
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/*pre_scale_w cal*/
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if ((w_ratio >= (2<<16)) && (w_ratio < (4<<16))) {
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daw = (msg->src.act_w + 1) >> 1;
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if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {
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daw -= 1;
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msg->src.act_w = daw << 1;
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}
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}
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else if ((w_ratio >= (4<<16)) && (w_ratio < (8<<16))) {
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daw = (msg->src.act_w + 3) >> 2;
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if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {
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daw -= 1;
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msg->src.act_w = daw << 2;
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}
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}
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else if ((w_ratio >= (8<<16)) && (w_ratio < (16<<16))) {
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daw = (msg->src.act_w + 7) >> 3;
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if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {
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daw -= 1;
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msg->src.act_w = daw << 3;
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}
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}
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else
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{
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daw = msg->src.act_w;
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}
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pl = (RGA_pixel_width_init(msg->src.format));
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stride = (pl * daw + 3) & (~3);
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msg->dst.act_w = daw;
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msg->dst.vir_w = stride / pl;
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/*pre_scale_h cal*/
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if ((h_ratio >= (2<<16)) && (h_ratio < (4<<16))) {
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dah = (msg->src.act_h + 1) >> 1;
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if((IS_YUV(msg->dst.format)) && (dah & 1)) {
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dah -= 1;
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msg->src.act_h = dah << 1;
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}
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}
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else if ((h_ratio >= (4<<16)) && (h_ratio < (8<<16))) {
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dah = (msg->src.act_h + 3) >> 2;
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if((IS_YUV(msg->dst.format)) && (dah & 1)) {
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dah -= 1;
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msg->src.act_h = dah << 2;
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}
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}
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else if ((h_ratio >= (8<<16)) && (h_ratio < (16<<16))) {
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dah = (msg->src.act_h + 7) >> 3;
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if((IS_YUV(msg->dst.format)) && (dah & 1)) {
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dah -= 1;
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msg->src.act_h = dah << 3;
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}
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}
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else
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{
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dah = msg->src.act_h;
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}
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msg->dst.act_h = dah;
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msg->dst.vir_h = dah;
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msg->dst.x_offset = 0;
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msg->dst.y_offset = 0;
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msg->dst.yrgb_addr = (unsigned long)rga_service.pre_scale_buf;
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msg->dst.uv_addr = msg->dst.yrgb_addr + stride * dah;
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msg->dst.v_addr = msg->dst.uv_addr + ((stride * dah) >> 1);
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msg->render_mode = pre_scaling_mode;
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msg1->src.yrgb_addr = msg->dst.yrgb_addr;
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msg1->src.uv_addr = msg->dst.uv_addr;
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msg1->src.v_addr = msg->dst.v_addr;
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msg1->src.act_w = msg->dst.act_w;
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msg1->src.act_h = msg->dst.act_h;
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msg1->src.vir_w = msg->dst.vir_w;
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msg1->src.vir_h = msg->dst.vir_h;
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msg1->src.x_offset = 0;
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msg1->src.y_offset = 0;
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return 0;
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}
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#include <linux/memory.h>
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#include "RGA_API.h"
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#include "rga.h"
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//#include "rga_angle.h"
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#define IS_YUV_420(format) \
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((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \
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(format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP))
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#define IS_YUV_422(format) \
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((format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \
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(format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))
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#define IS_YUV(format) \
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((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \
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(format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP) | \
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(format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \
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(format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))
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extern rga_service_info rga_service;
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void
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matrix_cal(const struct rga_req *msg, TILE_INFO *tile)
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{
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uint64_t x_time, y_time;
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uint64_t sina, cosa;
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int s_act_w, s_act_h, d_act_w, d_act_h;
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s_act_w = msg->src.act_w;
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s_act_h = msg->src.act_h;
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d_act_w = msg->dst.act_w;
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d_act_h = msg->dst.act_h;
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if (s_act_w == 1) s_act_w += 1;
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if (s_act_h == 1) s_act_h += 1;
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if (d_act_h == 1) d_act_h += 1;
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if (d_act_w == 1) d_act_w += 1;
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x_time = ((s_act_w - 1)<<16) / (d_act_w - 1);
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y_time = ((s_act_h - 1)<<16) / (d_act_h - 1);
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sina = msg->sina;
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cosa = msg->cosa;
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switch(msg->rotate_mode)
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{
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/* 16.16 x 16.16 */
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/* matrix[] is 64 bit wide */
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case 1 :
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tile->matrix[0] = cosa*x_time;
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tile->matrix[1] = -sina*y_time;
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tile->matrix[2] = sina*x_time;
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tile->matrix[3] = cosa*y_time;
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break;
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case 2 :
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tile->matrix[0] = -(x_time<<16);
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tile->matrix[1] = 0;
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tile->matrix[2] = 0;
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tile->matrix[3] = (y_time<<16);
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break;
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case 3 :
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tile->matrix[0] = (x_time<<16);
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tile->matrix[1] = 0;
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tile->matrix[2] = 0;
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tile->matrix[3] = -(y_time<<16);
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break;
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default :
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tile->matrix[0] = (uint64_t)1<<32;
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tile->matrix[1] = 0;
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tile->matrix[2] = 0;
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tile->matrix[3] = (uint64_t)1<<32;
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break;
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}
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}
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int32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1)
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{
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struct rga_req *mp;
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uint32_t w_ratio, h_ratio;
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uint32_t stride;
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uint32_t daw, dah;
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uint32_t pl;
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daw = dah = 0;
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mp = msg1;
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if(msg->dst.act_w == 0)
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{
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printk("%s, [%d] rga dst act_w is zero\n", __FUNCTION__, __LINE__);
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return -EINVAL;
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}
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if (msg->dst.act_h == 0)
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{
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printk("%s, [%d] rga dst act_w is zero\n", __FUNCTION__, __LINE__);
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return -EINVAL;
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}
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w_ratio = (msg->src.act_w << 16) / msg->dst.act_w;
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h_ratio = (msg->src.act_h << 16) / msg->dst.act_h;
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memcpy(msg1, msg, sizeof(struct rga_req));
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msg->dst.format = msg->src.format;
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/*pre_scale_w cal*/
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if ((w_ratio >= (2<<16)) && (w_ratio < (4<<16))) {
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daw = (msg->src.act_w + 1) >> 1;
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if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {
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daw -= 1;
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msg->src.act_w = daw << 1;
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}
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}
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else if ((w_ratio >= (4<<16)) && (w_ratio < (8<<16))) {
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daw = (msg->src.act_w + 3) >> 2;
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if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {
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daw -= 1;
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msg->src.act_w = daw << 2;
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}
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}
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else if ((w_ratio >= (8<<16)) && (w_ratio < (16<<16))) {
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daw = (msg->src.act_w + 7) >> 3;
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if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {
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daw -= 1;
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msg->src.act_w = daw << 3;
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}
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}
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else
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{
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daw = msg->src.act_w;
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}
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pl = (RGA_pixel_width_init(msg->src.format));
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stride = (pl * daw + 3) & (~3);
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msg->dst.act_w = daw;
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msg->dst.vir_w = stride / pl;
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/*pre_scale_h cal*/
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if ((h_ratio >= (2<<16)) && (h_ratio < (4<<16))) {
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dah = (msg->src.act_h + 1) >> 1;
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if((IS_YUV(msg->dst.format)) && (dah & 1)) {
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dah -= 1;
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msg->src.act_h = dah << 1;
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}
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}
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else if ((h_ratio >= (4<<16)) && (h_ratio < (8<<16))) {
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dah = (msg->src.act_h + 3) >> 2;
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if((IS_YUV(msg->dst.format)) && (dah & 1)) {
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dah -= 1;
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msg->src.act_h = dah << 2;
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}
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}
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else if ((h_ratio >= (8<<16)) && (h_ratio < (16<<16))) {
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dah = (msg->src.act_h + 7) >> 3;
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if((IS_YUV(msg->dst.format)) && (dah & 1)) {
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dah -= 1;
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msg->src.act_h = dah << 3;
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}
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}
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else
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{
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dah = msg->src.act_h;
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}
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msg->dst.act_h = dah;
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msg->dst.vir_h = dah;
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msg->dst.x_offset = 0;
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msg->dst.y_offset = 0;
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msg->dst.yrgb_addr = (unsigned long)rga_service.pre_scale_buf;
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msg->dst.uv_addr = msg->dst.yrgb_addr + stride * dah;
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msg->dst.v_addr = msg->dst.uv_addr + ((stride * dah) >> 1);
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msg->render_mode = pre_scaling_mode;
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msg1->src.yrgb_addr = msg->dst.yrgb_addr;
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msg1->src.uv_addr = msg->dst.uv_addr;
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msg1->src.v_addr = msg->dst.v_addr;
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msg1->src.act_w = msg->dst.act_w;
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msg1->src.act_h = msg->dst.act_h;
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msg1->src.vir_w = msg->dst.vir_w;
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msg1->src.vir_h = msg->dst.vir_h;
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msg1->src.x_offset = 0;
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msg1->src.y_offset = 0;
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return 0;
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}
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@@ -1,14 +1,14 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __RGA_API_H__
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#define __RGA_API_H__
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#ifndef __RGA_API_H__
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#define __RGA_API_H__
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#include <linux/miscdevice.h>
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#include <linux/wakelock.h>
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#include "rga_reg_info.h"
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#include "rga.h"
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#define ENABLE 1
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#include "rga_reg_info.h"
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#include "rga.h"
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#define ENABLE 1
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#define DISABLE 0
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struct rga_drvdata {
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@@ -31,10 +31,10 @@ struct rga_drvdata {
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char *version;
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||||
};
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||||
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||||
int32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1);
|
||||
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||||
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||||
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||||
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||||
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#endif
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int32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1);
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||||
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||||
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#endif
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||||
|
||||
@@ -1,508 +1,508 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _RGA_DRIVER_H_
|
||||
#define _RGA_DRIVER_H_
|
||||
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/scatterlist.h>
|
||||
|
||||
|
||||
#define RGA_BLIT_SYNC 0x5017
|
||||
#define RGA_BLIT_ASYNC 0x5018
|
||||
#define RGA_FLUSH 0x5019
|
||||
#define RGA_GET_RESULT 0x501a
|
||||
#define RGA_GET_VERSION 0x501b
|
||||
|
||||
|
||||
#define RGA_REG_CTRL_LEN 0x8 /* 8 */
|
||||
#define RGA_REG_CMD_LEN 0x20 /* 32 */
|
||||
#define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */
|
||||
|
||||
#define RGA_OUT_OF_RESOURCES -10
|
||||
#define RGA_MALLOC_ERROR -11
|
||||
|
||||
#ifndef _RGA_DRIVER_H_
|
||||
#define _RGA_DRIVER_H_
|
||||
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/scatterlist.h>
|
||||
|
||||
|
||||
#define RGA_BLIT_SYNC 0x5017
|
||||
#define RGA_BLIT_ASYNC 0x5018
|
||||
#define RGA_FLUSH 0x5019
|
||||
#define RGA_GET_RESULT 0x501a
|
||||
#define RGA_GET_VERSION 0x501b
|
||||
|
||||
|
||||
#define RGA_REG_CTRL_LEN 0x8 /* 8 */
|
||||
#define RGA_REG_CMD_LEN 0x20 /* 32 */
|
||||
#define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */
|
||||
|
||||
#define RGA_OUT_OF_RESOURCES -10
|
||||
#define RGA_MALLOC_ERROR -11
|
||||
|
||||
#define RGA_BUF_GEM_TYPE_MASK 0xC0
|
||||
|
||||
#define rgaIS_ERROR(status) (status < 0)
|
||||
#define rgaNO_ERROR(status) (status >= 0)
|
||||
#define rgaIS_SUCCESS(status) (status == 0)
|
||||
|
||||
|
||||
#define rgaIS_ERROR(status) (status < 0)
|
||||
#define rgaNO_ERROR(status) (status >= 0)
|
||||
#define rgaIS_SUCCESS(status) (status == 0)
|
||||
|
||||
#define RGA_DEBUGFS 1
|
||||
|
||||
/* RGA process mode enum */
|
||||
enum
|
||||
{
|
||||
bitblt_mode = 0x0,
|
||||
color_palette_mode = 0x1,
|
||||
color_fill_mode = 0x2,
|
||||
line_point_drawing_mode = 0x3,
|
||||
blur_sharp_filter_mode = 0x4,
|
||||
pre_scaling_mode = 0x5,
|
||||
update_palette_table_mode = 0x6,
|
||||
update_patten_buff_mode = 0x7,
|
||||
};
|
||||
|
||||
|
||||
enum
|
||||
{
|
||||
rop_enable_mask = 0x2,
|
||||
dither_enable_mask = 0x8,
|
||||
fading_enable_mask = 0x10,
|
||||
PD_enbale_mask = 0x20,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */
|
||||
yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */
|
||||
yuv2rgb_mode2 = 0x2, /* BT.709 */
|
||||
};
|
||||
|
||||
|
||||
/* RGA rotate mode */
|
||||
enum
|
||||
{
|
||||
rotate_mode0 = 0x0, /* no rotate */
|
||||
rotate_mode1 = 0x1, /* rotate */
|
||||
rotate_mode2 = 0x2, /* x_mirror */
|
||||
rotate_mode3 = 0x3, /* y_mirror */
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
color_palette_mode0 = 0x0, /* 1K */
|
||||
color_palette_mode1 = 0x1, /* 2K */
|
||||
color_palette_mode2 = 0x2, /* 4K */
|
||||
color_palette_mode3 = 0x3, /* 8K */
|
||||
};
|
||||
|
||||
|
||||
|
||||
/*
|
||||
// Alpha Red Green Blue
|
||||
{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888
|
||||
{ 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888
|
||||
{ 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888
|
||||
{ 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888
|
||||
{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565
|
||||
{ 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551
|
||||
{ 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444
|
||||
{ 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888
|
||||
|
||||
*/
|
||||
enum
|
||||
{
|
||||
RK_FORMAT_RGBA_8888 = 0x0,
|
||||
RK_FORMAT_RGBX_8888 = 0x1,
|
||||
RK_FORMAT_RGB_888 = 0x2,
|
||||
RK_FORMAT_BGRA_8888 = 0x3,
|
||||
RK_FORMAT_RGB_565 = 0x4,
|
||||
RK_FORMAT_RGBA_5551 = 0x5,
|
||||
RK_FORMAT_RGBA_4444 = 0x6,
|
||||
RK_FORMAT_BGR_888 = 0x7,
|
||||
|
||||
RK_FORMAT_YCbCr_422_SP = 0x8,
|
||||
RK_FORMAT_YCbCr_422_P = 0x9,
|
||||
RK_FORMAT_YCbCr_420_SP = 0xa,
|
||||
RK_FORMAT_YCbCr_420_P = 0xb,
|
||||
|
||||
RK_FORMAT_YCrCb_422_SP = 0xc,
|
||||
RK_FORMAT_YCrCb_422_P = 0xd,
|
||||
RK_FORMAT_YCrCb_420_SP = 0xe,
|
||||
RK_FORMAT_YCrCb_420_P = 0xf,
|
||||
|
||||
RK_FORMAT_BPP1 = 0x10,
|
||||
RK_FORMAT_BPP2 = 0x11,
|
||||
RK_FORMAT_BPP4 = 0x12,
|
||||
RK_FORMAT_BPP8 = 0x13,
|
||||
RK_FORMAT_YCbCr_420_SP_10B = 0x20,
|
||||
RK_FORMAT_YCrCb_420_SP_10B = 0x21,
|
||||
};
|
||||
|
||||
|
||||
typedef struct rga_img_info_t
|
||||
{
|
||||
unsigned long yrgb_addr; /* yrgb mem addr */
|
||||
unsigned long uv_addr; /* cb/cr mem addr */
|
||||
unsigned long v_addr; /* cr mem addr */
|
||||
unsigned int format; //definition by RK_FORMAT
|
||||
|
||||
unsigned short act_w;
|
||||
unsigned short act_h;
|
||||
unsigned short x_offset;
|
||||
unsigned short y_offset;
|
||||
|
||||
unsigned short vir_w;
|
||||
unsigned short vir_h;
|
||||
|
||||
unsigned short endian_mode; //for BPP
|
||||
unsigned short alpha_swap;
|
||||
}
|
||||
rga_img_info_t;
|
||||
|
||||
|
||||
typedef struct mdp_img_act
|
||||
{
|
||||
unsigned short w; // width
|
||||
unsigned short h; // height
|
||||
short x_off; // x offset for the vir
|
||||
short y_off; // y offset for the vir
|
||||
}
|
||||
mdp_img_act;
|
||||
|
||||
|
||||
|
||||
typedef struct RANGE
|
||||
{
|
||||
unsigned short min;
|
||||
unsigned short max;
|
||||
}
|
||||
RANGE;
|
||||
|
||||
typedef struct POINT
|
||||
{
|
||||
unsigned short x;
|
||||
unsigned short y;
|
||||
}
|
||||
POINT;
|
||||
|
||||
typedef struct RECT
|
||||
{
|
||||
unsigned short xmin;
|
||||
unsigned short xmax; // width - 1
|
||||
unsigned short ymin;
|
||||
unsigned short ymax; // height - 1
|
||||
} RECT;
|
||||
|
||||
typedef struct RGB
|
||||
{
|
||||
unsigned char r;
|
||||
unsigned char g;
|
||||
unsigned char b;
|
||||
unsigned char res;
|
||||
}RGB;
|
||||
|
||||
|
||||
typedef struct MMU
|
||||
{
|
||||
unsigned char mmu_en;
|
||||
unsigned long base_addr;
|
||||
|
||||
/* RGA process mode enum */
|
||||
enum
|
||||
{
|
||||
bitblt_mode = 0x0,
|
||||
color_palette_mode = 0x1,
|
||||
color_fill_mode = 0x2,
|
||||
line_point_drawing_mode = 0x3,
|
||||
blur_sharp_filter_mode = 0x4,
|
||||
pre_scaling_mode = 0x5,
|
||||
update_palette_table_mode = 0x6,
|
||||
update_patten_buff_mode = 0x7,
|
||||
};
|
||||
|
||||
|
||||
enum
|
||||
{
|
||||
rop_enable_mask = 0x2,
|
||||
dither_enable_mask = 0x8,
|
||||
fading_enable_mask = 0x10,
|
||||
PD_enbale_mask = 0x20,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */
|
||||
yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */
|
||||
yuv2rgb_mode2 = 0x2, /* BT.709 */
|
||||
};
|
||||
|
||||
|
||||
/* RGA rotate mode */
|
||||
enum
|
||||
{
|
||||
rotate_mode0 = 0x0, /* no rotate */
|
||||
rotate_mode1 = 0x1, /* rotate */
|
||||
rotate_mode2 = 0x2, /* x_mirror */
|
||||
rotate_mode3 = 0x3, /* y_mirror */
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
color_palette_mode0 = 0x0, /* 1K */
|
||||
color_palette_mode1 = 0x1, /* 2K */
|
||||
color_palette_mode2 = 0x2, /* 4K */
|
||||
color_palette_mode3 = 0x3, /* 8K */
|
||||
};
|
||||
|
||||
|
||||
|
||||
/*
|
||||
// Alpha Red Green Blue
|
||||
{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888
|
||||
{ 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888
|
||||
{ 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888
|
||||
{ 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888
|
||||
{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565
|
||||
{ 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551
|
||||
{ 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444
|
||||
{ 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888
|
||||
|
||||
*/
|
||||
enum
|
||||
{
|
||||
RK_FORMAT_RGBA_8888 = 0x0,
|
||||
RK_FORMAT_RGBX_8888 = 0x1,
|
||||
RK_FORMAT_RGB_888 = 0x2,
|
||||
RK_FORMAT_BGRA_8888 = 0x3,
|
||||
RK_FORMAT_RGB_565 = 0x4,
|
||||
RK_FORMAT_RGBA_5551 = 0x5,
|
||||
RK_FORMAT_RGBA_4444 = 0x6,
|
||||
RK_FORMAT_BGR_888 = 0x7,
|
||||
|
||||
RK_FORMAT_YCbCr_422_SP = 0x8,
|
||||
RK_FORMAT_YCbCr_422_P = 0x9,
|
||||
RK_FORMAT_YCbCr_420_SP = 0xa,
|
||||
RK_FORMAT_YCbCr_420_P = 0xb,
|
||||
|
||||
RK_FORMAT_YCrCb_422_SP = 0xc,
|
||||
RK_FORMAT_YCrCb_422_P = 0xd,
|
||||
RK_FORMAT_YCrCb_420_SP = 0xe,
|
||||
RK_FORMAT_YCrCb_420_P = 0xf,
|
||||
|
||||
RK_FORMAT_BPP1 = 0x10,
|
||||
RK_FORMAT_BPP2 = 0x11,
|
||||
RK_FORMAT_BPP4 = 0x12,
|
||||
RK_FORMAT_BPP8 = 0x13,
|
||||
RK_FORMAT_YCbCr_420_SP_10B = 0x20,
|
||||
RK_FORMAT_YCrCb_420_SP_10B = 0x21,
|
||||
};
|
||||
|
||||
|
||||
typedef struct rga_img_info_t
|
||||
{
|
||||
unsigned long yrgb_addr; /* yrgb mem addr */
|
||||
unsigned long uv_addr; /* cb/cr mem addr */
|
||||
unsigned long v_addr; /* cr mem addr */
|
||||
unsigned int format; //definition by RK_FORMAT
|
||||
|
||||
unsigned short act_w;
|
||||
unsigned short act_h;
|
||||
unsigned short x_offset;
|
||||
unsigned short y_offset;
|
||||
|
||||
unsigned short vir_w;
|
||||
unsigned short vir_h;
|
||||
|
||||
unsigned short endian_mode; //for BPP
|
||||
unsigned short alpha_swap;
|
||||
}
|
||||
rga_img_info_t;
|
||||
|
||||
|
||||
typedef struct mdp_img_act
|
||||
{
|
||||
unsigned short w; // width
|
||||
unsigned short h; // height
|
||||
short x_off; // x offset for the vir
|
||||
short y_off; // y offset for the vir
|
||||
}
|
||||
mdp_img_act;
|
||||
|
||||
|
||||
|
||||
typedef struct RANGE
|
||||
{
|
||||
unsigned short min;
|
||||
unsigned short max;
|
||||
}
|
||||
RANGE;
|
||||
|
||||
typedef struct POINT
|
||||
{
|
||||
unsigned short x;
|
||||
unsigned short y;
|
||||
}
|
||||
POINT;
|
||||
|
||||
typedef struct RECT
|
||||
{
|
||||
unsigned short xmin;
|
||||
unsigned short xmax; // width - 1
|
||||
unsigned short ymin;
|
||||
unsigned short ymax; // height - 1
|
||||
} RECT;
|
||||
|
||||
typedef struct RGB
|
||||
{
|
||||
unsigned char r;
|
||||
unsigned char g;
|
||||
unsigned char b;
|
||||
unsigned char res;
|
||||
}RGB;
|
||||
|
||||
|
||||
typedef struct MMU
|
||||
{
|
||||
unsigned char mmu_en;
|
||||
unsigned long base_addr;
|
||||
uint32_t mmu_flag;
|
||||
} MMU;
|
||||
|
||||
|
||||
|
||||
|
||||
typedef struct COLOR_FILL
|
||||
{
|
||||
short gr_x_a;
|
||||
short gr_y_a;
|
||||
short gr_x_b;
|
||||
short gr_y_b;
|
||||
short gr_x_g;
|
||||
short gr_y_g;
|
||||
short gr_x_r;
|
||||
short gr_y_r;
|
||||
|
||||
//u8 cp_gr_saturation;
|
||||
}
|
||||
COLOR_FILL;
|
||||
|
||||
typedef struct FADING
|
||||
{
|
||||
uint8_t b;
|
||||
uint8_t g;
|
||||
uint8_t r;
|
||||
uint8_t res;
|
||||
}
|
||||
FADING;
|
||||
|
||||
|
||||
typedef struct line_draw_t
|
||||
{
|
||||
POINT start_point; /* LineDraw_start_point */
|
||||
POINT end_point; /* LineDraw_end_point */
|
||||
uint32_t color; /* LineDraw_color */
|
||||
uint32_t flag; /* (enum) LineDrawing mode sel */
|
||||
uint32_t line_width; /* range 1~16 */
|
||||
}
|
||||
line_draw_t;
|
||||
|
||||
|
||||
|
||||
struct rga_req {
|
||||
uint8_t render_mode; /* (enum) process mode sel */
|
||||
|
||||
rga_img_info_t src; /* src image info */
|
||||
rga_img_info_t dst; /* dst image info */
|
||||
rga_img_info_t pat; /* patten image info */
|
||||
|
||||
unsigned long rop_mask_addr; /* rop4 mask addr */
|
||||
unsigned long LUT_addr; /* LUT addr */
|
||||
|
||||
RECT clip; /* dst clip window default value is dst_vir */
|
||||
/* value from [0, w-1] / [0, h-1]*/
|
||||
|
||||
int32_t sina; /* dst angle default value 0 16.16 scan from table */
|
||||
int32_t cosa; /* dst angle default value 0 16.16 scan from table */
|
||||
|
||||
uint16_t alpha_rop_flag; /* alpha rop process flag */
|
||||
/* ([0] = 1 alpha_rop_enable) */
|
||||
/* ([1] = 1 rop enable) */
|
||||
/* ([2] = 1 fading_enable) */
|
||||
/* ([3] = 1 PD_enable) */
|
||||
/* ([4] = 1 alpha cal_mode_sel) */
|
||||
/* ([5] = 1 dither_enable) */
|
||||
/* ([6] = 1 gradient fill mode sel) */
|
||||
/* ([7] = 1 AA_enable) */
|
||||
|
||||
uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */
|
||||
|
||||
uint32_t color_key_max; /* color key max */
|
||||
uint32_t color_key_min; /* color key min */
|
||||
|
||||
uint32_t fg_color; /* foreground color */
|
||||
uint32_t bg_color; /* background color */
|
||||
|
||||
COLOR_FILL gr_color; /* color fill use gradient */
|
||||
|
||||
line_draw_t line_draw_info;
|
||||
|
||||
FADING fading;
|
||||
|
||||
uint8_t PD_mode; /* porter duff alpha mode sel */
|
||||
|
||||
uint8_t alpha_global_value; /* global alpha value */
|
||||
|
||||
uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/
|
||||
|
||||
uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/
|
||||
|
||||
uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
|
||||
|
||||
uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
|
||||
|
||||
uint8_t endian_mode; /* 0/big endian 1/little endian*/
|
||||
|
||||
uint8_t rotate_mode; /* (enum) rotate mode */
|
||||
/* 0x0, no rotate */
|
||||
/* 0x1, rotate */
|
||||
/* 0x2, x_mirror */
|
||||
/* 0x3, y_mirror */
|
||||
|
||||
uint8_t color_fill_mode; /* 0 solid color / 1 patten color */
|
||||
|
||||
MMU mmu_info; /* mmu information */
|
||||
|
||||
uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */
|
||||
/* ([2~3] rop mode) */
|
||||
/* ([4] zero mode en) */
|
||||
/* ([5] dst alpha mode) */
|
||||
|
||||
uint8_t src_trans_mode;
|
||||
|
||||
struct sg_table *sg_src;
|
||||
} MMU;
|
||||
|
||||
|
||||
|
||||
|
||||
typedef struct COLOR_FILL
|
||||
{
|
||||
short gr_x_a;
|
||||
short gr_y_a;
|
||||
short gr_x_b;
|
||||
short gr_y_b;
|
||||
short gr_x_g;
|
||||
short gr_y_g;
|
||||
short gr_x_r;
|
||||
short gr_y_r;
|
||||
|
||||
//u8 cp_gr_saturation;
|
||||
}
|
||||
COLOR_FILL;
|
||||
|
||||
typedef struct FADING
|
||||
{
|
||||
uint8_t b;
|
||||
uint8_t g;
|
||||
uint8_t r;
|
||||
uint8_t res;
|
||||
}
|
||||
FADING;
|
||||
|
||||
|
||||
typedef struct line_draw_t
|
||||
{
|
||||
POINT start_point; /* LineDraw_start_point */
|
||||
POINT end_point; /* LineDraw_end_point */
|
||||
uint32_t color; /* LineDraw_color */
|
||||
uint32_t flag; /* (enum) LineDrawing mode sel */
|
||||
uint32_t line_width; /* range 1~16 */
|
||||
}
|
||||
line_draw_t;
|
||||
|
||||
|
||||
|
||||
struct rga_req {
|
||||
uint8_t render_mode; /* (enum) process mode sel */
|
||||
|
||||
rga_img_info_t src; /* src image info */
|
||||
rga_img_info_t dst; /* dst image info */
|
||||
rga_img_info_t pat; /* patten image info */
|
||||
|
||||
unsigned long rop_mask_addr; /* rop4 mask addr */
|
||||
unsigned long LUT_addr; /* LUT addr */
|
||||
|
||||
RECT clip; /* dst clip window default value is dst_vir */
|
||||
/* value from [0, w-1] / [0, h-1]*/
|
||||
|
||||
int32_t sina; /* dst angle default value 0 16.16 scan from table */
|
||||
int32_t cosa; /* dst angle default value 0 16.16 scan from table */
|
||||
|
||||
uint16_t alpha_rop_flag; /* alpha rop process flag */
|
||||
/* ([0] = 1 alpha_rop_enable) */
|
||||
/* ([1] = 1 rop enable) */
|
||||
/* ([2] = 1 fading_enable) */
|
||||
/* ([3] = 1 PD_enable) */
|
||||
/* ([4] = 1 alpha cal_mode_sel) */
|
||||
/* ([5] = 1 dither_enable) */
|
||||
/* ([6] = 1 gradient fill mode sel) */
|
||||
/* ([7] = 1 AA_enable) */
|
||||
|
||||
uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */
|
||||
|
||||
uint32_t color_key_max; /* color key max */
|
||||
uint32_t color_key_min; /* color key min */
|
||||
|
||||
uint32_t fg_color; /* foreground color */
|
||||
uint32_t bg_color; /* background color */
|
||||
|
||||
COLOR_FILL gr_color; /* color fill use gradient */
|
||||
|
||||
line_draw_t line_draw_info;
|
||||
|
||||
FADING fading;
|
||||
|
||||
uint8_t PD_mode; /* porter duff alpha mode sel */
|
||||
|
||||
uint8_t alpha_global_value; /* global alpha value */
|
||||
|
||||
uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/
|
||||
|
||||
uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/
|
||||
|
||||
uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
|
||||
|
||||
uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
|
||||
|
||||
uint8_t endian_mode; /* 0/big endian 1/little endian*/
|
||||
|
||||
uint8_t rotate_mode; /* (enum) rotate mode */
|
||||
/* 0x0, no rotate */
|
||||
/* 0x1, rotate */
|
||||
/* 0x2, x_mirror */
|
||||
/* 0x3, y_mirror */
|
||||
|
||||
uint8_t color_fill_mode; /* 0 solid color / 1 patten color */
|
||||
|
||||
MMU mmu_info; /* mmu information */
|
||||
|
||||
uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */
|
||||
/* ([2~3] rop mode) */
|
||||
/* ([4] zero mode en) */
|
||||
/* ([5] dst alpha mode) */
|
||||
|
||||
uint8_t src_trans_mode;
|
||||
|
||||
struct sg_table *sg_src;
|
||||
struct sg_table *sg_dst;
|
||||
struct dma_buf_attachment *attach_src;
|
||||
struct dma_buf_attachment *attach_dst;
|
||||
};
|
||||
|
||||
|
||||
typedef struct TILE_INFO
|
||||
{
|
||||
int64_t matrix[4];
|
||||
|
||||
uint16_t tile_x_num; /* x axis tile num / tile size is 8x8 pixel */
|
||||
uint16_t tile_y_num; /* y axis tile num */
|
||||
|
||||
int16_t dst_x_tmp; /* dst pos x = (xstart - xoff) default value 0 */
|
||||
int16_t dst_y_tmp; /* dst pos y = (ystart - yoff) default value 0 */
|
||||
|
||||
uint16_t tile_w;
|
||||
uint16_t tile_h;
|
||||
int16_t tile_start_x_coor;
|
||||
int16_t tile_start_y_coor;
|
||||
int32_t tile_xoff;
|
||||
int32_t tile_yoff;
|
||||
|
||||
int32_t tile_temp_xstart;
|
||||
int32_t tile_temp_ystart;
|
||||
|
||||
/* src tile incr */
|
||||
int32_t x_dx;
|
||||
int32_t x_dy;
|
||||
int32_t y_dx;
|
||||
int32_t y_dy;
|
||||
|
||||
mdp_img_act dst_ctrl;
|
||||
|
||||
}
|
||||
TILE_INFO;
|
||||
|
||||
struct rga_mmu_buf_t {
|
||||
int32_t front;
|
||||
int32_t back;
|
||||
int32_t size;
|
||||
int32_t curr;
|
||||
unsigned int *buf;
|
||||
unsigned int *buf_virtual;
|
||||
|
||||
struct page **pages;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct for process session which connect to rga
|
||||
*
|
||||
* @author ZhangShengqin (2012-2-15)
|
||||
*/
|
||||
typedef struct rga_session {
|
||||
/* a linked list of data so we can access them for debugging */
|
||||
struct list_head list_session;
|
||||
/* a linked list of register data waiting for process */
|
||||
struct list_head waiting;
|
||||
/* a linked list of register data in processing */
|
||||
struct list_head running;
|
||||
/* all coommand this thread done */
|
||||
atomic_t done;
|
||||
wait_queue_head_t wait;
|
||||
pid_t pid;
|
||||
atomic_t task_running;
|
||||
atomic_t num_done;
|
||||
} rga_session;
|
||||
|
||||
struct rga_reg {
|
||||
rga_session *session;
|
||||
struct list_head session_link; /* link to rga service session */
|
||||
struct list_head status_link; /* link to register set list */
|
||||
uint32_t sys_reg[RGA_REG_CTRL_LEN];
|
||||
uint32_t cmd_reg[RGA_REG_CMD_LEN];
|
||||
|
||||
uint32_t *MMU_base;
|
||||
uint32_t MMU_len;
|
||||
//atomic_t int_enable;
|
||||
|
||||
//struct rga_req req;
|
||||
};
|
||||
|
||||
|
||||
typedef struct TILE_INFO
|
||||
{
|
||||
int64_t matrix[4];
|
||||
|
||||
uint16_t tile_x_num; /* x axis tile num / tile size is 8x8 pixel */
|
||||
uint16_t tile_y_num; /* y axis tile num */
|
||||
|
||||
int16_t dst_x_tmp; /* dst pos x = (xstart - xoff) default value 0 */
|
||||
int16_t dst_y_tmp; /* dst pos y = (ystart - yoff) default value 0 */
|
||||
|
||||
uint16_t tile_w;
|
||||
uint16_t tile_h;
|
||||
int16_t tile_start_x_coor;
|
||||
int16_t tile_start_y_coor;
|
||||
int32_t tile_xoff;
|
||||
int32_t tile_yoff;
|
||||
|
||||
int32_t tile_temp_xstart;
|
||||
int32_t tile_temp_ystart;
|
||||
|
||||
/* src tile incr */
|
||||
int32_t x_dx;
|
||||
int32_t x_dy;
|
||||
int32_t y_dx;
|
||||
int32_t y_dy;
|
||||
|
||||
mdp_img_act dst_ctrl;
|
||||
|
||||
}
|
||||
TILE_INFO;
|
||||
|
||||
struct rga_mmu_buf_t {
|
||||
int32_t front;
|
||||
int32_t back;
|
||||
int32_t size;
|
||||
int32_t curr;
|
||||
unsigned int *buf;
|
||||
unsigned int *buf_virtual;
|
||||
|
||||
struct page **pages;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct for process session which connect to rga
|
||||
*
|
||||
* @author ZhangShengqin (2012-2-15)
|
||||
*/
|
||||
typedef struct rga_session {
|
||||
/* a linked list of data so we can access them for debugging */
|
||||
struct list_head list_session;
|
||||
/* a linked list of register data waiting for process */
|
||||
struct list_head waiting;
|
||||
/* a linked list of register data in processing */
|
||||
struct list_head running;
|
||||
/* all coommand this thread done */
|
||||
atomic_t done;
|
||||
wait_queue_head_t wait;
|
||||
pid_t pid;
|
||||
atomic_t task_running;
|
||||
atomic_t num_done;
|
||||
} rga_session;
|
||||
|
||||
struct rga_reg {
|
||||
rga_session *session;
|
||||
struct list_head session_link; /* link to rga service session */
|
||||
struct list_head status_link; /* link to register set list */
|
||||
uint32_t sys_reg[RGA_REG_CTRL_LEN];
|
||||
uint32_t cmd_reg[RGA_REG_CMD_LEN];
|
||||
|
||||
uint32_t *MMU_base;
|
||||
uint32_t MMU_len;
|
||||
//atomic_t int_enable;
|
||||
|
||||
//struct rga_req req;
|
||||
|
||||
struct sg_table *sg_src;
|
||||
struct sg_table *sg_dst;
|
||||
|
||||
struct dma_buf_attachment *attach_src;
|
||||
struct dma_buf_attachment *attach_dst;
|
||||
};
|
||||
|
||||
|
||||
|
||||
typedef struct rga_service_info {
|
||||
struct mutex lock;
|
||||
struct timer_list timer; /* timer for power off */
|
||||
struct list_head waiting; /* link to link_reg in struct vpu_reg */
|
||||
struct list_head running; /* link to link_reg in struct vpu_reg */
|
||||
struct list_head done; /* link to link_reg in struct vpu_reg */
|
||||
struct list_head session; /* link to list_session in struct vpu_session */
|
||||
atomic_t total_running;
|
||||
|
||||
struct rga_reg *reg;
|
||||
|
||||
uint32_t cmd_buff[28*8];/* cmd_buff for rga */
|
||||
uint32_t *pre_scale_buf;
|
||||
unsigned long *pre_scale_buf_virtual;
|
||||
};
|
||||
|
||||
|
||||
|
||||
typedef struct rga_service_info {
|
||||
struct mutex lock;
|
||||
struct timer_list timer; /* timer for power off */
|
||||
struct list_head waiting; /* link to link_reg in struct vpu_reg */
|
||||
struct list_head running; /* link to link_reg in struct vpu_reg */
|
||||
struct list_head done; /* link to link_reg in struct vpu_reg */
|
||||
struct list_head session; /* link to list_session in struct vpu_session */
|
||||
atomic_t total_running;
|
||||
|
||||
struct rga_reg *reg;
|
||||
|
||||
uint32_t cmd_buff[28*8];/* cmd_buff for rga */
|
||||
uint32_t *pre_scale_buf;
|
||||
unsigned long *pre_scale_buf_virtual;
|
||||
atomic_t int_disable; /* 0 int enable 1 int disable */
|
||||
atomic_t cmd_num;
|
||||
atomic_t cmd_num;
|
||||
atomic_t src_format_swt;
|
||||
int last_prc_src_format;
|
||||
atomic_t rga_working;
|
||||
bool enable;
|
||||
bool enable;
|
||||
u32 dev_mode;
|
||||
|
||||
//struct rga_req req[10];
|
||||
|
||||
struct mutex mutex; // mutex
|
||||
} rga_service_info;
|
||||
|
||||
|
||||
|
||||
#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026) || defined(CONFIG_ARCH_RK312x)
|
||||
#define RGA_BASE 0x1010c000
|
||||
#elif defined(CONFIG_ARCH_RK30)
|
||||
#define RGA_BASE 0x10114000
|
||||
#endif
|
||||
|
||||
//General Registers
|
||||
#define RGA_SYS_CTRL 0x000
|
||||
#define RGA_CMD_CTRL 0x004
|
||||
#define RGA_CMD_ADDR 0x008
|
||||
#define RGA_STATUS 0x00c
|
||||
#define RGA_INT 0x010
|
||||
#define RGA_AXI_ID 0x014
|
||||
#define RGA_MMU_STA_CTRL 0x018
|
||||
#define RGA_MMU_STA 0x01c
|
||||
|
||||
//struct rga_req req[10];
|
||||
|
||||
struct mutex mutex; // mutex
|
||||
} rga_service_info;
|
||||
|
||||
|
||||
|
||||
#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026) || defined(CONFIG_ARCH_RK312x)
|
||||
#define RGA_BASE 0x1010c000
|
||||
#elif defined(CONFIG_ARCH_RK30)
|
||||
#define RGA_BASE 0x10114000
|
||||
#endif
|
||||
|
||||
//General Registers
|
||||
#define RGA_SYS_CTRL 0x000
|
||||
#define RGA_CMD_CTRL 0x004
|
||||
#define RGA_CMD_ADDR 0x008
|
||||
#define RGA_STATUS 0x00c
|
||||
#define RGA_INT 0x010
|
||||
#define RGA_AXI_ID 0x014
|
||||
#define RGA_MMU_STA_CTRL 0x018
|
||||
#define RGA_MMU_STA 0x01c
|
||||
#define RGA_VERSION 0x028
|
||||
|
||||
//Command code start
|
||||
#define RGA_MODE_CTRL 0x100
|
||||
|
||||
//Source Image Registers
|
||||
#define RGA_SRC_Y_MST 0x104
|
||||
#define RGA_SRC_CB_MST 0x108
|
||||
#define RGA_MASK_READ_MST 0x108 //repeat
|
||||
#define RGA_SRC_CR_MST 0x10c
|
||||
#define RGA_SRC_VIR_INFO 0x110
|
||||
#define RGA_SRC_ACT_INFO 0x114
|
||||
#define RGA_SRC_X_PARA 0x118
|
||||
#define RGA_SRC_Y_PARA 0x11c
|
||||
#define RGA_SRC_TILE_XINFO 0x120
|
||||
#define RGA_SRC_TILE_YINFO 0x124
|
||||
#define RGA_SRC_TILE_H_INCR 0x128
|
||||
#define RGA_SRC_TILE_V_INCR 0x12c
|
||||
#define RGA_SRC_TILE_OFFSETX 0x130
|
||||
#define RGA_SRC_TILE_OFFSETY 0x134
|
||||
#define RGA_SRC_BG_COLOR 0x138
|
||||
#define RGA_SRC_FG_COLOR 0x13c
|
||||
#define RGA_LINE_DRAWING_COLOR 0x13c //repeat
|
||||
#define RGA_SRC_TR_COLOR0 0x140
|
||||
#define RGA_CP_GR_A 0x140 //repeat
|
||||
#define RGA_SRC_TR_COLOR1 0x144
|
||||
#define RGA_CP_GR_B 0x144 //repeat
|
||||
|
||||
#define RGA_LINE_DRAW 0x148
|
||||
#define RGA_PAT_START_POINT 0x148 //repeat
|
||||
|
||||
//Destination Image Registers
|
||||
#define RGA_DST_MST 0x14c
|
||||
#define RGA_LUT_MST 0x14c //repeat
|
||||
#define RGA_PAT_MST 0x14c //repeat
|
||||
#define RGA_LINE_DRAWING_MST 0x14c //repeat
|
||||
|
||||
#define RGA_DST_VIR_INFO 0x150
|
||||
|
||||
#define RGA_DST_CTR_INFO 0x154
|
||||
#define RGA_LINE_DRAW_XY_INFO 0x154 //repeat
|
||||
|
||||
//Alpha/ROP Registers
|
||||
#define RGA_ALPHA_CON 0x158
|
||||
|
||||
#define RGA_PAT_CON 0x15c
|
||||
#define RGA_DST_VIR_WIDTH_PIX 0x15c //repeat
|
||||
|
||||
#define RGA_ROP_CON0 0x160
|
||||
#define RGA_CP_GR_G 0x160 //repeat
|
||||
#define RGA_PRESCL_CB_MST 0x160 //repeat
|
||||
|
||||
#define RGA_ROP_CON1 0x164
|
||||
#define RGA_CP_GR_R 0x164 //repeat
|
||||
#define RGA_PRESCL_CR_MST 0x164 //repeat
|
||||
|
||||
//MMU Register
|
||||
#define RGA_FADING_CON 0x168
|
||||
#define RGA_MMU_CTRL 0x168 //repeat
|
||||
|
||||
#define RGA_MMU_TBL 0x16c //repeat
|
||||
|
||||
#define RGA_YUV_OUT_CFG 0x170
|
||||
#define RGA_DST_UV_MST 0x174
|
||||
|
||||
|
||||
#define RGA_BLIT_COMPLETE_EVENT 1
|
||||
|
||||
long rga_ioctl_kernel(struct rga_req *req);
|
||||
|
||||
#endif /*_RK29_IPP_DRIVER_H_*/
|
||||
|
||||
//Command code start
|
||||
#define RGA_MODE_CTRL 0x100
|
||||
|
||||
//Source Image Registers
|
||||
#define RGA_SRC_Y_MST 0x104
|
||||
#define RGA_SRC_CB_MST 0x108
|
||||
#define RGA_MASK_READ_MST 0x108 //repeat
|
||||
#define RGA_SRC_CR_MST 0x10c
|
||||
#define RGA_SRC_VIR_INFO 0x110
|
||||
#define RGA_SRC_ACT_INFO 0x114
|
||||
#define RGA_SRC_X_PARA 0x118
|
||||
#define RGA_SRC_Y_PARA 0x11c
|
||||
#define RGA_SRC_TILE_XINFO 0x120
|
||||
#define RGA_SRC_TILE_YINFO 0x124
|
||||
#define RGA_SRC_TILE_H_INCR 0x128
|
||||
#define RGA_SRC_TILE_V_INCR 0x12c
|
||||
#define RGA_SRC_TILE_OFFSETX 0x130
|
||||
#define RGA_SRC_TILE_OFFSETY 0x134
|
||||
#define RGA_SRC_BG_COLOR 0x138
|
||||
#define RGA_SRC_FG_COLOR 0x13c
|
||||
#define RGA_LINE_DRAWING_COLOR 0x13c //repeat
|
||||
#define RGA_SRC_TR_COLOR0 0x140
|
||||
#define RGA_CP_GR_A 0x140 //repeat
|
||||
#define RGA_SRC_TR_COLOR1 0x144
|
||||
#define RGA_CP_GR_B 0x144 //repeat
|
||||
|
||||
#define RGA_LINE_DRAW 0x148
|
||||
#define RGA_PAT_START_POINT 0x148 //repeat
|
||||
|
||||
//Destination Image Registers
|
||||
#define RGA_DST_MST 0x14c
|
||||
#define RGA_LUT_MST 0x14c //repeat
|
||||
#define RGA_PAT_MST 0x14c //repeat
|
||||
#define RGA_LINE_DRAWING_MST 0x14c //repeat
|
||||
|
||||
#define RGA_DST_VIR_INFO 0x150
|
||||
|
||||
#define RGA_DST_CTR_INFO 0x154
|
||||
#define RGA_LINE_DRAW_XY_INFO 0x154 //repeat
|
||||
|
||||
//Alpha/ROP Registers
|
||||
#define RGA_ALPHA_CON 0x158
|
||||
|
||||
#define RGA_PAT_CON 0x15c
|
||||
#define RGA_DST_VIR_WIDTH_PIX 0x15c //repeat
|
||||
|
||||
#define RGA_ROP_CON0 0x160
|
||||
#define RGA_CP_GR_G 0x160 //repeat
|
||||
#define RGA_PRESCL_CB_MST 0x160 //repeat
|
||||
|
||||
#define RGA_ROP_CON1 0x164
|
||||
#define RGA_CP_GR_R 0x164 //repeat
|
||||
#define RGA_PRESCL_CR_MST 0x164 //repeat
|
||||
|
||||
//MMU Register
|
||||
#define RGA_FADING_CON 0x168
|
||||
#define RGA_MMU_CTRL 0x168 //repeat
|
||||
|
||||
#define RGA_MMU_TBL 0x16c //repeat
|
||||
|
||||
#define RGA_YUV_OUT_CFG 0x170
|
||||
#define RGA_DST_UV_MST 0x174
|
||||
|
||||
|
||||
#define RGA_BLIT_COMPLETE_EVENT 1
|
||||
|
||||
long rga_ioctl_kernel(struct rga_req *req);
|
||||
|
||||
#endif /*_RK29_IPP_DRIVER_H_*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,24 +1,24 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __RGA_MMU_INFO_H__
|
||||
#define __RGA_MMU_INFO_H__
|
||||
|
||||
#ifndef __RGA_MMU_INFO_H__
|
||||
#define __RGA_MMU_INFO_H__
|
||||
|
||||
#include "rga.h"
|
||||
#include "RGA_API.h"
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(X, Y) ((X)<(Y)?(X):(Y))
|
||||
#endif
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(X, Y) ((X)>(Y)?(X):(Y))
|
||||
#endif
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(X, Y) ((X)<(Y)?(X):(Y))
|
||||
#endif
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(X, Y) ((X)>(Y)?(X):(Y))
|
||||
#endif
|
||||
|
||||
extern struct rga_drvdata *drvdata;
|
||||
|
||||
void rga_dma_flush_range(void *pstart, void *pend);
|
||||
int rga_set_mmu_info(struct rga_reg *reg, struct rga_req *req);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
int rga_set_mmu_info(struct rga_reg *reg, struct rga_req *req);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,467 +1,467 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __REG_INFO_H__
|
||||
#define __REG_INFO_H__
|
||||
|
||||
|
||||
//#include "chip_register.h"
|
||||
|
||||
//#include "rga_struct.h"
|
||||
#include "rga.h"
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(X, Y) ((X)<(Y)?(X):(Y))
|
||||
#endif
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(X, Y) ((X)>(Y)?(X):(Y))
|
||||
#endif
|
||||
|
||||
#ifndef ABS
|
||||
#define ABS(X) (((X) < 0) ? (-(X)) : (X))
|
||||
#endif
|
||||
|
||||
#ifndef CLIP
|
||||
#define CLIP(x, a, b) ((x) < (a)) ? (a) : (((x) > (b)) ? (b) : (x))
|
||||
#endif
|
||||
|
||||
//RGA register map
|
||||
|
||||
//General Registers
|
||||
#define rRGA_SYS_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_SYS_CTRL))
|
||||
#define rRGA_CMD_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_CMD_CTRL))
|
||||
#define rRGA_CMD_ADDR (*(volatile uint32_t *)(RGA_BASE + RGA_CMD_ADDR))
|
||||
#define rRGA_STATUS (*(volatile uint32_t *)(RGA_BASE + RGA_STATUS))
|
||||
#define rRGA_INT (*(volatile uint32_t *)(RGA_BASE + RGA_INT))
|
||||
#define rRGA_AXI_ID (*(volatile uint32_t *)(RGA_BASE + RGA_AXI_ID))
|
||||
#define rRGA_MMU_STA_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_STA_CTRL))
|
||||
#define rRGA_MMU_STA (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_STA))
|
||||
|
||||
//Command code start
|
||||
#define rRGA_MODE_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_MODE_CTRL))
|
||||
|
||||
//Source Image Registers
|
||||
#define rRGA_SRC_Y_MST (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_Y_MST))
|
||||
#define rRGA_SRC_CB_MST (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_CB_MST))
|
||||
#define rRGA_MASK_READ_MST (*(volatile uint32_t *)(RGA_BASE + RGA_MASK_READ_MST)) //repeat
|
||||
#define rRGA_SRC_CR_MST (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_CR_MST))
|
||||
#define rRGA_SRC_VIR_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_VIR_INFO))
|
||||
#define rRGA_SRC_ACT_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_ACT_INFO))
|
||||
#define rRGA_SRC_X_PARA (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_X_PARA))
|
||||
#define rRGA_SRC_Y_PARA (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_Y_PARA))
|
||||
#define rRGA_SRC_TILE_XINFO (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_XINFO))
|
||||
#define rRGA_SRC_TILE_YINFO (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_YINFO))
|
||||
#define rRGA_SRC_TILE_H_INCR (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_H_INCR))
|
||||
#define rRGA_SRC_TILE_V_INCR (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_V_INCR))
|
||||
#define rRGA_SRC_TILE_OFFSETX (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_OFFSETX))
|
||||
#define rRGA_SRC_TILE_OFFSETY (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_OFFSETY))
|
||||
#define rRGA_SRC_BG_COLOR (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_BG_COLOR))
|
||||
#define rRGA_SRC_FG_COLOR (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_FG_COLOR))
|
||||
#define rRGA_LINE_DRAWING_COLOR (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAWING_COLOR)) //repeat
|
||||
#define rRGA_SRC_TR_COLOR0 (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TR_COLOR0))
|
||||
#define rRGA_CP_GR_A (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_A)) //repeat
|
||||
#define rRGA_SRC_TR_COLOR1 (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TR_COLOR1))
|
||||
#define rRGA_CP_GR_B (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_B)) //repeat
|
||||
|
||||
#define rRGA_LINE_DRAW (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAW))
|
||||
#define rRGA_PAT_START_POINT (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_START_POINT)) //repeat
|
||||
|
||||
//Destination Image Registers
|
||||
#define rRGA_DST_MST (*(volatile uint32_t *)(RGA_BASE + RGA_DST_MST))
|
||||
#define rRGA_LUT_MST (*(volatile uint32_t *)(RGA_BASE + RGA_LUT_MST)) //repeat
|
||||
#define rRGA_PAT_MST (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_MST)) //repeat
|
||||
#define rRGA_LINE_DRAWING_MST (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAWING_MST)) //repeat
|
||||
|
||||
#define rRGA_DST_VIR_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_DST_VIR_INFO))
|
||||
|
||||
#define rRGA_DST_CTR_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_DST_CTR_INFO))
|
||||
#define rRGA_LINE_DRAW_XY_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAW_XY_INFO)) //repeat
|
||||
|
||||
//Alpha/ROP Registers
|
||||
#define rRGA_ALPHA_CON (*(volatile uint32_t *)(RGA_BASE + RGA_ALPHA_CON))
|
||||
#define rRGA_FADING_CON (*(volatile uint32_t *)(RGA_BASE + RGA_FADING_CON))
|
||||
|
||||
#define rRGA_PAT_CON (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_CON))
|
||||
#define rRGA_DST_VIR_WIDTH_PIX (*(volatile uint32_t *)(RGA_BASE + RGA_DST_VIR_WIDTH_PIX)) //repeat
|
||||
|
||||
#define rRGA_ROP_CON0 (*(volatile uint32_t *)(RGA_BASE + RGA_ROP_CON0))
|
||||
#define rRGA_CP_GR_G (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_G)) //repeat
|
||||
#define rRGA_PRESCL_CB_MST (*(volatile uint32_t *)(RGA_BASE + RGA_PRESCL_CB_MST)) //repeat
|
||||
|
||||
#define rRGA_ROP_CON1 (*(volatile uint32_t *)(RGA_BASE + RGA_ROP_CON1))
|
||||
#define rRGA_CP_GR_R (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_R)) //repeat
|
||||
#define rRGA_PRESCL_CR_MST (*(volatile uint32_t *)(RGA_BASE + RGA_PRESCL_CR_MST)) //repeat
|
||||
|
||||
//MMU Register
|
||||
#define rRGA_MMU_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_CTRL))
|
||||
|
||||
|
||||
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
//reg detail definition
|
||||
//-----------------------------------------------------------------
|
||||
/*RGA_SYS_CTRL*/
|
||||
#define m_RGA_SYS_CTRL_CMD_MODE ( 1<<2 )
|
||||
#define m_RGA_SYS_CTRL_OP_ST_SLV ( 1<<1 )
|
||||
#define m_RGA_sys_CTRL_SOFT_RESET ( 1<<0 )
|
||||
|
||||
#define s_RGA_SYS_CTRL_CMD_MODE(x) ( (x&0x1)<<2 )
|
||||
#define s_RGA_SYS_CTRL_OP_ST_SLV(x) ( (x&0x1)<<1 )
|
||||
#define s_RGA_sys_CTRL_SOFT_RESET(x) ( (x&0x1)<<0 )
|
||||
|
||||
|
||||
/*RGA_CMD_CTRL*/
|
||||
#define m_RGA_CMD_CTRL_CMD_INCR_NUM ( 0x3ff<<3 )
|
||||
#define m_RGA_CMD_CTRL_CMD_STOP_MODE ( 1<<2 )
|
||||
#define m_RGA_CMD_CTRL_CMD_INCR_VALID ( 1<<1 )
|
||||
#define m_RGA_CMD_CTRL_CMD_LINE_FET_ST ( 1<<0 )
|
||||
|
||||
#define s_RGA_CMD_CTRL_CMD_INCR_NUM(x) ( (x&0x3ff)<<3 )
|
||||
#define s_RGA_CMD_CTRL_CMD_STOP_MODE(x) ( (x&0x1)<<2 )
|
||||
#define s_RGA_CMD_CTRL_CMD_INCR_VALID(x) ( (x&0x1)<<1 )
|
||||
#define s_RGA_CMD_CTRL_CMD_LINE_FET_ST(x) ( (x*0x1)<<0 )
|
||||
|
||||
|
||||
/*RGA_STATUS*/
|
||||
#define m_RGA_CMD_STATUS_CMD_TOTAL_NUM ( 0xfff<<20 )
|
||||
#define m_RGA_CMD_STATUS_NOW_CMD_NUM ( 0xfff<<8 )
|
||||
#define m_RGA_CMD_STATUS_ENGINE_STATUS ( 1<<0 )
|
||||
|
||||
|
||||
/*RGA_INT*/
|
||||
#define m_RGA_INT_ALL_CMD_DONE_INT_EN ( 1<<10 )
|
||||
#define m_RGA_INT_MMU_INT_EN ( 1<<9 )
|
||||
#define m_RGA_INT_ERROR_INT_EN ( 1<<8 )
|
||||
#define m_RGA_INT_NOW_CMD_DONE_INT_CLEAR ( 1<<7 )
|
||||
#define m_RGA_INT_ALL_CMD_DONE_INT_CLEAR ( 1<<6 )
|
||||
#define m_RGA_INT_MMU_INT_CLEAR ( 1<<5 )
|
||||
#define m_RGA_INT_ERROR_INT_CLEAR ( 1<<4 )
|
||||
#define m_RGA_INT_NOW_CMD_DONE_INT_FLAG ( 1<<3 )
|
||||
#define m_RGA_INT_ALL_CMD_DONE_INT_FLAG ( 1<<2 )
|
||||
#define m_RGA_INT_MMU_INT_FLAG ( 1<<1 )
|
||||
#define m_RGA_INT_ERROR_INT_FLAG ( 1<<0 )
|
||||
|
||||
#define s_RGA_INT_ALL_CMD_DONE_INT_EN(x) ( (x&0x1)<<10 )
|
||||
#define s_RGA_INT_MMU_INT_EN(x) ( (x&0x1)<<9 )
|
||||
#define s_RGA_INT_ERROR_INT_EN(x) ( (x&0x1)<<8 )
|
||||
#define s_RGA_INT_NOW_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<7 )
|
||||
#define s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<6 )
|
||||
#define s_RGA_INT_MMU_INT_CLEAR(x) ( (x&0x1)<<5 )
|
||||
#define s_RGA_INT_ERROR_INT_CLEAR(x) ( (x&0x1)<<4 )
|
||||
|
||||
|
||||
/*RGA_AXI_ID*/
|
||||
#define m_RGA_AXI_ID_MMU_READ ( 3<<30 )
|
||||
#define m_RGA_AXI_ID_MMU_WRITE ( 3<<28 )
|
||||
#define m_RGA_AXI_ID_MASK_READ ( 0xf<<24 )
|
||||
#define m_RGA_AXI_ID_CMD_FET ( 0xf<<20 )
|
||||
#define m_RGA_AXI_ID_DST_WRITE ( 0xf<<16 )
|
||||
#define m_RGA_AXI_ID_DST_READ ( 0xf<<12 )
|
||||
#define m_RGA_AXI_ID_SRC_CR_READ ( 0xf<<8 )
|
||||
#define m_RGA_AXI_ID_SRC_CB_READ ( 0xf<<4 )
|
||||
#define m_RGA_AXI_ID_SRC_Y_READ ( 0xf<<0 )
|
||||
|
||||
#define s_RGA_AXI_ID_MMU_READ(x) ( (x&0x3)<<30 )
|
||||
#define s_RGA_AXI_ID_MMU_WRITE(x) ( (x&0x3)<<28 )
|
||||
#define s_RGA_AXI_ID_MASK_READ(x) ( (x&0xf)<<24 )
|
||||
#define s_RGA_AXI_ID_CMD_FET(x) ( (x&0xf)<<20 )
|
||||
#define s_RGA_AXI_ID_DST_WRITE(x) ( (x&0xf)<<16 )
|
||||
#define s_RGA_AXI_ID_DST_READ(x) ( (x&0xf)<<12 )
|
||||
#define s_RGA_AXI_ID_SRC_CR_READ(x) ( (x&0xf)<<8 )
|
||||
#define s_RGA_AXI_ID_SRC_CB_READ(x) ( (x&0xf)<<4 )
|
||||
#define s_RGA_AXI_ID_SRC_Y_READ(x) ( (x&0xf)<<0 )
|
||||
|
||||
|
||||
/*RGA_MMU_STA_CTRL*/
|
||||
#define m_RGA_MMU_STA_CTRL_TLB_STA_CLEAR ( 1<<3 )
|
||||
#define m_RGA_MMU_STA_CTRL_TLB_STA_RESUME ( 1<<2 )
|
||||
#define m_RGA_MMU_STA_CTRL_TLB_STA_PAUSE ( 1<<1 )
|
||||
#define m_RGA_MMU_STA_CTRL_TLB_STA_EN ( 1<<0 )
|
||||
|
||||
#define s_RGA_MMU_STA_CTRL_TLB_STA_CLEAR(x) ( (x&0x1)<<3 )
|
||||
#define s_RGA_MMU_STA_CTRL_TLB_STA_RESUME(x) ( (x&0x1)<<2 )
|
||||
#define s_RGA_MMU_STA_CTRL_TLB_STA_PAUSE(x) ( (x&0x1)<<1 )
|
||||
#define s_RGA_MMU_STA_CTRL_TLB_STA_EN(x) ( (x&0x1)<<0 )
|
||||
|
||||
|
||||
|
||||
/* RGA_MODE_CTRL */
|
||||
#define m_RGA_MODE_CTRL_2D_RENDER_MODE ( 7<<0 )
|
||||
#define m_RGA_MODE_CTRL_SRC_RGB_PACK ( 1<<3 )
|
||||
#define m_RGA_MODE_CTRL_SRC_FORMAT ( 15<<4 )
|
||||
#define m_RGA_MODE_CTRL_SRC_RB_SWAP ( 1<<8 )
|
||||
#define m_RGA_MODE_CTRL_SRC_ALPHA_SWAP ( 1<<9 )
|
||||
#define m_RGA_MODE_CTRL_SRC_UV_SWAP_MODE ( 1<<10 )
|
||||
#define m_RGA_MODE_CTRL_YUV2RGB_CON_MODE ( 3<<11 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TRANS_MODE (0x1f<<13 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_MODE ( 1<<13 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_R_EN ( 1<<14 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_G_EN ( 1<<15 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_B_EN ( 1<<16 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_A_EN ( 1<<17 )
|
||||
#define m_RGA_MODE_CTRL_ROTATE_MODE ( 3<<18 )
|
||||
#define m_RGA_MODE_CTRL_SCALE_MODE ( 3<<20 )
|
||||
#define m_RGA_MODE_CTRL_PAT_SEL ( 1<<22 )
|
||||
#define m_RGA_MODE_CTRL_DST_FORMAT ( 3<<23 )
|
||||
#define m_RGA_MODE_CTRL_DST_RGB_PACK ( 1<<25 )
|
||||
#define m_RGA_MODE_CTRL_DST_RB_SWAP ( 1<<26 )
|
||||
#define m_RGA_MODE_CTRL_DST_ALPHA_SWAP ( 1<<27 )
|
||||
#define m_RGA_MODE_CTRL_LUT_ENDIAN_MODE ( 1<<28 )
|
||||
#define m_RGA_MODE_CTRL_CMD_INT_ENABLE ( 1<<29 )
|
||||
#define m_RGA_MODE_CTRL_ZERO_MODE_ENABLE ( 1<<30 )
|
||||
#define m_RGA_MODE_CTRL_DST_ALPHA_ENABLE ( 1<<30 )
|
||||
|
||||
|
||||
|
||||
#define s_RGA_MODE_CTRL_2D_RENDER_MODE(x) ( (x&0x7)<<0 )
|
||||
#define s_RGA_MODE_CTRL_SRC_RGB_PACK(x) ( (x&0x1)<<3 )
|
||||
#define s_RGA_MODE_CTRL_SRC_FORMAT(x) ( (x&0xf)<<4 )
|
||||
#define s_RGA_MODE_CTRL_SRC_RB_SWAP(x) ( (x&0x1)<<8 )
|
||||
#define s_RGA_MODE_CTRL_SRC_ALPHA_SWAP(x) ( (x&0x1)<<9 )
|
||||
#define s_RGA_MODE_CTRL_SRC_UV_SWAP_MODE(x) ( (x&0x1)<<10 )
|
||||
#define s_RGA_MODE_CTRL_YUV2RGB_CON_MODE(x) ( (x&0x3)<<11 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TRANS_MODE(x) ( (x&0x1f)<<13 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_MODE(x) ( (x&0x1)<<13 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_R_EN(x) ( (x&0x1)<<14 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_G_EN(x) ( (x&0x1)<<15 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_B_EN(x) ( (x&0x1)<<16 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_A_EN(x) ( (x&0x1)<<17 )
|
||||
#define s_RGA_MODE_CTRL_ROTATE_MODE(x) ( (x&0x3)<<18 )
|
||||
#define s_RGA_MODE_CTRL_SCALE_MODE(x) ( (x&0x3)<<20 )
|
||||
#define s_RGA_MODE_CTRL_PAT_SEL(x) ( (x&0x1)<<22 )
|
||||
#define s_RGA_MODE_CTRL_DST_FORMAT(x) ( (x&0x3)<<23 )
|
||||
#define s_RGA_MODE_CTRL_DST_RGB_PACK(x) ( (x&0x1)<<25 )
|
||||
#define s_RGA_MODE_CTRL_DST_RB_SWAP(x) ( (x&0x1)<<26 )
|
||||
#define s_RGA_MODE_CTRL_DST_ALPHA_SWAP(x) ( (x&0x1)<<27 )
|
||||
#define s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(x) ( (x&0x1)<<28 )
|
||||
#define s_RGA_MODE_CTRL_CMD_INT_ENABLE(x) ( (x&0x1)<<29 )
|
||||
#define s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(x) ( (x&0x1)<<30 )
|
||||
#define s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(x) ( (x&0x1)<<31 )
|
||||
|
||||
|
||||
|
||||
/* RGA_LINE_DRAW */
|
||||
#define m_RGA_LINE_DRAW_MAJOR_WIDTH ( 0x7ff<<0 )
|
||||
#define m_RGA_LINE_DRAW_LINE_DIRECTION ( 0x1<<11)
|
||||
#define m_RGA_LINE_DRAW_LINE_WIDTH ( 0xf<<12)
|
||||
#define m_RGA_LINE_DRAW_INCR_VALUE ( 0xfff<<16)
|
||||
#define m_RGA_LINE_DRAW_DIR_MAJOR ( 0x1<<28)
|
||||
#define m_RGA_LINE_DRAW_DIR_SEMI_MAJOR ( 0x1<<29)
|
||||
#define m_RGA_LINE_DRAW_LAST_POINT ( 0x1<<30)
|
||||
#define m_RGA_LINE_DRAW_ANTI_ALISING ( 0x1<<31)
|
||||
|
||||
#define s_RGA_LINE_DRAW_MAJOR_WIDTH(x) (((x)&0x7ff)<<0 )
|
||||
#define s_RGA_LINE_DRAW_LINE_DIRECTION(x) ( ((x)&0x1)<<11)
|
||||
#define s_RGA_LINE_DRAW_LINE_WIDTH(x) ( ((x)&0xf)<<12)
|
||||
#define s_RGA_LINE_DRAW_INCR_VALUE(x) (((x)&0xfff)<<16)
|
||||
#define s_RGA_LINE_DRAW_DIR_MAJOR(x) ( ((x)&0x1)<<28)
|
||||
#define s_RGA_LINE_DRAW_DIR_SEMI_MAJOR(x) ( ((x)&0x1)<<29)
|
||||
#define s_RGA_LINE_DRAW_LAST_POINT(x) ( ((x)&0x1)<<30)
|
||||
#define s_RGA_LINE_DRAW_ANTI_ALISING(x) ( ((x)&0x1)<<31)
|
||||
|
||||
|
||||
/* RGA_ALPHA_CON */
|
||||
#define m_RGA_ALPHA_CON_ENABLE ( 0x1<<0 )
|
||||
#define m_RGA_ALPHA_CON_A_OR_R_SEL ( 0x1<<1 )
|
||||
#define m_RGA_ALPHA_CON_ALPHA_MODE ( 0x3<<2 )
|
||||
#define m_RGA_ALPHA_CON_PD_MODE ( 0xf<<4 )
|
||||
#define m_RGA_ALPHA_CON_SET_CONSTANT_VALUE (0xff<<8 )
|
||||
#define m_RGA_ALPHA_CON_PD_M_SEL ( 0x1<<16)
|
||||
#define m_RGA_ALPHA_CON_FADING_ENABLE ( 0x1<<17)
|
||||
#define m_RGA_ALPHA_CON_ROP_MODE_SEL ( 0x3<<18)
|
||||
#define m_RGA_ALPHA_CON_CAL_MODE_SEL ( 0x1<<28)
|
||||
#define m_RGA_ALPHA_CON_DITHER_ENABLE ( 0x1<<29)
|
||||
#define m_RGA_ALPHA_CON_GRADIENT_CAL_MODE ( 0x1<<30)
|
||||
#define m_RGA_ALPHA_CON_AA_SEL ( 0x1<<31)
|
||||
|
||||
#define s_RGA_ALPHA_CON_ENABLE(x) ( (x&0x1)<<0 )
|
||||
#define s_RGA_ALPHA_CON_A_OR_R_SEL(x) ( (x&0x1)<<1 )
|
||||
#define s_RGA_ALPHA_CON_ALPHA_MODE(x) ( (x&0x3)<<2 )
|
||||
#define s_RGA_ALPHA_CON_PD_MODE(x) ( (x&0xf)<<4 )
|
||||
#define s_RGA_ALPHA_CON_SET_CONSTANT_VALUE(x) ((x&0xff)<<8 )
|
||||
#define s_RGA_ALPHA_CON_PD_M_SEL(x) ( (x&0x1)<<16)
|
||||
#define s_RGA_ALPHA_CON_FADING_ENABLE(x) ( (x&0x1)<<17)
|
||||
#define s_RGA_ALPHA_CON_ROP_MODE_SEL(x) ( (x&0x3)<<18)
|
||||
#define s_RGA_ALPHA_CON_CAL_MODE_SEL(x) ( (x&0x1)<<28)
|
||||
#define s_RGA_ALPHA_CON_DITHER_ENABLE(x) ( (x&0x1)<<29)
|
||||
#define s_RGA_ALPHA_CON_GRADIENT_CAL_MODE(x) ( (x&0x1)<<30)
|
||||
#define s_RGA_ALPHA_CON_AA_SEL(x) ( (x&0x1)<<31)
|
||||
|
||||
|
||||
/* blur sharp mode */
|
||||
#define m_RGA_BLUR_SHARP_FILTER_MODE ( 0x1<<25 )
|
||||
#define m_RGA_BLUR_SHARP_FILTER_TYPE ( 0x3<<26 )
|
||||
|
||||
#define s_RGA_BLUR_SHARP_FILTER_MODE(x) ( (x&0x1)<<25 )
|
||||
#define s_RGA_BLUR_SHARP_FILTER_TYPE(x) ( (x&0x3)<<26 )
|
||||
|
||||
|
||||
/* pre scale mode */
|
||||
#define m_RGA_PRE_SCALE_HOR_RATIO ( 0x3 <<20 )
|
||||
#define m_RGA_PRE_SCALE_VER_RATIO ( 0x3 <<22 )
|
||||
#define m_RGA_PRE_SCALE_OUTPUT_FORMAT ( 0x1 <<24 )
|
||||
|
||||
#define s_RGA_PRE_SCALE_HOR_RATIO(x) ( (x&0x3) <<20 )
|
||||
#define s_RGA_PRE_SCALE_VER_RATIO(x) ( (x&0x3) <<22 )
|
||||
#define s_RGA_PRE_SCALE_OUTPUT_FORMAT(x) ( (x&0x1) <<24 )
|
||||
|
||||
|
||||
|
||||
/* RGA_MMU_CTRL*/
|
||||
#define m_RGA_MMU_CTRL_TLB_ADDR ( 0xffffffff<<0)
|
||||
#define m_RGA_MMU_CTRL_PAGE_TABLE_SIZE ( 0x3<<4 )
|
||||
#define m_RGA_MMU_CTRL_MMU_ENABLE ( 0x1<<0 )
|
||||
#define m_RGA_MMU_CTRL_SRC_FLUSH ( 0x1<<1 )
|
||||
#define m_RGA_MMU_CTRL_DST_FLUSH ( 0x1<<2 )
|
||||
#define m_RGA_MMU_CTRL_CMD_CHAN_FLUSH ( 0x1<<3 )
|
||||
|
||||
#define s_RGA_MMU_CTRL_TLB_ADDR(x) ((x&0xffffffff))
|
||||
#define s_RGA_MMU_CTRL_PAGE_TABLE_SIZE(x) ((x&0x3)<<4)
|
||||
#define s_RGA_MMU_CTRL_MMU_ENABLE(x) ((x&0x1)<<0)
|
||||
#define s_RGA_MMU_CTRL_SRC_FLUSH(x) ((x&0x1)<<1)
|
||||
#define s_RGA_MMU_CTRL_DST_FLUSH(x) ((x&0x1)<<2)
|
||||
#define s_RGA_MMU_CTRL_CMD_CHAN_FLUSH(x) ((x&0x1)<<3)
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
#define RGA_MODE_CTRL_OFFSET 0x0
|
||||
#define RGA_SRC_Y_MST_OFFSET 0x4
|
||||
#define RGA_SRC_CB_MST_OFFSET 0x8
|
||||
#define RGA_SRC_CR_MST_OFFSET 0xc
|
||||
#define RGA_SRC_VIR_INFO_OFFSET 0x10
|
||||
#define RGA_SRC_ACT_INFO_OFFSET 0x14
|
||||
#define RGA_SRC_X_PARA_OFFSET 0x18
|
||||
#define RGA_SRC_Y_PARA_OFFSET 0x1c
|
||||
#define RGA_SRC_TILE_XINFO_OFFSET 0x20
|
||||
#define RGA_SRC_TILE_YINFO_OFFSET 0x24
|
||||
#define RGA_SRC_TILE_H_INCR_OFFSET 0x28
|
||||
#define RGA_SRC_TILE_V_INCR_OFFSET 0x2c
|
||||
#define RGA_SRC_TILE_OFFSETX_OFFSET 0x30
|
||||
#define RGA_SRC_TILE_OFFSETY_OFFSET 0x34
|
||||
#define RGA_SRC_BG_COLOR_OFFSET 0x38
|
||||
|
||||
#define RGA_SRC_FG_COLOR_OFFSET 0x3c
|
||||
#define RGA_LINE_DRAWING_COLOR_OFFSET 0x3c
|
||||
|
||||
#define RGA_SRC_TR_COLOR0_OFFSET 0x40
|
||||
#define RGA_CP_GR_A_OFFSET 0x40 //repeat
|
||||
|
||||
#define RGA_SRC_TR_COLOR1_OFFSET 0x44
|
||||
#define RGA_CP_GR_B_OFFSET 0x44 //repeat
|
||||
|
||||
#define RGA_LINE_DRAW_OFFSET 0x48
|
||||
#define RGA_PAT_START_POINT_OFFSET 0x48 //repeat
|
||||
|
||||
#define RGA_DST_MST_OFFSET 0x4c
|
||||
#define RGA_LUT_MST_OFFSET 0x4c //repeat
|
||||
#define RGA_PAT_MST_OFFSET 0x4c //repeat
|
||||
#define RGA_LINE_DRAWING_MST_OFFSET 0x4c //repeat
|
||||
|
||||
#define RGA_DST_VIR_INFO_OFFSET 0x50
|
||||
|
||||
#define RGA_DST_CTR_INFO_OFFSET 0x54
|
||||
#define RGA_LINE_DRAW_XY_INFO_OFFSET 0x54 //repeat
|
||||
|
||||
#define RGA_ALPHA_CON_OFFSET 0x58
|
||||
#define RGA_FADING_CON_OFFSET 0x5c
|
||||
|
||||
#define RGA_PAT_CON_OFFSET 0x60
|
||||
#define RGA_LINE_DRAWING_WIDTH_OFFSET 0x60 //repeat
|
||||
|
||||
#define RGA_ROP_CON0_OFFSET 0x64
|
||||
#define RGA_CP_GR_G_OFFSET 0x64 //repeat
|
||||
#define RGA_PRESCL_CB_MST_OFFSET 0x64 //repeat
|
||||
|
||||
#define RGA_ROP_CON1_OFFSET 0x68
|
||||
#define RGA_CP_GR_R_OFFSET 0x68 //repeat
|
||||
#define RGA_PRESCL_CR_MST_OFFSET 0x68 //repeat
|
||||
|
||||
#define RGA_MMU_CTRL_OFFSET 0x6c
|
||||
|
||||
|
||||
#define RGA_SYS_CTRL_OFFSET 0x000
|
||||
#define RGA_CMD_CTRL_OFFSET 0x004
|
||||
#define RGA_CMD_ADDR_OFFSET 0x008
|
||||
#define RGA_STATUS_OFFSET 0x00c
|
||||
#define RGA_INT_OFFSET 0x010
|
||||
#define RGA_AXI_ID_OFFSET 0x014
|
||||
#define RGA_MMU_STA_CTRL_OFFSET 0x018
|
||||
#define RGA_MMU_STA_OFFSET 0x01c
|
||||
*/
|
||||
//hxx
|
||||
|
||||
#define RGA_SYS_CTRL_OFFSET (RGA_SYS_CTRL-0x100)
|
||||
#define RGA_CMD_CTRL_OFFSET (RGA_CMD_CTRL-0x100)
|
||||
#define RGA_CMD_ADDR_OFFSET (RGA_CMD_ADDR-0x100)
|
||||
#define RGA_STATUS_OFFSET (RGA_STATUS-0x100)
|
||||
#define RGA_INT_OFFSET (RGA_INT-0x100)
|
||||
#define RGA_AXI_ID_OFFSET (RGA_AXI_ID-0x100)
|
||||
#define RGA_MMU_STA_CTRL_OFFSET (RGA_MMU_STA_CTRL-0x100)
|
||||
#define RGA_MMU_STA_OFFSET (RGA_MMU_STA-0x100)
|
||||
|
||||
#define RGA_MODE_CTRL_OFFSET (RGA_MODE_CTRL-0x100)
|
||||
#define RGA_SRC_Y_MST_OFFSET (RGA_SRC_Y_MST-0x100)
|
||||
#define RGA_SRC_CB_MST_OFFSET (RGA_SRC_CB_MST-0x100)
|
||||
#define RGA_SRC_CR_MST_OFFSET (RGA_SRC_CR_MST-0x100)
|
||||
#define RGA_SRC_VIR_INFO_OFFSET (RGA_SRC_VIR_INFO-0x100)
|
||||
#define RGA_SRC_ACT_INFO_OFFSET (RGA_SRC_ACT_INFO-0x100)
|
||||
#define RGA_SRC_X_PARA_OFFSET (RGA_SRC_X_PARA-0x100)
|
||||
#define RGA_SRC_Y_PARA_OFFSET (RGA_SRC_Y_PARA-0x100)
|
||||
#define RGA_SRC_TILE_XINFO_OFFSET (RGA_SRC_TILE_XINFO-0x100)
|
||||
#define RGA_SRC_TILE_YINFO_OFFSET (RGA_SRC_TILE_YINFO-0x100)
|
||||
#define RGA_SRC_TILE_H_INCR_OFFSET (RGA_SRC_TILE_H_INCR-0x100)
|
||||
#define RGA_SRC_TILE_V_INCR_OFFSET (RGA_SRC_TILE_V_INCR-0x100)
|
||||
#define RGA_SRC_TILE_OFFSETX_OFFSET (RGA_SRC_TILE_OFFSETX-0x100)
|
||||
#define RGA_SRC_TILE_OFFSETY_OFFSET (RGA_SRC_TILE_OFFSETY-0x100)
|
||||
#define RGA_SRC_BG_COLOR_OFFSET (RGA_SRC_BG_COLOR-0x100)
|
||||
|
||||
#define RGA_SRC_FG_COLOR_OFFSET (RGA_SRC_FG_COLOR-0x100)
|
||||
#define RGA_LINE_DRAWING_COLOR_OFFSET (RGA_LINE_DRAWING_COLOR-0x100)
|
||||
|
||||
#define RGA_SRC_TR_COLOR0_OFFSET (RGA_SRC_TR_COLOR0-0x100)
|
||||
#define RGA_CP_GR_A_OFFSET (RGA_CP_GR_A-0x100) //repeat
|
||||
|
||||
#define RGA_SRC_TR_COLOR1_OFFSET (RGA_SRC_TR_COLOR1-0x100)
|
||||
#define RGA_CP_GR_B_OFFSET (RGA_CP_GR_B-0x100) //repeat
|
||||
|
||||
#define RGA_LINE_DRAW_OFFSET (RGA_LINE_DRAW-0x100)
|
||||
#define RGA_PAT_START_POINT_OFFSET (RGA_PAT_START_POINT-0x100) //repeat
|
||||
|
||||
#define RGA_DST_MST_OFFSET (RGA_DST_MST-0x100)
|
||||
#define RGA_LUT_MST_OFFSET (RGA_LUT_MST-0x100) //repeat
|
||||
#define RGA_PAT_MST_OFFSET (RGA_PAT_MST-0x100) //repeat
|
||||
#define RGA_LINE_DRAWING_MST_OFFSET (RGA_LINE_DRAWING_MST-0x100) //repeat
|
||||
|
||||
#define RGA_DST_VIR_INFO_OFFSET (RGA_DST_VIR_INFO-0x100)
|
||||
|
||||
#define RGA_DST_CTR_INFO_OFFSET (RGA_DST_CTR_INFO-0x100)
|
||||
#define RGA_LINE_DRAW_XY_INFO_OFFSET (RGA_LINE_DRAW_XY_INFO-0x100) //repeat
|
||||
|
||||
#define RGA_ALPHA_CON_OFFSET (RGA_ALPHA_CON-0x100)
|
||||
|
||||
#define RGA_PAT_CON_OFFSET (RGA_PAT_CON-0x100)
|
||||
#define RGA_LINE_DRAWING_WIDTH_OFFSET (RGA_DST_VIR_WIDTH_PIX-0x100) //repeat
|
||||
|
||||
#define RGA_ROP_CON0_OFFSET (RGA_ROP_CON0-0x100)
|
||||
#define RGA_CP_GR_G_OFFSET (RGA_CP_GR_G-0x100) //repeat
|
||||
#define RGA_PRESCL_CB_MST_OFFSET (RGA_PRESCL_CB_MST-0x100) //repeat
|
||||
|
||||
#define RGA_ROP_CON1_OFFSET (RGA_ROP_CON1-0x100)
|
||||
#define RGA_CP_GR_R_OFFSET (RGA_CP_GR_R-0x100) //repeat
|
||||
#define RGA_PRESCL_CR_MST_OFFSET (RGA_PRESCL_CR_MST-0x100) //repeat
|
||||
|
||||
#define RGA_FADING_CON_OFFSET (RGA_FADING_CON-0x100)
|
||||
#define RGA_MMU_TLB_OFFSET (RGA_MMU_TBL-0x100)
|
||||
|
||||
#define RGA_YUV_OUT_CFG_OFFSET (RGA_YUV_OUT_CFG-0x100)
|
||||
#define RGA_DST_UV_MST_OFFSET (RGA_DST_UV_MST-0x100)
|
||||
|
||||
|
||||
|
||||
void matrix_cal(const struct rga_req *msg, TILE_INFO *tile);
|
||||
|
||||
|
||||
int RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base);
|
||||
uint8_t RGA_pixel_width_init(uint32_t format);
|
||||
|
||||
#ifndef __REG_INFO_H__
|
||||
#define __REG_INFO_H__
|
||||
|
||||
|
||||
//#include "chip_register.h"
|
||||
|
||||
//#include "rga_struct.h"
|
||||
#include "rga.h"
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(X, Y) ((X)<(Y)?(X):(Y))
|
||||
#endif
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(X, Y) ((X)>(Y)?(X):(Y))
|
||||
#endif
|
||||
|
||||
#ifndef ABS
|
||||
#define ABS(X) (((X) < 0) ? (-(X)) : (X))
|
||||
#endif
|
||||
|
||||
#ifndef CLIP
|
||||
#define CLIP(x, a, b) ((x) < (a)) ? (a) : (((x) > (b)) ? (b) : (x))
|
||||
#endif
|
||||
|
||||
//RGA register map
|
||||
|
||||
//General Registers
|
||||
#define rRGA_SYS_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_SYS_CTRL))
|
||||
#define rRGA_CMD_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_CMD_CTRL))
|
||||
#define rRGA_CMD_ADDR (*(volatile uint32_t *)(RGA_BASE + RGA_CMD_ADDR))
|
||||
#define rRGA_STATUS (*(volatile uint32_t *)(RGA_BASE + RGA_STATUS))
|
||||
#define rRGA_INT (*(volatile uint32_t *)(RGA_BASE + RGA_INT))
|
||||
#define rRGA_AXI_ID (*(volatile uint32_t *)(RGA_BASE + RGA_AXI_ID))
|
||||
#define rRGA_MMU_STA_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_STA_CTRL))
|
||||
#define rRGA_MMU_STA (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_STA))
|
||||
|
||||
//Command code start
|
||||
#define rRGA_MODE_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_MODE_CTRL))
|
||||
|
||||
//Source Image Registers
|
||||
#define rRGA_SRC_Y_MST (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_Y_MST))
|
||||
#define rRGA_SRC_CB_MST (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_CB_MST))
|
||||
#define rRGA_MASK_READ_MST (*(volatile uint32_t *)(RGA_BASE + RGA_MASK_READ_MST)) //repeat
|
||||
#define rRGA_SRC_CR_MST (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_CR_MST))
|
||||
#define rRGA_SRC_VIR_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_VIR_INFO))
|
||||
#define rRGA_SRC_ACT_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_ACT_INFO))
|
||||
#define rRGA_SRC_X_PARA (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_X_PARA))
|
||||
#define rRGA_SRC_Y_PARA (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_Y_PARA))
|
||||
#define rRGA_SRC_TILE_XINFO (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_XINFO))
|
||||
#define rRGA_SRC_TILE_YINFO (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_YINFO))
|
||||
#define rRGA_SRC_TILE_H_INCR (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_H_INCR))
|
||||
#define rRGA_SRC_TILE_V_INCR (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_V_INCR))
|
||||
#define rRGA_SRC_TILE_OFFSETX (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_OFFSETX))
|
||||
#define rRGA_SRC_TILE_OFFSETY (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_OFFSETY))
|
||||
#define rRGA_SRC_BG_COLOR (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_BG_COLOR))
|
||||
#define rRGA_SRC_FG_COLOR (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_FG_COLOR))
|
||||
#define rRGA_LINE_DRAWING_COLOR (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAWING_COLOR)) //repeat
|
||||
#define rRGA_SRC_TR_COLOR0 (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TR_COLOR0))
|
||||
#define rRGA_CP_GR_A (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_A)) //repeat
|
||||
#define rRGA_SRC_TR_COLOR1 (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TR_COLOR1))
|
||||
#define rRGA_CP_GR_B (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_B)) //repeat
|
||||
|
||||
#define rRGA_LINE_DRAW (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAW))
|
||||
#define rRGA_PAT_START_POINT (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_START_POINT)) //repeat
|
||||
|
||||
//Destination Image Registers
|
||||
#define rRGA_DST_MST (*(volatile uint32_t *)(RGA_BASE + RGA_DST_MST))
|
||||
#define rRGA_LUT_MST (*(volatile uint32_t *)(RGA_BASE + RGA_LUT_MST)) //repeat
|
||||
#define rRGA_PAT_MST (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_MST)) //repeat
|
||||
#define rRGA_LINE_DRAWING_MST (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAWING_MST)) //repeat
|
||||
|
||||
#define rRGA_DST_VIR_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_DST_VIR_INFO))
|
||||
|
||||
#define rRGA_DST_CTR_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_DST_CTR_INFO))
|
||||
#define rRGA_LINE_DRAW_XY_INFO (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAW_XY_INFO)) //repeat
|
||||
|
||||
//Alpha/ROP Registers
|
||||
#define rRGA_ALPHA_CON (*(volatile uint32_t *)(RGA_BASE + RGA_ALPHA_CON))
|
||||
#define rRGA_FADING_CON (*(volatile uint32_t *)(RGA_BASE + RGA_FADING_CON))
|
||||
|
||||
#define rRGA_PAT_CON (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_CON))
|
||||
#define rRGA_DST_VIR_WIDTH_PIX (*(volatile uint32_t *)(RGA_BASE + RGA_DST_VIR_WIDTH_PIX)) //repeat
|
||||
|
||||
#define rRGA_ROP_CON0 (*(volatile uint32_t *)(RGA_BASE + RGA_ROP_CON0))
|
||||
#define rRGA_CP_GR_G (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_G)) //repeat
|
||||
#define rRGA_PRESCL_CB_MST (*(volatile uint32_t *)(RGA_BASE + RGA_PRESCL_CB_MST)) //repeat
|
||||
|
||||
#define rRGA_ROP_CON1 (*(volatile uint32_t *)(RGA_BASE + RGA_ROP_CON1))
|
||||
#define rRGA_CP_GR_R (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_R)) //repeat
|
||||
#define rRGA_PRESCL_CR_MST (*(volatile uint32_t *)(RGA_BASE + RGA_PRESCL_CR_MST)) //repeat
|
||||
|
||||
//MMU Register
|
||||
#define rRGA_MMU_CTRL (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_CTRL))
|
||||
|
||||
|
||||
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
//reg detail definition
|
||||
//-----------------------------------------------------------------
|
||||
/*RGA_SYS_CTRL*/
|
||||
#define m_RGA_SYS_CTRL_CMD_MODE ( 1<<2 )
|
||||
#define m_RGA_SYS_CTRL_OP_ST_SLV ( 1<<1 )
|
||||
#define m_RGA_sys_CTRL_SOFT_RESET ( 1<<0 )
|
||||
|
||||
#define s_RGA_SYS_CTRL_CMD_MODE(x) ( (x&0x1)<<2 )
|
||||
#define s_RGA_SYS_CTRL_OP_ST_SLV(x) ( (x&0x1)<<1 )
|
||||
#define s_RGA_sys_CTRL_SOFT_RESET(x) ( (x&0x1)<<0 )
|
||||
|
||||
|
||||
/*RGA_CMD_CTRL*/
|
||||
#define m_RGA_CMD_CTRL_CMD_INCR_NUM ( 0x3ff<<3 )
|
||||
#define m_RGA_CMD_CTRL_CMD_STOP_MODE ( 1<<2 )
|
||||
#define m_RGA_CMD_CTRL_CMD_INCR_VALID ( 1<<1 )
|
||||
#define m_RGA_CMD_CTRL_CMD_LINE_FET_ST ( 1<<0 )
|
||||
|
||||
#define s_RGA_CMD_CTRL_CMD_INCR_NUM(x) ( (x&0x3ff)<<3 )
|
||||
#define s_RGA_CMD_CTRL_CMD_STOP_MODE(x) ( (x&0x1)<<2 )
|
||||
#define s_RGA_CMD_CTRL_CMD_INCR_VALID(x) ( (x&0x1)<<1 )
|
||||
#define s_RGA_CMD_CTRL_CMD_LINE_FET_ST(x) ( (x*0x1)<<0 )
|
||||
|
||||
|
||||
/*RGA_STATUS*/
|
||||
#define m_RGA_CMD_STATUS_CMD_TOTAL_NUM ( 0xfff<<20 )
|
||||
#define m_RGA_CMD_STATUS_NOW_CMD_NUM ( 0xfff<<8 )
|
||||
#define m_RGA_CMD_STATUS_ENGINE_STATUS ( 1<<0 )
|
||||
|
||||
|
||||
/*RGA_INT*/
|
||||
#define m_RGA_INT_ALL_CMD_DONE_INT_EN ( 1<<10 )
|
||||
#define m_RGA_INT_MMU_INT_EN ( 1<<9 )
|
||||
#define m_RGA_INT_ERROR_INT_EN ( 1<<8 )
|
||||
#define m_RGA_INT_NOW_CMD_DONE_INT_CLEAR ( 1<<7 )
|
||||
#define m_RGA_INT_ALL_CMD_DONE_INT_CLEAR ( 1<<6 )
|
||||
#define m_RGA_INT_MMU_INT_CLEAR ( 1<<5 )
|
||||
#define m_RGA_INT_ERROR_INT_CLEAR ( 1<<4 )
|
||||
#define m_RGA_INT_NOW_CMD_DONE_INT_FLAG ( 1<<3 )
|
||||
#define m_RGA_INT_ALL_CMD_DONE_INT_FLAG ( 1<<2 )
|
||||
#define m_RGA_INT_MMU_INT_FLAG ( 1<<1 )
|
||||
#define m_RGA_INT_ERROR_INT_FLAG ( 1<<0 )
|
||||
|
||||
#define s_RGA_INT_ALL_CMD_DONE_INT_EN(x) ( (x&0x1)<<10 )
|
||||
#define s_RGA_INT_MMU_INT_EN(x) ( (x&0x1)<<9 )
|
||||
#define s_RGA_INT_ERROR_INT_EN(x) ( (x&0x1)<<8 )
|
||||
#define s_RGA_INT_NOW_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<7 )
|
||||
#define s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<6 )
|
||||
#define s_RGA_INT_MMU_INT_CLEAR(x) ( (x&0x1)<<5 )
|
||||
#define s_RGA_INT_ERROR_INT_CLEAR(x) ( (x&0x1)<<4 )
|
||||
|
||||
|
||||
/*RGA_AXI_ID*/
|
||||
#define m_RGA_AXI_ID_MMU_READ ( 3<<30 )
|
||||
#define m_RGA_AXI_ID_MMU_WRITE ( 3<<28 )
|
||||
#define m_RGA_AXI_ID_MASK_READ ( 0xf<<24 )
|
||||
#define m_RGA_AXI_ID_CMD_FET ( 0xf<<20 )
|
||||
#define m_RGA_AXI_ID_DST_WRITE ( 0xf<<16 )
|
||||
#define m_RGA_AXI_ID_DST_READ ( 0xf<<12 )
|
||||
#define m_RGA_AXI_ID_SRC_CR_READ ( 0xf<<8 )
|
||||
#define m_RGA_AXI_ID_SRC_CB_READ ( 0xf<<4 )
|
||||
#define m_RGA_AXI_ID_SRC_Y_READ ( 0xf<<0 )
|
||||
|
||||
#define s_RGA_AXI_ID_MMU_READ(x) ( (x&0x3)<<30 )
|
||||
#define s_RGA_AXI_ID_MMU_WRITE(x) ( (x&0x3)<<28 )
|
||||
#define s_RGA_AXI_ID_MASK_READ(x) ( (x&0xf)<<24 )
|
||||
#define s_RGA_AXI_ID_CMD_FET(x) ( (x&0xf)<<20 )
|
||||
#define s_RGA_AXI_ID_DST_WRITE(x) ( (x&0xf)<<16 )
|
||||
#define s_RGA_AXI_ID_DST_READ(x) ( (x&0xf)<<12 )
|
||||
#define s_RGA_AXI_ID_SRC_CR_READ(x) ( (x&0xf)<<8 )
|
||||
#define s_RGA_AXI_ID_SRC_CB_READ(x) ( (x&0xf)<<4 )
|
||||
#define s_RGA_AXI_ID_SRC_Y_READ(x) ( (x&0xf)<<0 )
|
||||
|
||||
|
||||
/*RGA_MMU_STA_CTRL*/
|
||||
#define m_RGA_MMU_STA_CTRL_TLB_STA_CLEAR ( 1<<3 )
|
||||
#define m_RGA_MMU_STA_CTRL_TLB_STA_RESUME ( 1<<2 )
|
||||
#define m_RGA_MMU_STA_CTRL_TLB_STA_PAUSE ( 1<<1 )
|
||||
#define m_RGA_MMU_STA_CTRL_TLB_STA_EN ( 1<<0 )
|
||||
|
||||
#define s_RGA_MMU_STA_CTRL_TLB_STA_CLEAR(x) ( (x&0x1)<<3 )
|
||||
#define s_RGA_MMU_STA_CTRL_TLB_STA_RESUME(x) ( (x&0x1)<<2 )
|
||||
#define s_RGA_MMU_STA_CTRL_TLB_STA_PAUSE(x) ( (x&0x1)<<1 )
|
||||
#define s_RGA_MMU_STA_CTRL_TLB_STA_EN(x) ( (x&0x1)<<0 )
|
||||
|
||||
|
||||
|
||||
/* RGA_MODE_CTRL */
|
||||
#define m_RGA_MODE_CTRL_2D_RENDER_MODE ( 7<<0 )
|
||||
#define m_RGA_MODE_CTRL_SRC_RGB_PACK ( 1<<3 )
|
||||
#define m_RGA_MODE_CTRL_SRC_FORMAT ( 15<<4 )
|
||||
#define m_RGA_MODE_CTRL_SRC_RB_SWAP ( 1<<8 )
|
||||
#define m_RGA_MODE_CTRL_SRC_ALPHA_SWAP ( 1<<9 )
|
||||
#define m_RGA_MODE_CTRL_SRC_UV_SWAP_MODE ( 1<<10 )
|
||||
#define m_RGA_MODE_CTRL_YUV2RGB_CON_MODE ( 3<<11 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TRANS_MODE (0x1f<<13 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_MODE ( 1<<13 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_R_EN ( 1<<14 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_G_EN ( 1<<15 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_B_EN ( 1<<16 )
|
||||
#define m_RGA_MODE_CTRL_SRC_TR_A_EN ( 1<<17 )
|
||||
#define m_RGA_MODE_CTRL_ROTATE_MODE ( 3<<18 )
|
||||
#define m_RGA_MODE_CTRL_SCALE_MODE ( 3<<20 )
|
||||
#define m_RGA_MODE_CTRL_PAT_SEL ( 1<<22 )
|
||||
#define m_RGA_MODE_CTRL_DST_FORMAT ( 3<<23 )
|
||||
#define m_RGA_MODE_CTRL_DST_RGB_PACK ( 1<<25 )
|
||||
#define m_RGA_MODE_CTRL_DST_RB_SWAP ( 1<<26 )
|
||||
#define m_RGA_MODE_CTRL_DST_ALPHA_SWAP ( 1<<27 )
|
||||
#define m_RGA_MODE_CTRL_LUT_ENDIAN_MODE ( 1<<28 )
|
||||
#define m_RGA_MODE_CTRL_CMD_INT_ENABLE ( 1<<29 )
|
||||
#define m_RGA_MODE_CTRL_ZERO_MODE_ENABLE ( 1<<30 )
|
||||
#define m_RGA_MODE_CTRL_DST_ALPHA_ENABLE ( 1<<30 )
|
||||
|
||||
|
||||
|
||||
#define s_RGA_MODE_CTRL_2D_RENDER_MODE(x) ( (x&0x7)<<0 )
|
||||
#define s_RGA_MODE_CTRL_SRC_RGB_PACK(x) ( (x&0x1)<<3 )
|
||||
#define s_RGA_MODE_CTRL_SRC_FORMAT(x) ( (x&0xf)<<4 )
|
||||
#define s_RGA_MODE_CTRL_SRC_RB_SWAP(x) ( (x&0x1)<<8 )
|
||||
#define s_RGA_MODE_CTRL_SRC_ALPHA_SWAP(x) ( (x&0x1)<<9 )
|
||||
#define s_RGA_MODE_CTRL_SRC_UV_SWAP_MODE(x) ( (x&0x1)<<10 )
|
||||
#define s_RGA_MODE_CTRL_YUV2RGB_CON_MODE(x) ( (x&0x3)<<11 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TRANS_MODE(x) ( (x&0x1f)<<13 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_MODE(x) ( (x&0x1)<<13 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_R_EN(x) ( (x&0x1)<<14 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_G_EN(x) ( (x&0x1)<<15 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_B_EN(x) ( (x&0x1)<<16 )
|
||||
#define s_RGA_MODE_CTRL_SRC_TR_A_EN(x) ( (x&0x1)<<17 )
|
||||
#define s_RGA_MODE_CTRL_ROTATE_MODE(x) ( (x&0x3)<<18 )
|
||||
#define s_RGA_MODE_CTRL_SCALE_MODE(x) ( (x&0x3)<<20 )
|
||||
#define s_RGA_MODE_CTRL_PAT_SEL(x) ( (x&0x1)<<22 )
|
||||
#define s_RGA_MODE_CTRL_DST_FORMAT(x) ( (x&0x3)<<23 )
|
||||
#define s_RGA_MODE_CTRL_DST_RGB_PACK(x) ( (x&0x1)<<25 )
|
||||
#define s_RGA_MODE_CTRL_DST_RB_SWAP(x) ( (x&0x1)<<26 )
|
||||
#define s_RGA_MODE_CTRL_DST_ALPHA_SWAP(x) ( (x&0x1)<<27 )
|
||||
#define s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(x) ( (x&0x1)<<28 )
|
||||
#define s_RGA_MODE_CTRL_CMD_INT_ENABLE(x) ( (x&0x1)<<29 )
|
||||
#define s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(x) ( (x&0x1)<<30 )
|
||||
#define s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(x) ( (x&0x1)<<31 )
|
||||
|
||||
|
||||
|
||||
/* RGA_LINE_DRAW */
|
||||
#define m_RGA_LINE_DRAW_MAJOR_WIDTH ( 0x7ff<<0 )
|
||||
#define m_RGA_LINE_DRAW_LINE_DIRECTION ( 0x1<<11)
|
||||
#define m_RGA_LINE_DRAW_LINE_WIDTH ( 0xf<<12)
|
||||
#define m_RGA_LINE_DRAW_INCR_VALUE ( 0xfff<<16)
|
||||
#define m_RGA_LINE_DRAW_DIR_MAJOR ( 0x1<<28)
|
||||
#define m_RGA_LINE_DRAW_DIR_SEMI_MAJOR ( 0x1<<29)
|
||||
#define m_RGA_LINE_DRAW_LAST_POINT ( 0x1<<30)
|
||||
#define m_RGA_LINE_DRAW_ANTI_ALISING ( 0x1<<31)
|
||||
|
||||
#define s_RGA_LINE_DRAW_MAJOR_WIDTH(x) (((x)&0x7ff)<<0 )
|
||||
#define s_RGA_LINE_DRAW_LINE_DIRECTION(x) ( ((x)&0x1)<<11)
|
||||
#define s_RGA_LINE_DRAW_LINE_WIDTH(x) ( ((x)&0xf)<<12)
|
||||
#define s_RGA_LINE_DRAW_INCR_VALUE(x) (((x)&0xfff)<<16)
|
||||
#define s_RGA_LINE_DRAW_DIR_MAJOR(x) ( ((x)&0x1)<<28)
|
||||
#define s_RGA_LINE_DRAW_DIR_SEMI_MAJOR(x) ( ((x)&0x1)<<29)
|
||||
#define s_RGA_LINE_DRAW_LAST_POINT(x) ( ((x)&0x1)<<30)
|
||||
#define s_RGA_LINE_DRAW_ANTI_ALISING(x) ( ((x)&0x1)<<31)
|
||||
|
||||
|
||||
/* RGA_ALPHA_CON */
|
||||
#define m_RGA_ALPHA_CON_ENABLE ( 0x1<<0 )
|
||||
#define m_RGA_ALPHA_CON_A_OR_R_SEL ( 0x1<<1 )
|
||||
#define m_RGA_ALPHA_CON_ALPHA_MODE ( 0x3<<2 )
|
||||
#define m_RGA_ALPHA_CON_PD_MODE ( 0xf<<4 )
|
||||
#define m_RGA_ALPHA_CON_SET_CONSTANT_VALUE (0xff<<8 )
|
||||
#define m_RGA_ALPHA_CON_PD_M_SEL ( 0x1<<16)
|
||||
#define m_RGA_ALPHA_CON_FADING_ENABLE ( 0x1<<17)
|
||||
#define m_RGA_ALPHA_CON_ROP_MODE_SEL ( 0x3<<18)
|
||||
#define m_RGA_ALPHA_CON_CAL_MODE_SEL ( 0x1<<28)
|
||||
#define m_RGA_ALPHA_CON_DITHER_ENABLE ( 0x1<<29)
|
||||
#define m_RGA_ALPHA_CON_GRADIENT_CAL_MODE ( 0x1<<30)
|
||||
#define m_RGA_ALPHA_CON_AA_SEL ( 0x1<<31)
|
||||
|
||||
#define s_RGA_ALPHA_CON_ENABLE(x) ( (x&0x1)<<0 )
|
||||
#define s_RGA_ALPHA_CON_A_OR_R_SEL(x) ( (x&0x1)<<1 )
|
||||
#define s_RGA_ALPHA_CON_ALPHA_MODE(x) ( (x&0x3)<<2 )
|
||||
#define s_RGA_ALPHA_CON_PD_MODE(x) ( (x&0xf)<<4 )
|
||||
#define s_RGA_ALPHA_CON_SET_CONSTANT_VALUE(x) ((x&0xff)<<8 )
|
||||
#define s_RGA_ALPHA_CON_PD_M_SEL(x) ( (x&0x1)<<16)
|
||||
#define s_RGA_ALPHA_CON_FADING_ENABLE(x) ( (x&0x1)<<17)
|
||||
#define s_RGA_ALPHA_CON_ROP_MODE_SEL(x) ( (x&0x3)<<18)
|
||||
#define s_RGA_ALPHA_CON_CAL_MODE_SEL(x) ( (x&0x1)<<28)
|
||||
#define s_RGA_ALPHA_CON_DITHER_ENABLE(x) ( (x&0x1)<<29)
|
||||
#define s_RGA_ALPHA_CON_GRADIENT_CAL_MODE(x) ( (x&0x1)<<30)
|
||||
#define s_RGA_ALPHA_CON_AA_SEL(x) ( (x&0x1)<<31)
|
||||
|
||||
|
||||
/* blur sharp mode */
|
||||
#define m_RGA_BLUR_SHARP_FILTER_MODE ( 0x1<<25 )
|
||||
#define m_RGA_BLUR_SHARP_FILTER_TYPE ( 0x3<<26 )
|
||||
|
||||
#define s_RGA_BLUR_SHARP_FILTER_MODE(x) ( (x&0x1)<<25 )
|
||||
#define s_RGA_BLUR_SHARP_FILTER_TYPE(x) ( (x&0x3)<<26 )
|
||||
|
||||
|
||||
/* pre scale mode */
|
||||
#define m_RGA_PRE_SCALE_HOR_RATIO ( 0x3 <<20 )
|
||||
#define m_RGA_PRE_SCALE_VER_RATIO ( 0x3 <<22 )
|
||||
#define m_RGA_PRE_SCALE_OUTPUT_FORMAT ( 0x1 <<24 )
|
||||
|
||||
#define s_RGA_PRE_SCALE_HOR_RATIO(x) ( (x&0x3) <<20 )
|
||||
#define s_RGA_PRE_SCALE_VER_RATIO(x) ( (x&0x3) <<22 )
|
||||
#define s_RGA_PRE_SCALE_OUTPUT_FORMAT(x) ( (x&0x1) <<24 )
|
||||
|
||||
|
||||
|
||||
/* RGA_MMU_CTRL*/
|
||||
#define m_RGA_MMU_CTRL_TLB_ADDR ( 0xffffffff<<0)
|
||||
#define m_RGA_MMU_CTRL_PAGE_TABLE_SIZE ( 0x3<<4 )
|
||||
#define m_RGA_MMU_CTRL_MMU_ENABLE ( 0x1<<0 )
|
||||
#define m_RGA_MMU_CTRL_SRC_FLUSH ( 0x1<<1 )
|
||||
#define m_RGA_MMU_CTRL_DST_FLUSH ( 0x1<<2 )
|
||||
#define m_RGA_MMU_CTRL_CMD_CHAN_FLUSH ( 0x1<<3 )
|
||||
|
||||
#define s_RGA_MMU_CTRL_TLB_ADDR(x) ((x&0xffffffff))
|
||||
#define s_RGA_MMU_CTRL_PAGE_TABLE_SIZE(x) ((x&0x3)<<4)
|
||||
#define s_RGA_MMU_CTRL_MMU_ENABLE(x) ((x&0x1)<<0)
|
||||
#define s_RGA_MMU_CTRL_SRC_FLUSH(x) ((x&0x1)<<1)
|
||||
#define s_RGA_MMU_CTRL_DST_FLUSH(x) ((x&0x1)<<2)
|
||||
#define s_RGA_MMU_CTRL_CMD_CHAN_FLUSH(x) ((x&0x1)<<3)
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
#define RGA_MODE_CTRL_OFFSET 0x0
|
||||
#define RGA_SRC_Y_MST_OFFSET 0x4
|
||||
#define RGA_SRC_CB_MST_OFFSET 0x8
|
||||
#define RGA_SRC_CR_MST_OFFSET 0xc
|
||||
#define RGA_SRC_VIR_INFO_OFFSET 0x10
|
||||
#define RGA_SRC_ACT_INFO_OFFSET 0x14
|
||||
#define RGA_SRC_X_PARA_OFFSET 0x18
|
||||
#define RGA_SRC_Y_PARA_OFFSET 0x1c
|
||||
#define RGA_SRC_TILE_XINFO_OFFSET 0x20
|
||||
#define RGA_SRC_TILE_YINFO_OFFSET 0x24
|
||||
#define RGA_SRC_TILE_H_INCR_OFFSET 0x28
|
||||
#define RGA_SRC_TILE_V_INCR_OFFSET 0x2c
|
||||
#define RGA_SRC_TILE_OFFSETX_OFFSET 0x30
|
||||
#define RGA_SRC_TILE_OFFSETY_OFFSET 0x34
|
||||
#define RGA_SRC_BG_COLOR_OFFSET 0x38
|
||||
|
||||
#define RGA_SRC_FG_COLOR_OFFSET 0x3c
|
||||
#define RGA_LINE_DRAWING_COLOR_OFFSET 0x3c
|
||||
|
||||
#define RGA_SRC_TR_COLOR0_OFFSET 0x40
|
||||
#define RGA_CP_GR_A_OFFSET 0x40 //repeat
|
||||
|
||||
#define RGA_SRC_TR_COLOR1_OFFSET 0x44
|
||||
#define RGA_CP_GR_B_OFFSET 0x44 //repeat
|
||||
|
||||
#define RGA_LINE_DRAW_OFFSET 0x48
|
||||
#define RGA_PAT_START_POINT_OFFSET 0x48 //repeat
|
||||
|
||||
#define RGA_DST_MST_OFFSET 0x4c
|
||||
#define RGA_LUT_MST_OFFSET 0x4c //repeat
|
||||
#define RGA_PAT_MST_OFFSET 0x4c //repeat
|
||||
#define RGA_LINE_DRAWING_MST_OFFSET 0x4c //repeat
|
||||
|
||||
#define RGA_DST_VIR_INFO_OFFSET 0x50
|
||||
|
||||
#define RGA_DST_CTR_INFO_OFFSET 0x54
|
||||
#define RGA_LINE_DRAW_XY_INFO_OFFSET 0x54 //repeat
|
||||
|
||||
#define RGA_ALPHA_CON_OFFSET 0x58
|
||||
#define RGA_FADING_CON_OFFSET 0x5c
|
||||
|
||||
#define RGA_PAT_CON_OFFSET 0x60
|
||||
#define RGA_LINE_DRAWING_WIDTH_OFFSET 0x60 //repeat
|
||||
|
||||
#define RGA_ROP_CON0_OFFSET 0x64
|
||||
#define RGA_CP_GR_G_OFFSET 0x64 //repeat
|
||||
#define RGA_PRESCL_CB_MST_OFFSET 0x64 //repeat
|
||||
|
||||
#define RGA_ROP_CON1_OFFSET 0x68
|
||||
#define RGA_CP_GR_R_OFFSET 0x68 //repeat
|
||||
#define RGA_PRESCL_CR_MST_OFFSET 0x68 //repeat
|
||||
|
||||
#define RGA_MMU_CTRL_OFFSET 0x6c
|
||||
|
||||
|
||||
#define RGA_SYS_CTRL_OFFSET 0x000
|
||||
#define RGA_CMD_CTRL_OFFSET 0x004
|
||||
#define RGA_CMD_ADDR_OFFSET 0x008
|
||||
#define RGA_STATUS_OFFSET 0x00c
|
||||
#define RGA_INT_OFFSET 0x010
|
||||
#define RGA_AXI_ID_OFFSET 0x014
|
||||
#define RGA_MMU_STA_CTRL_OFFSET 0x018
|
||||
#define RGA_MMU_STA_OFFSET 0x01c
|
||||
*/
|
||||
//hxx
|
||||
|
||||
#define RGA_SYS_CTRL_OFFSET (RGA_SYS_CTRL-0x100)
|
||||
#define RGA_CMD_CTRL_OFFSET (RGA_CMD_CTRL-0x100)
|
||||
#define RGA_CMD_ADDR_OFFSET (RGA_CMD_ADDR-0x100)
|
||||
#define RGA_STATUS_OFFSET (RGA_STATUS-0x100)
|
||||
#define RGA_INT_OFFSET (RGA_INT-0x100)
|
||||
#define RGA_AXI_ID_OFFSET (RGA_AXI_ID-0x100)
|
||||
#define RGA_MMU_STA_CTRL_OFFSET (RGA_MMU_STA_CTRL-0x100)
|
||||
#define RGA_MMU_STA_OFFSET (RGA_MMU_STA-0x100)
|
||||
|
||||
#define RGA_MODE_CTRL_OFFSET (RGA_MODE_CTRL-0x100)
|
||||
#define RGA_SRC_Y_MST_OFFSET (RGA_SRC_Y_MST-0x100)
|
||||
#define RGA_SRC_CB_MST_OFFSET (RGA_SRC_CB_MST-0x100)
|
||||
#define RGA_SRC_CR_MST_OFFSET (RGA_SRC_CR_MST-0x100)
|
||||
#define RGA_SRC_VIR_INFO_OFFSET (RGA_SRC_VIR_INFO-0x100)
|
||||
#define RGA_SRC_ACT_INFO_OFFSET (RGA_SRC_ACT_INFO-0x100)
|
||||
#define RGA_SRC_X_PARA_OFFSET (RGA_SRC_X_PARA-0x100)
|
||||
#define RGA_SRC_Y_PARA_OFFSET (RGA_SRC_Y_PARA-0x100)
|
||||
#define RGA_SRC_TILE_XINFO_OFFSET (RGA_SRC_TILE_XINFO-0x100)
|
||||
#define RGA_SRC_TILE_YINFO_OFFSET (RGA_SRC_TILE_YINFO-0x100)
|
||||
#define RGA_SRC_TILE_H_INCR_OFFSET (RGA_SRC_TILE_H_INCR-0x100)
|
||||
#define RGA_SRC_TILE_V_INCR_OFFSET (RGA_SRC_TILE_V_INCR-0x100)
|
||||
#define RGA_SRC_TILE_OFFSETX_OFFSET (RGA_SRC_TILE_OFFSETX-0x100)
|
||||
#define RGA_SRC_TILE_OFFSETY_OFFSET (RGA_SRC_TILE_OFFSETY-0x100)
|
||||
#define RGA_SRC_BG_COLOR_OFFSET (RGA_SRC_BG_COLOR-0x100)
|
||||
|
||||
#define RGA_SRC_FG_COLOR_OFFSET (RGA_SRC_FG_COLOR-0x100)
|
||||
#define RGA_LINE_DRAWING_COLOR_OFFSET (RGA_LINE_DRAWING_COLOR-0x100)
|
||||
|
||||
#define RGA_SRC_TR_COLOR0_OFFSET (RGA_SRC_TR_COLOR0-0x100)
|
||||
#define RGA_CP_GR_A_OFFSET (RGA_CP_GR_A-0x100) //repeat
|
||||
|
||||
#define RGA_SRC_TR_COLOR1_OFFSET (RGA_SRC_TR_COLOR1-0x100)
|
||||
#define RGA_CP_GR_B_OFFSET (RGA_CP_GR_B-0x100) //repeat
|
||||
|
||||
#define RGA_LINE_DRAW_OFFSET (RGA_LINE_DRAW-0x100)
|
||||
#define RGA_PAT_START_POINT_OFFSET (RGA_PAT_START_POINT-0x100) //repeat
|
||||
|
||||
#define RGA_DST_MST_OFFSET (RGA_DST_MST-0x100)
|
||||
#define RGA_LUT_MST_OFFSET (RGA_LUT_MST-0x100) //repeat
|
||||
#define RGA_PAT_MST_OFFSET (RGA_PAT_MST-0x100) //repeat
|
||||
#define RGA_LINE_DRAWING_MST_OFFSET (RGA_LINE_DRAWING_MST-0x100) //repeat
|
||||
|
||||
#define RGA_DST_VIR_INFO_OFFSET (RGA_DST_VIR_INFO-0x100)
|
||||
|
||||
#define RGA_DST_CTR_INFO_OFFSET (RGA_DST_CTR_INFO-0x100)
|
||||
#define RGA_LINE_DRAW_XY_INFO_OFFSET (RGA_LINE_DRAW_XY_INFO-0x100) //repeat
|
||||
|
||||
#define RGA_ALPHA_CON_OFFSET (RGA_ALPHA_CON-0x100)
|
||||
|
||||
#define RGA_PAT_CON_OFFSET (RGA_PAT_CON-0x100)
|
||||
#define RGA_LINE_DRAWING_WIDTH_OFFSET (RGA_DST_VIR_WIDTH_PIX-0x100) //repeat
|
||||
|
||||
#define RGA_ROP_CON0_OFFSET (RGA_ROP_CON0-0x100)
|
||||
#define RGA_CP_GR_G_OFFSET (RGA_CP_GR_G-0x100) //repeat
|
||||
#define RGA_PRESCL_CB_MST_OFFSET (RGA_PRESCL_CB_MST-0x100) //repeat
|
||||
|
||||
#define RGA_ROP_CON1_OFFSET (RGA_ROP_CON1-0x100)
|
||||
#define RGA_CP_GR_R_OFFSET (RGA_CP_GR_R-0x100) //repeat
|
||||
#define RGA_PRESCL_CR_MST_OFFSET (RGA_PRESCL_CR_MST-0x100) //repeat
|
||||
|
||||
#define RGA_FADING_CON_OFFSET (RGA_FADING_CON-0x100)
|
||||
#define RGA_MMU_TLB_OFFSET (RGA_MMU_TBL-0x100)
|
||||
|
||||
#define RGA_YUV_OUT_CFG_OFFSET (RGA_YUV_OUT_CFG-0x100)
|
||||
#define RGA_DST_UV_MST_OFFSET (RGA_DST_UV_MST-0x100)
|
||||
|
||||
|
||||
|
||||
void matrix_cal(const struct rga_req *msg, TILE_INFO *tile);
|
||||
|
||||
|
||||
int RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base);
|
||||
uint8_t RGA_pixel_width_init(uint32_t format);
|
||||
|
||||
|
||||
@@ -1,56 +1,56 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __RGA_ROP_H__
|
||||
#define __RGA_ROP_H__
|
||||
|
||||
unsigned int ROP3_code[256] =
|
||||
{
|
||||
0x00000007, 0x00000451, 0x00006051, 0x00800051, 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0
|
||||
0x00800765, 0x000004b0, 0x00000065, 0x000004f4, 0x00000075, 0x000004e6, 0x00804850, 0x00800005,
|
||||
|
||||
0x00006850, 0x00800050, 0x00805028, 0x00000568, 0x00804031, 0x00000471, 0x002b6071, 0x018037aa,//1
|
||||
0x008007aa, 0x00036071, 0x00002c6a, 0x00803631, 0x00002d68, 0x00802721, 0x008002d0, 0x000006d0,
|
||||
|
||||
0x0080066e, 0x00000528, 0x00000066, 0x0000056c, 0x018007aa, 0x0002e06a, 0x00003471, 0x00834031,//2
|
||||
0x00800631, 0x0002b471, 0x00006071, 0x008037aa, 0x000036d0, 0x008002d4, 0x00002d28, 0x000006d4,
|
||||
|
||||
0x0000006e, 0x00000565, 0x00003451, 0x00800006, 0x000034f0, 0x00834830, 0x00800348, 0x00000748,//3
|
||||
0x00002f48, 0x0080034c, 0x000034b0, 0x0000074c, 0x00000031, 0x00834850, 0x000034e6, 0x00800071,
|
||||
|
||||
0x008006f4, 0x00000431, 0x018007a1, 0x00b6e870, 0x00000074, 0x0000046e, 0x00002561, 0x00802f28,//4
|
||||
0x00800728, 0x0002a561, 0x000026c2, 0x008002c6, 0x00007068, 0x018035aa, 0x00002c2a, 0x000006c6,
|
||||
|
||||
0x0000006c, 0x00000475, 0x000024e2, 0x008036b0, 0x00804051, 0x00800004, 0x00800251, 0x00000651,
|
||||
0x00002e4a, 0x0080024e, 0x00000028, 0x00824842, 0x000024a2, 0x0000064e, 0x000024f4, 0x00800068,//5
|
||||
|
||||
0x008006b0, 0x000234f0, 0x00002741, 0x00800345, 0x00003651, 0x00800255, 0x00000030, 0x00834051,
|
||||
0x00a34842, 0x000002b0, 0x00800271, 0x0002b651, 0x00800368, 0x0002a741, 0x0000364e, 0x00806830,//6
|
||||
|
||||
0x00006870, 0x008037a2, 0x00003431, 0x00000745, 0x00002521, 0x00000655, 0x0000346e, 0x00800062,
|
||||
0x008002f0, 0x000236d0, 0x000026d4, 0x00807028, 0x000036c6, 0x00806031, 0x008005aa, 0x00000671,//7
|
||||
|
||||
0x00800671, 0x000005aa, 0x00006031, 0x008036c6, 0x00007028, 0x00802e55, 0x008236d0, 0x000002f0,
|
||||
0x00000070, 0x0080346e, 0x00800655, 0x00802521, 0x00800745, 0x00803431, 0x000037a2, 0x00806870,//8
|
||||
|
||||
0x00006830, 0x0080364e, 0x00822f48, 0x00000361, 0x0082b651, 0x00000271, 0x00800231, 0x002b4051,
|
||||
0x00034051, 0x00800030, 0x0080026e, 0x00803651, 0x0080036c, 0x00802741, 0x008234f0, 0x000006b0,//9
|
||||
|
||||
0x00000068, 0x00802c75, 0x0080064e, 0x008024a2, 0x0002c04a, 0x00800021, 0x00800275, 0x00802e51,
|
||||
0x00800651, 0x00000251, 0x00800000, 0x00004051, 0x000036b0, 0x008024e2, 0x00800475, 0x00000045,//a
|
||||
|
||||
0x008006c6, 0x00802c2a, 0x000035aa, 0x00807068, 0x008002f4, 0x008026c2, 0x00822d68, 0x00000728,
|
||||
0x00002f28, 0x00802561, 0x0080046e, 0x00000046, 0x00836870, 0x000007a2, 0x00800431, 0x00004071,//b
|
||||
|
||||
0x00000071, 0x008034e6, 0x00034850, 0x00800031, 0x0080074c, 0x008034b0, 0x00800365, 0x00802f48,
|
||||
0x00800748, 0x00000341, 0x000026a2, 0x008034f0, 0x00800002, 0x00005048, 0x00800565, 0x00000055,//c
|
||||
|
||||
0x008006d4, 0x00802d28, 0x008002e6, 0x008036d0, 0x000037aa, 0x00806071, 0x0082b471, 0x00000631,
|
||||
0x00002e2a, 0x00803471, 0x00826862, 0x010007aa, 0x0080056c, 0x00000054, 0x00800528, 0x00005068,//d
|
||||
|
||||
0x008006d0, 0x000002d0, 0x00002721, 0x00802d68, 0x00003631, 0x00802c6a, 0x00836071, 0x000007aa,
|
||||
0x010037aa, 0x00a36870, 0x00800471, 0x00004031, 0x00800568, 0x00005028, 0x00000050, 0x00800545,//e
|
||||
|
||||
0x00800001, 0x00004850, 0x008004e6, 0x0000004e, 0x008004f4, 0x0000004c, 0x008004b0, 0x00004870,
|
||||
0x008004f0, 0x00004830, 0x00000048, 0x0080044e, 0x00000051, 0x008004d4, 0x00800451, 0x00800007,//f
|
||||
};
|
||||
|
||||
#endif
|
||||
#ifndef __RGA_ROP_H__
|
||||
#define __RGA_ROP_H__
|
||||
|
||||
unsigned int ROP3_code[256] =
|
||||
{
|
||||
0x00000007, 0x00000451, 0x00006051, 0x00800051, 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0
|
||||
0x00800765, 0x000004b0, 0x00000065, 0x000004f4, 0x00000075, 0x000004e6, 0x00804850, 0x00800005,
|
||||
|
||||
0x00006850, 0x00800050, 0x00805028, 0x00000568, 0x00804031, 0x00000471, 0x002b6071, 0x018037aa,//1
|
||||
0x008007aa, 0x00036071, 0x00002c6a, 0x00803631, 0x00002d68, 0x00802721, 0x008002d0, 0x000006d0,
|
||||
|
||||
0x0080066e, 0x00000528, 0x00000066, 0x0000056c, 0x018007aa, 0x0002e06a, 0x00003471, 0x00834031,//2
|
||||
0x00800631, 0x0002b471, 0x00006071, 0x008037aa, 0x000036d0, 0x008002d4, 0x00002d28, 0x000006d4,
|
||||
|
||||
0x0000006e, 0x00000565, 0x00003451, 0x00800006, 0x000034f0, 0x00834830, 0x00800348, 0x00000748,//3
|
||||
0x00002f48, 0x0080034c, 0x000034b0, 0x0000074c, 0x00000031, 0x00834850, 0x000034e6, 0x00800071,
|
||||
|
||||
0x008006f4, 0x00000431, 0x018007a1, 0x00b6e870, 0x00000074, 0x0000046e, 0x00002561, 0x00802f28,//4
|
||||
0x00800728, 0x0002a561, 0x000026c2, 0x008002c6, 0x00007068, 0x018035aa, 0x00002c2a, 0x000006c6,
|
||||
|
||||
0x0000006c, 0x00000475, 0x000024e2, 0x008036b0, 0x00804051, 0x00800004, 0x00800251, 0x00000651,
|
||||
0x00002e4a, 0x0080024e, 0x00000028, 0x00824842, 0x000024a2, 0x0000064e, 0x000024f4, 0x00800068,//5
|
||||
|
||||
0x008006b0, 0x000234f0, 0x00002741, 0x00800345, 0x00003651, 0x00800255, 0x00000030, 0x00834051,
|
||||
0x00a34842, 0x000002b0, 0x00800271, 0x0002b651, 0x00800368, 0x0002a741, 0x0000364e, 0x00806830,//6
|
||||
|
||||
0x00006870, 0x008037a2, 0x00003431, 0x00000745, 0x00002521, 0x00000655, 0x0000346e, 0x00800062,
|
||||
0x008002f0, 0x000236d0, 0x000026d4, 0x00807028, 0x000036c6, 0x00806031, 0x008005aa, 0x00000671,//7
|
||||
|
||||
0x00800671, 0x000005aa, 0x00006031, 0x008036c6, 0x00007028, 0x00802e55, 0x008236d0, 0x000002f0,
|
||||
0x00000070, 0x0080346e, 0x00800655, 0x00802521, 0x00800745, 0x00803431, 0x000037a2, 0x00806870,//8
|
||||
|
||||
0x00006830, 0x0080364e, 0x00822f48, 0x00000361, 0x0082b651, 0x00000271, 0x00800231, 0x002b4051,
|
||||
0x00034051, 0x00800030, 0x0080026e, 0x00803651, 0x0080036c, 0x00802741, 0x008234f0, 0x000006b0,//9
|
||||
|
||||
0x00000068, 0x00802c75, 0x0080064e, 0x008024a2, 0x0002c04a, 0x00800021, 0x00800275, 0x00802e51,
|
||||
0x00800651, 0x00000251, 0x00800000, 0x00004051, 0x000036b0, 0x008024e2, 0x00800475, 0x00000045,//a
|
||||
|
||||
0x008006c6, 0x00802c2a, 0x000035aa, 0x00807068, 0x008002f4, 0x008026c2, 0x00822d68, 0x00000728,
|
||||
0x00002f28, 0x00802561, 0x0080046e, 0x00000046, 0x00836870, 0x000007a2, 0x00800431, 0x00004071,//b
|
||||
|
||||
0x00000071, 0x008034e6, 0x00034850, 0x00800031, 0x0080074c, 0x008034b0, 0x00800365, 0x00802f48,
|
||||
0x00800748, 0x00000341, 0x000026a2, 0x008034f0, 0x00800002, 0x00005048, 0x00800565, 0x00000055,//c
|
||||
|
||||
0x008006d4, 0x00802d28, 0x008002e6, 0x008036d0, 0x000037aa, 0x00806071, 0x0082b471, 0x00000631,
|
||||
0x00002e2a, 0x00803471, 0x00826862, 0x010007aa, 0x0080056c, 0x00000054, 0x00800528, 0x00005068,//d
|
||||
|
||||
0x008006d0, 0x000002d0, 0x00002721, 0x00802d68, 0x00003631, 0x00802c6a, 0x00836071, 0x000007aa,
|
||||
0x010037aa, 0x00a36870, 0x00800471, 0x00004031, 0x00800568, 0x00005028, 0x00000050, 0x00800545,//e
|
||||
|
||||
0x00800001, 0x00004850, 0x008004e6, 0x0000004e, 0x008004f4, 0x0000004c, 0x008004b0, 0x00004870,
|
||||
0x008004f0, 0x00004830, 0x00000048, 0x0080044e, 0x00000051, 0x008004d4, 0x00800451, 0x00800007,//f
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,49 +1,49 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __RGA_TYPE_H__
|
||||
#define __RGA_TYPE_H__
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __cplusplus */
|
||||
|
||||
typedef unsigned int UWORD32;
|
||||
typedef unsigned int uint32;
|
||||
typedef unsigned int RK_U32;
|
||||
|
||||
typedef unsigned short UWORD16;
|
||||
typedef unsigned short RK_U16;
|
||||
|
||||
typedef unsigned char UBYTE;
|
||||
typedef unsigned char RK_U8;
|
||||
|
||||
typedef int WORD32;
|
||||
typedef int RK_S32;
|
||||
|
||||
typedef short WORD16;
|
||||
typedef short RK_S16;
|
||||
|
||||
typedef char BYTE;
|
||||
typedef char RK_S8;
|
||||
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0L
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1L
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
#endif /* __RGA_TYPR_H__ */
|
||||
|
||||
#ifndef __RGA_TYPE_H__
|
||||
#define __RGA_TYPE_H__
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __cplusplus */
|
||||
|
||||
typedef unsigned int UWORD32;
|
||||
typedef unsigned int uint32;
|
||||
typedef unsigned int RK_U32;
|
||||
|
||||
typedef unsigned short UWORD16;
|
||||
typedef unsigned short RK_U16;
|
||||
|
||||
typedef unsigned char UBYTE;
|
||||
typedef unsigned char RK_U8;
|
||||
|
||||
typedef int WORD32;
|
||||
typedef int RK_S32;
|
||||
|
||||
typedef short WORD16;
|
||||
typedef short RK_S16;
|
||||
|
||||
typedef char BYTE;
|
||||
typedef char RK_S8;
|
||||
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0L
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1L
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
#if __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
#endif /* __RGA_TYPR_H__ */
|
||||
|
||||
|
||||
Reference in New Issue
Block a user