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enable DLL normal mode

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hcy
2012-10-09 11:38:26 +08:00
parent d02bbcd5f4
commit 2e1c5af1fa
1 changed files with 2 additions and 2 deletions
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4
arch/arm/mach-rk2928/ddr.c
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@@ -31,7 +31,7 @@ typedef uint32_t uint32 ;
#define SR_IDLE (0x1) //unit:32*DDR clk cycle, and 0 for disable auto self-refresh
#define PD_IDLE (0x40) //unit:DDR clk cycle, and 0 for disable auto power-down
#define PHY_ODT_DISABLE_FREQ (333) //<2F><><EFBFBD><EFBFBD>odt disable<6C><65>Ƶ<EFBFBD><C6B5>
#define PHY_DLL_DISABLE_FREQ (666) //<2F><><EFBFBD><EFBFBD>dll bypass<73><73>Ƶ<EFBFBD><C6B5>
#define PHY_DLL_DISABLE_FREQ (266) //<2F><><EFBFBD><EFBFBD>dll bypass<73><73>Ƶ<EFBFBD><C6B5>
//#define PMU_BASE_ADDR RK30_PMU_BASE //??RK 2928 PMU<4D><55><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define SDRAMC_BASE_ADDR RK2928_DDR_PCTL_BASE
@@ -2210,7 +2210,7 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
uint32_t cs,die=1;
uint32_t calStatusLeft, calStatusRight;
ddr_print("version 1.00 20120925 \n");
ddr_print("version 1.00 20121009 \n");
cs = (1 << (((pGRF_Reg->GRF_OS_REG[1]) >> DDR_RANK_COUNT)&0x1)); //case 0:1rank ; case 1:2rank ;
mem_type = ((pGRF_Reg->GRF_OS_REG[1] >> 13) &0x7);
ddr_speed_bin = dram_speed_bin;