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clock: G12A: add sys_pll/hifi_pll/gp0_pll table

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PD#156734: pll freq table which 3G < DCO < 6G

Change-Id: Ia1cadbd13af57d45a3a6d7b1bf65b8a055f4f91f
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
This commit is contained in:
Qiufang Dai
2018-01-08 21:10:53 +08:00
committed by Yixun Lan
parent 9391abb298
commit 2e4da54fed
1 changed files with 51 additions and 0 deletions
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51
drivers/amlogic/clk/g12a/g12a.h
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@@ -117,6 +117,57 @@ static const struct pll_rate_table g12a_pll_rate_table[] = {
PLL_RATE(696000000, 232, 1, 3), /*DCO=5568M*/
PLL_RATE(792000000, 132, 1, 2), /*DCO=3168M*/
PLL_RATE(912000000, 152, 1, 2), /*DCO=3648M*/
PLL_RATE(1008000000, 168, 1, 2), /*DCO=4032M*/
PLL_RATE(1104000000, 184, 1, 2), /*DCO=4416M*/
PLL_RATE(1200000000, 200, 1, 2), /*DCO=4800M*/
PLL_RATE(1296000000, 216, 1, 2), /*DCO=5184M*/
PLL_RATE(1398000000, 233, 1, 2), /*DCO=5592M*/
PLL_RATE(1494000000, 249, 1, 2), /*DCO=5976M*/
PLL_RATE(1608000000, 134, 1, 1), /*DCO=3216M*/
PLL_RATE(1704000000, 142, 1, 1), /*DCO=3408M*/
PLL_RATE(1800000000, 150, 1, 1), /*DCO=3600M*/
PLL_RATE(1896000000, 158, 1, 1), /*DCO=3792M*/
PLL_RATE(1992000000, 166, 1, 1), /*DCO=3984M*/
PLL_RATE(2100000000, 175, 1, 1), /*DCO=4200M*/
PLL_RATE(2196000000, 183, 1, 1), /*DCO=4392M*/
PLL_RATE(2292000000, 191, 1, 1), /*DCO=4584M*/
PLL_RATE(2400000000, 200, 1, 1), /*DCO=4800M*/
PLL_RATE(2496000000, 208, 1, 1), /*DCO=4992M*/
PLL_RATE(2592000000, 216, 1, 1), /*DCO=5184M*/
PLL_RATE(2700000000, 225, 1, 1), /*DCO=5400M*/
PLL_RATE(2796000000, 233, 1, 1), /*DCO=5592M*/
PLL_RATE(2892000000, 241, 1, 1), /*DCO=5784M*/
PLL_RATE(3000000000, 125, 1, 0), /*DCO=3000M*/
PLL_RATE(3096000000, 129, 1, 0), /*DCO=3096M*/
PLL_RATE(3192000000, 133, 1, 0), /*DCO=3192M*/
PLL_RATE(3288000000, 137, 1, 0), /*DCO=3288M*/
PLL_RATE(3408000000, 142, 1, 0), /*DCO=3408M*/
PLL_RATE(3504000000, 146, 1, 0), /*DCO=3504M*/
PLL_RATE(3600000000, 150, 1, 0), /*DCO=3600M*/
PLL_RATE(3696000000, 154, 1, 0), /*DCO=3696M*/
PLL_RATE(3792000000, 158, 1, 0), /*DCO=3792M*/
PLL_RATE(3888000000, 162, 1, 0), /*DCO=3888M*/
PLL_RATE(4008000000, 167, 1, 0), /*DCO=4008M*/
PLL_RATE(4104000000, 171, 1, 0), /*DCO=4104M*/
PLL_RATE(4200000000, 175, 1, 0), /*DCO=4200M*/
PLL_RATE(4296000000, 179, 1, 0), /*DCO=4296M*/
PLL_RATE(4392000000, 183, 1, 0), /*DCO=4392M*/
PLL_RATE(4488000000, 187, 1, 0), /*DCO=4488M*/
PLL_RATE(4608000000, 192, 1, 0), /*DCO=4608M*/
PLL_RATE(4704000000, 196, 1, 0), /*DCO=4704M*/
PLL_RATE(4800000000, 200, 1, 0), /*DCO=4800M*/
PLL_RATE(4896000000, 204, 1, 0), /*DCO=4896M*/
PLL_RATE(4992000000, 208, 1, 0), /*DCO=4992M*/
PLL_RATE(5088000000, 212, 1, 0), /*DCO=5088M*/
PLL_RATE(5208000000, 217, 1, 0), /*DCO=5208M*/
PLL_RATE(5304000000, 221, 1, 0), /*DCO=5304M*/
PLL_RATE(5400000000, 225, 1, 0), /*DCO=5400M*/
PLL_RATE(5496000000, 229, 1, 0), /*DCO=5496M*/
PLL_RATE(5592000000, 233, 1, 0), /*DCO=5592M*/
PLL_RATE(5688000000, 237, 1, 0), /*DCO=5688M*/
PLL_RATE(5808000000, 242, 1, 0), /*DCO=5808M*/
PLL_RATE(5904000000, 246, 1, 0), /*DCO=5904M*/
PLL_RATE(6000000000, 250, 1, 0), /*DCO=6000M*/
{ /* sentinel */ },
};