clk: rockchip: Add ROCKCHIP_DDRCLK Kconfig

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I5569cb9b52dd1f7fb702d8a37aef494fcc189c2c

drivers/clk/rockchip/Kconfig

@@ -166,18 +166,31 @@ config ROCKCHIP_CLK_PVTM
 	help
 	  Say y here to enable clk pvtm.
 
+config ROCKCHIP_DDRCLK
+	bool
+
 config ROCKCHIP_DDRCLK_SCPI
 	bool "Rockchip DDR Clk SCPI"
 	default y if RK3368_SCPI_PROTOCOL
+	select ROCKCHIP_DDRCLK
 	help
 	  Say y here to enable ddr clk scpi.
 
 config ROCKCHIP_DDRCLK_SIP
 	bool "Rockchip DDR Clk SIP"
 	default y if CPU_RK3399
+	select ROCKCHIP_DDRCLK
 	help
 	  Say y here to enable ddr clk sip.
 
+config ROCKCHIP_DDRCLK_SIP_V2
+	bool "Rockchip DDR Clk SIP V2"
+	default y if CPU_PX30   || CPU_RK1808 || CPU_RK312X || CPU_RK322X || \
+		     CPU_RK3288 || CPU_RK3308 || CPU_RK3328 || CPU_RV1126
+	select ROCKCHIP_DDRCLK
+	help
+	  Say y here to enable ddr clk sip v2.
+
 config ROCKCHIP_PLL_RK3066
 	bool "Rockchip PLL Type RK3066"
 	default y if CPU_RK30XX || CPU_RK3188 || \

drivers/clk/rockchip/Makefile

@@ -12,7 +12,7 @@ clk-rockchip-y += clk-cpu.o
 clk-rockchip-y += clk-half-divider.o
 clk-rockchip-y += clk-mmc-phase.o
 clk-rockchip-y += clk-muxgrf.o
-clk-rockchip-y += clk-ddr.o
+clk-rockchip-$(CONFIG_ROCKCHIP_DDRCLK) += clk-ddr.o
 clk-rockchip-$(CONFIG_ROCKCHIP_CLK_INV)  += clk-inverter.o
 clk-rockchip-$(CONFIG_ROCKCHIP_CLK_PVTM) += clk-pvtm.o
 clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o

drivers/clk/rockchip/clk-ddr.c

@@ -269,9 +269,11 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
 		init.ops = &rockchip_ddrclk_scpi_ops;
 		break;
 #endif
+#ifdef CONFIG_ROCKCHIP_DDRCLK_SIP_V2
 	case ROCKCHIP_DDRCLK_SIP_V2:
 		init.ops = &rockchip_ddrclk_sip_ops_v2;
 		break;
+#endif
 	default:
 		pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
 		kfree(ddrclk);

drivers/clk/rockchip/clk.h

@@ -596,6 +596,7 @@ struct clk *rockchip_clk_register_mmc(const char *name,
 #define ROCKCHIP_DDRCLK_SCPI		0x02
 #define ROCKCHIP_DDRCLK_SIP_V2		0x03
 
+#ifdef CONFIG_ROCKCHIP_DDRCLK
 void rockchip_set_ddrclk_params(void __iomem *params);
 void rockchip_set_ddrclk_dmcfreq_wait_complete(int (*func)(void));
 
@@ -605,6 +606,20 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
 					 int mux_shift, int mux_width,
 					 int div_shift, int div_width,
 					 int ddr_flags, void __iomem *reg_base);
+#else
+static inline void rockchip_set_ddrclk_params(void __iomem *params) {}
+static inline void rockchip_set_ddrclk_dmcfreq_wait_complete(int (*func)(void)) {}
+static inline
+struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
+					 const char *const *parent_names,
+					 u8 num_parents, int mux_offset,
+					 int mux_shift, int mux_width,
+					 int div_shift, int div_width,
+					 int ddr_flags, void __iomem *reg_base)
+{
+	return NULL;
+}
+#endif
 
 #define ROCKCHIP_INVERTER_HIWORD_MASK	BIT(0)