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arm64: dts: rockchip: rk1808: pick commits about rk1808 dtsi from v4.4
This patch do these operation: 42a2c3610d88 Revert "Revert "arm64: dts: rockchip: update iommu clk name from "hclk" to "iface""" ca40255ac827 arm64: dts: rockchip: adjust dmc opp-table for rk1808 3c867de9a7f3 arm64: dts: rockchip: rk1808: set PCIe as RC default 5eab28bdf11e arm64: dts: rockchip: rk1808: add usb3phy_grf_p for combo phy a3bb2719be95 arm64: dts: rockchip: rk1808: set min voltage for dmc when low temperature e0d40e1af1dd arm64: dts: rockchip: limit vdd_npu to 0.88V for rk1808 SoCs ccffc153ed72 arm64: dts: rockchip: rk1808: add mipi csi dts config ca3c7ea638a7 arm64: dts: rockchip: rk1808: Add wide-temperature configure 6d4c56b8202a arm64: dts: rockchip: Add system monitor node 77cd099b752f arm64: dts: rockchip: rk1808: disable peri ms and sram auto CS f4eb4471e1c2 arm64: dts: rockchip: rk1808: Correct the drive strength for rgmii/rmii 302df1d57c63 arm64: dts: rockchip: modify io driver strength for rk1808 6a8dfe606a0a arm64: dts: rockchip: rk1808: assigned-clock-parents for clk_32k_ioe c2901bf3f30e soc: rockchip: Change the parameter of power model for cpu and npu 71812e7394a4 arm64: dts: rockchip: add soc_bus support for rk1808 2463e3323cd7 arm64: dts: rockchip: adjust opp-table for rk1808 SoCs 4c3b6ea9751c arm64: dts: rockchip: rk1808: support cpu idle e2037aa67f8f Revert "arm64: dts: rockchip: rk1808: Correct the drive strength for rgmii/rmii" bca7a337bb60 Revert "soc: rockchip: Change the parameter of power model for cpu and npu" 63f5e887d360 Revert "arm64: dts: rockchip: Add system monitor node" d691a5bf4b5f Revert "arm64: dts: rockchip: update iommu clk name from "hclk" to "iface"" Change-Id: Ic5915c50019710b57d28e6d1833a6132af57c870 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This commit is contained in:
Jianqun Xu
@@ -53,6 +53,7 @@
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operating-points-v2 = <&cpu0_opp_table>;
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dynamic-power-coefficient = <74>;
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#cooling-cells = <2>;
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cpu-idle-states = <&CPU_SLEEP>;
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power-model {
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compatible = "simple-power-model";
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ref-leakage = <31>;
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@@ -70,6 +71,29 @@
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clocks = <&cru ARMCLK>;
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operating-points-v2 = <&cpu0_opp_table>;
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dynamic-power-coefficient = <74>;
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cpu-idle-states = <&CPU_SLEEP>;
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};
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idle-states {
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entry-method = "psci";
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CPU_SLEEP: cpu-sleep {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <120>;
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exit-latency-us = <250>;
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min-residency-us = <900>;
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};
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CLUSTER_SLEEP: cluster-sleep {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x1010000>;
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entry-latency-us = <400>;
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exit-latency-us = <500>;
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min-residency-us = <2000>;
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};
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};
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};
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@@ -77,9 +101,34 @@
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compatible = "operating-points-v2";
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opp-shared;
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rockchip,temp-hysteresis = <5000>;
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rockchip,low-temp = <0>;
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rockchip,low-temp-min-volt = <800000>;
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rockchip,low-temp-adjust-volt = <
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/* MHz MHz uV */
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0 1608 50000
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>;
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rockchip,max-volt = <950000>;
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rockchip,evb-irdrop = <25000>;
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nvmem-cells = <&cpu_leakage>;
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nvmem-cell-names = "leakage";
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rockchip,pvtm-voltage-sel = <
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0 69000 0
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69001 74000 1
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74001 99999 2
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>;
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rockchip,pvtm-freq = <408000>;
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rockchip,pvtm-volt = <800000>;
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rockchip,pvtm-ch = <0 0>;
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rockchip,pvtm-sample-time = <1000>;
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rockchip,pvtm-number = <10>;
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rockchip,pvtm-error = <1000>;
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rockchip,pvtm-ref-temp = <25>;
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rockchip,pvtm-temp-prop = <(-20) (-26)>;
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rockchip,thermal-zone = "soc-thermal";
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <750000 750000 950000>;
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@@ -103,7 +152,42 @@
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <750000 750000 950000>;
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opp-microvolt = <800000 800000 950000>;
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opp-microvolt-L0 = <800000 800000 950000>;
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opp-microvolt-L1 = <750000 750000 950000>;
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opp-microvolt-L2 = <750000 750000 950000>;
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clock-latency-ns = <40000>;
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};
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opp-1296000000 {
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opp-hz = /bits/ 64 <1296000000>;
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opp-microvolt = <825000 825000 950000>;
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opp-microvolt-L0 = <825000 825000 950000>;
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opp-microvolt-L1 = <775000 775000 950000>;
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opp-microvolt-L2 = <750000 750000 950000>;
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clock-latency-ns = <40000>;
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};
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opp-1416000000 {
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <850000 850000 950000>;
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opp-microvolt-L0 = <850000 850000 950000>;
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opp-microvolt-L1 = <800000 800000 950000>;
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opp-microvolt-L2 = <775000 775000 950000>;
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clock-latency-ns = <40000>;
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};
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opp-1512000000 {
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opp-hz = /bits/ 64 <1512000000>;
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opp-microvolt = <875000 875000 950000>;
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opp-microvolt-L0 = <875000 875000 950000>;
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opp-microvolt-L1 = <825000 825000 950000>;
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opp-microvolt-L2 = <800000 800000 950000>;
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clock-latency-ns = <40000>;
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};
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opp-1608000000 {
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opp-hz = /bits/ 64 <1608000000>;
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opp-microvolt = <900000 900000 950000>;
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opp-microvolt-L0 = <900000 900000 950000>;
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opp-microvolt-L1 = <850000 850000 950000>;
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opp-microvolt-L2 = <825000 825000 950000>;
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clock-latency-ns = <40000>;
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};
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};
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@@ -121,6 +205,41 @@
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nvmem-cell-names = "id", "cpu-version";
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};
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bus_soc: bus-soc {
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compatible = "rockchip,rk1808-bus";
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rockchip,busfreq-policy = "autocs";
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soc-bus0 {
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bus-id = <0>;
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timer-us = <20>;
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enable-msk = <0x407f>;
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status = "okay";
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};
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soc-bus1 {
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bus-id = <1>;
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timer-us = <200>;
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enable-msk = <0x41ff>;
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status = "okay";
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};
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soc-bus2 {
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bus-id = <2>;
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timer-us = <200>;
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enable-msk = <0x4005>;
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status = "okay";
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};
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soc-bus3 {
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bus-id = <3>;
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timer-us = <200>;
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enable-msk = <0x4001>;
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status = "okay";
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};
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soc-bus4 {
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bus-id = <4>;
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timer-us = <200>;
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enable-msk = <0x4001>;
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status = "disabled";
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};
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};
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gmac_clkin: external-gmac-clock {
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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@@ -179,7 +298,7 @@
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};
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pcie0: pcie@fc400000 {
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compatible = "rockchip,rk1808-pcie-ep", "snps,dw-pcie";
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compatible = "rockchip,rk1808-pcie", "snps,dw-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0x1f>;
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@@ -521,16 +640,20 @@
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compatible = "rockchip,rk1808-cru";
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reg = <0x0 0xff350000 0x0 0x5000>;
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rockchip,grf = <&grf>;
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rockchip,pmugrf = <&pmugrf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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assigned-clocks =
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<&cru SCLK_32K_IOE>,
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<&cru PLL_GPLL>, <&cru PLL_CPLL>,
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<&cru PLL_PPLL>, <&cru ARMCLK>,
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<&cru MSCLK_PERI>, <&cru LSCLK_PERI>,
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<&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>,
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<&cru LSCLK_BUS_PRE>;
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assigned-clock-parents = <&xin32k>;
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assigned-clock-rates =
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<32768>,
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<1188000000>, <1000000000>,
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<100000000>, <816000000>,
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<200000000>, <100000000>,
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@@ -571,9 +694,11 @@
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assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
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assigned-clock-rates = <25000000>;
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resets = <&cru SRST_USB3_OTG_A>, <&cru SRST_PCIEPHY_POR>,
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<&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>;
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<&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>,
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<&cru SRST_USB3PHY_GRF_P>;
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reset-names = "otg-rst", "combphy-por",
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"combphy-apb", "combphy-pipe";
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"combphy-apb", "combphy-pipe",
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"usb3phy_grf_p";
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rockchip,combphygrf = <&combphy_grf>;
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rockchip,usbpciegrf = <&usb_pcie_grf>;
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status = "disabled";
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@@ -1122,6 +1247,14 @@
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reg = <0x0 0xff640000 0x0 0x1000>;
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};
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rktimer: rktimer@ff700000 {
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compatible = "rockchip,rk3288-timer";
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reg = <0x0 0xff700000 0x0 0x1000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
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clock-names = "pclk", "timer";
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};
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wdt: watchdog@ff720000 {
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compatible = "snps,dw-wdt";
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reg = <0x0 0xff720000 0x0 0x100>;
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@@ -1248,15 +1381,20 @@
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dmc_opp_table: dmc-opp-table {
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compatible = "operating-points-v2";
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rockchip,max-volt = <950000>;
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rockchip,evb-irdrop = <12500>;
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nvmem-cells = <&logic_leakage>;
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nvmem-cell-names = "leakage";
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rockchip,temp-hysteresis = <5000>;
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rockchip,low-temp = <0>;
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rockchip,low-temp-min-volt = <800000>;
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opp-194000000 {
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opp-hz = /bits/ 64 <194000000>;
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opp-192000000 {
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opp-hz = /bits/ 64 <192000000>;
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opp-microvolt = <800000>;
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};
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opp-328000000 {
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opp-hz = /bits/ 64 <328000000>;
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opp-324000000 {
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opp-hz = /bits/ 64 <324000000>;
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opp-microvolt = <800000>;
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};
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opp-450000000 {
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@@ -1267,18 +1405,24 @@
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opp-hz = /bits/ 64 <528000000>;
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opp-microvolt = <800000>;
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};
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opp-666000000 {
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opp-hz = /bits/ 64 <666000000>;
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opp-664000000 {
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opp-hz = /bits/ 64 <664000000>;
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opp-microvolt = <800000>;
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};
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opp-786000000 {
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opp-hz = /bits/ 64 <786000000>;
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opp-784000000 {
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opp-hz = /bits/ 64 <784000000>;
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opp-microvolt = <800000>;
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};
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opp-924000000 {
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opp-hz = /bits/ 64 <924000000>;
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opp-microvolt = <800000>;
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};
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/* 1066M is only for ddr4 */
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opp-1066000000 {
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opp-hz = /bits/ 64 <1066000000>;
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opp-microvolt = <800000>;
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status = "disabled";
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};
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};
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rk_rga: rk_rga@ffaf0000 {
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@@ -1295,18 +1439,14 @@
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cif: cif@ffae0000 {
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compatible = "rockchip,rk1808-cif";
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reg = <0x0 0xffae0000 0x0 0x200>, <0x0 0xffb10000 0x0 0x100>;
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reg-names = "cif_regs", "csihost_regs";
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cif-intr", "csi-intr1", "csi-intr2";
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reg = <0x0 0xffae0000 0x0 0x200>;
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reg-names = "cif_regs";
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cif-intr";
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clocks = <&cru ACLK_CIF>, <&cru DCLK_CIF>,
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<&cru HCLK_CIF>, <&cru SCLK_CIF_OUT>,
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<&cru PCLK_CSI2HOST>;
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<&cru HCLK_CIF>, <&cru SCLK_CIF_OUT>;
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clock-names = "aclk_cif", "dclk_cif",
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"hclk_cif", "sclk_cif_out",
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"pclk_csi2host";
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"hclk_cif", "sclk_cif_out";
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resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>,
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<&cru SRST_CIF_I>, <&cru SRST_CIF_D>,
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<&cru SRST_CIF_PCLKIN>;
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@@ -1370,6 +1510,18 @@
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status = "disabled";
|
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};
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mipi_csi2: mipi-csi2@ffb10000 {
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compatible = "rockchip,rk1808-mipi-csi2";
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reg = <0x0 0xffb10000 0x0 0x100>;
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reg-names = "csihost_regs";
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "csi-intr1", "csi-intr2";
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clocks = <&cru PCLK_CSI2HOST>;
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clock-names = "pclk_csi2host";
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status = "disabled";
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||||
};
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csi_tx: csi@ffb20000 {
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compatible = "rockchip,rk1808-mipi-csi";
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reg = <0x0 0xffb20000 0x0 0x500>;
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@@ -1561,28 +1713,49 @@
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npu_opp_table: npu-opp-table {
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||||
compatible = "operating-points-v2";
|
||||
|
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rockchip,thermal-zone = "soc-thermal";
|
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rockchip,temp-hysteresis = <5000>;
|
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rockchip,low-temp = <0>;
|
||||
rockchip,low-temp-min-volt = <800000>;
|
||||
rockchip,low-temp-adjust-volt = <
|
||||
/* MHz MHz uV */
|
||||
0 792 50000
|
||||
>;
|
||||
|
||||
rockchip,max-volt = <880000>;
|
||||
rockchip,evb-irdrop = <37500>;
|
||||
nvmem-cells = <&npu_leakage>;
|
||||
nvmem-cell-names = "leakage";
|
||||
|
||||
rockchip,pvtm-voltage-sel = <
|
||||
0 69000 0
|
||||
69001 74000 1
|
||||
74001 99999 2
|
||||
>;
|
||||
rockchip,pvtm-ch = <0 0>;
|
||||
|
||||
opp-200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
opp-microvolt = <750000 750000 950000>;
|
||||
opp-microvolt = <750000 750000 880000>;
|
||||
};
|
||||
opp-297000000 {
|
||||
opp-hz = /bits/ 64 <297000000>;
|
||||
opp-microvolt = <750000 750000 950000>;
|
||||
opp-microvolt = <750000 750000 880000>;
|
||||
};
|
||||
opp-400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <750000 750000 950000>;
|
||||
opp-microvolt = <750000 750000 880000>;
|
||||
};
|
||||
opp-594000000 {
|
||||
opp-hz = /bits/ 64 <594000000>;
|
||||
opp-microvolt = <750000 750000 950000>;
|
||||
opp-microvolt = <750000 750000 880000>;
|
||||
};
|
||||
opp-792000000 {
|
||||
opp-hz = /bits/ 64 <792000000>;
|
||||
opp-microvolt = <750000 750000 950000>;
|
||||
opp-microvolt = <825000 825000 880000>;
|
||||
opp-microvolt-L0 = <825000 825000 880000>;
|
||||
opp-microvolt-L1 = <800000 800000 880000>;
|
||||
opp-microvolt-L2 = <775000 775000 880000>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -1885,7 +2058,7 @@
|
||||
emmc_clk: emmc-clk {
|
||||
rockchip,pins =
|
||||
/* emmc_clkout */
|
||||
<1 RK_PB1 1 &pcfg_pull_up_2ma>;
|
||||
<1 RK_PB1 1 &pcfg_pull_up_4ma>;
|
||||
};
|
||||
|
||||
emmc_rstnout: emmc-rstnout {
|
||||
@@ -1897,21 +2070,21 @@
|
||||
emmc_bus8: emmc-bus8 {
|
||||
rockchip,pins =
|
||||
/* emmc_d0 */
|
||||
<1 RK_PA0 1 &pcfg_pull_up_2ma>,
|
||||
<1 RK_PA0 1 &pcfg_pull_up_4ma>,
|
||||
/* emmc_d1 */
|
||||
<1 RK_PA1 1 &pcfg_pull_up_2ma>,
|
||||
<1 RK_PA1 1 &pcfg_pull_up_4ma>,
|
||||
/* emmc_d2 */
|
||||
<1 RK_PA2 1 &pcfg_pull_up_2ma>,
|
||||
<1 RK_PA2 1 &pcfg_pull_up_4ma>,
|
||||
/* emmc_d3 */
|
||||
<1 RK_PA3 1 &pcfg_pull_up_2ma>,
|
||||
<1 RK_PA3 1 &pcfg_pull_up_4ma>,
|
||||
/* emmc_d4 */
|
||||
<1 RK_PA4 1 &pcfg_pull_up_2ma>,
|
||||
<1 RK_PA4 1 &pcfg_pull_up_4ma>,
|
||||
/* emmc_d5 */
|
||||
<1 RK_PA5 1 &pcfg_pull_up_2ma>,
|
||||
<1 RK_PA5 1 &pcfg_pull_up_4ma>,
|
||||
/* emmc_d6 */
|
||||
<1 RK_PA6 1 &pcfg_pull_up_2ma>,
|
||||
<1 RK_PA6 1 &pcfg_pull_up_4ma>,
|
||||
/* emmc_d7 */
|
||||
<1 RK_PA7 1 &pcfg_pull_up_2ma>;
|
||||
<1 RK_PA7 1 &pcfg_pull_up_4ma>;
|
||||
};
|
||||
|
||||
emmc_pwren: emmc-pwren {
|
||||
@@ -1921,7 +2094,7 @@
|
||||
|
||||
emmc_cmd: emmc-cmd {
|
||||
rockchip,pins =
|
||||
<1 RK_PB2 1 &pcfg_pull_up_2ma>;
|
||||
<1 RK_PB2 1 &pcfg_pull_up_4ma>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -2395,23 +2568,23 @@
|
||||
sdmmc0_bus4: sdmmc0-bus4 {
|
||||
rockchip,pins =
|
||||
/* sdmmc0_d0 */
|
||||
<4 RK_PA2 1 &pcfg_pull_none>,
|
||||
<4 RK_PA2 1 &pcfg_pull_up_8ma>,
|
||||
/* sdmmc0_d1 */
|
||||
<4 RK_PA3 1 &pcfg_pull_none>,
|
||||
<4 RK_PA3 1 &pcfg_pull_up_8ma>,
|
||||
/* sdmmc0_d2 */
|
||||
<4 RK_PA4 1 &pcfg_pull_none>,
|
||||
<4 RK_PA4 1 &pcfg_pull_up_8ma>,
|
||||
/* sdmmc0_d3 */
|
||||
<4 RK_PA5 1 &pcfg_pull_none>;
|
||||
<4 RK_PA5 1 &pcfg_pull_up_8ma>;
|
||||
};
|
||||
|
||||
sdmmc0_cmd: sdmmc0-cmd {
|
||||
rockchip,pins =
|
||||
<4 RK_PA0 1 &pcfg_pull_none>;
|
||||
<4 RK_PA0 1 &pcfg_pull_up_8ma>;
|
||||
};
|
||||
|
||||
sdmmc0_clk: sdmmc0-clk {
|
||||
rockchip,pins =
|
||||
<4 RK_PA1 1 &pcfg_pull_none_4ma>;
|
||||
<4 RK_PA1 1 &pcfg_pull_up_8ma>;
|
||||
};
|
||||
|
||||
sdmmc0_detn: sdmmc0-detn {
|
||||
@@ -2424,23 +2597,23 @@
|
||||
sdmmc1_bus4: sdmmc1-bus4 {
|
||||
rockchip,pins =
|
||||
/* sdmmc1_d0 */
|
||||
<4 RK_PB0 1 &pcfg_pull_none>,
|
||||
<4 RK_PB0 1 &pcfg_pull_up_4ma>,
|
||||
/* sdmmc1_d1 */
|
||||
<4 RK_PB1 1 &pcfg_pull_none>,
|
||||
<4 RK_PB1 1 &pcfg_pull_up_4ma>,
|
||||
/* sdmmc1_d2 */
|
||||
<4 RK_PB2 1 &pcfg_pull_none>,
|
||||
<4 RK_PB2 1 &pcfg_pull_up_4ma>,
|
||||
/* sdmmc1_d3 */
|
||||
<4 RK_PB3 1 &pcfg_pull_none>;
|
||||
<4 RK_PB3 1 &pcfg_pull_up_4ma>;
|
||||
};
|
||||
|
||||
sdmmc1_cmd: sdmmc1-cmd {
|
||||
rockchip,pins =
|
||||
<4 RK_PA6 1 &pcfg_pull_none>;
|
||||
<4 RK_PA6 1 &pcfg_pull_up_4ma>;
|
||||
};
|
||||
|
||||
sdmmc1_clk: sdmmc1-clk {
|
||||
rockchip,pins =
|
||||
<4 RK_PA7 1 &pcfg_pull_none_4ma>;
|
||||
<4 RK_PA7 1 &pcfg_pull_up_4ma>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -2833,12 +3006,12 @@
|
||||
xin32k {
|
||||
clkin_32k: clkin-32k {
|
||||
rockchip,pins =
|
||||
<0 RK_PC2 1 &pcfg_input_smt>;
|
||||
<0 RK_PC2 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
clkout_32k: clkout-32k {
|
||||
rockchip,pins =
|
||||
<0 RK_PC2 1 &pcfg_output_high>;
|
||||
<0 RK_PC2 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user