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Merge tag 'v6.1.83' of git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable into odroidxu4-6.1.y

Browse Source 
Linux 6.1.83

Change-Id: I74bc8b5c00e4fd08c62d86f448c3a7089637d36f
This commit is contained in:
Mauro (mdrjr) Ribeiro
2024-05-07 11:23:49 -03:00
parent 39e9c6a8a9 e5cd595e23
commit 2fe443adb2
476 changed files with 4675 additions and 3376 deletions
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2
Makefile
View File

@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 6
PATCHLEVEL = 1
SUBLEVEL = 82
SUBLEVEL = 83
EXTRAVERSION =
NAME = Curry Ramen

2
arch/arm/boot/dts/arm-realview-pb1176.dts
View File

@@ -451,7 +451,7 @@
/* Direct-mapped development chip ROM */
pb1176_rom@10200000 {
compatible = "direct-mapped";
compatible = "mtd-rom";
reg = <0x10200000 0x4000>;
bank-width = <1>;
};

28
arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
View File

@@ -106,8 +106,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-reset-duration = <20>;
phy-supply = <&sw2_reg>;
status = "okay";
@@ -120,17 +118,10 @@
#address-cells = <1>;
#size-cells = <0>;
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
switch@10 {
compatible = "qca,qca8334";
reg = <10>;
reg = <0x10>;
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
switch_ports: ports {
#address-cells = <1>;
@@ -151,15 +142,30 @@
eth2: port@2 {
reg = <2>;
label = "eth2";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
eth1: port@3 {
reg = <3>;
label = "eth1";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port2: ethernet-phy@1 {
reg = <1>;
};
phy_port3: ethernet-phy@2 {
reg = <2>;
};
};
};
};
};

2
arch/arm/boot/dts/qcom-msm8974.dtsi
View File

@@ -1134,7 +1134,7 @@
qfprom: qfprom@fc4bc000 {
compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
reg = <0xfc4bc000 0x1000>;
reg = <0xfc4bc000 0x2100>;
#address-cells = <1>;
#size-cells = <1>;
tsens_calib: calib@d0 {

12
arch/arm/boot/dts/r8a73a4-ape6evm.dts
View File

@@ -209,6 +209,18 @@
status = "okay";
};
&extal1_clk {
clock-frequency = <26000000>;
};
&extal2_clk {
clock-frequency = <48000000>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&pfc {
scifa0_pins: scifa0 {
groups = "scifa0_data";

9
arch/arm/boot/dts/r8a73a4.dtsi
View File

@@ -450,17 +450,20 @@
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
extal1_clk: extal1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
extal2_clk: extal2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
fsiack_clk: fsiack {
compatible = "fixed-clock";

13
arch/arm/crypto/sha256_glue.c
View File

@@ -24,8 +24,8 @@
#include "sha256_glue.h"
asmlinkage void sha256_block_data_order(u32 *digest, const void *data,
unsigned int num_blks);
asmlinkage void sha256_block_data_order(struct sha256_state *state,
const u8 *data, int num_blks);
int crypto_sha256_arm_update(struct shash_desc *desc, const u8 *data,
unsigned int len)
@@ -33,23 +33,20 @@ int crypto_sha256_arm_update(struct shash_desc *desc, const u8 *data,
/* make sure casting to sha256_block_fn() is safe */
BUILD_BUG_ON(offsetof(struct sha256_state, state) != 0);
return sha256_base_do_update(desc, data, len,
(sha256_block_fn *)sha256_block_data_order);
return sha256_base_do_update(desc, data, len, sha256_block_data_order);
}
EXPORT_SYMBOL(crypto_sha256_arm_update);
static int crypto_sha256_arm_final(struct shash_desc *desc, u8 *out)
{
sha256_base_do_finalize(desc,
(sha256_block_fn *)sha256_block_data_order);
sha256_base_do_finalize(desc, sha256_block_data_order);
return sha256_base_finish(desc, out);
}
int crypto_sha256_arm_finup(struct shash_desc *desc, const u8 *data,
unsigned int len, u8 *out)
{
sha256_base_do_update(desc, data, len,
(sha256_block_fn *)sha256_block_data_order);
sha256_base_do_update(desc, data, len, sha256_block_data_order);
return crypto_sha256_arm_final(desc, out);
}
EXPORT_SYMBOL(crypto_sha256_arm_finup);

12
arch/arm/crypto/sha512-glue.c
View File

@@ -25,27 +25,25 @@ MODULE_ALIAS_CRYPTO("sha512");
MODULE_ALIAS_CRYPTO("sha384-arm");
MODULE_ALIAS_CRYPTO("sha512-arm");
asmlinkage void sha512_block_data_order(u64 *state, u8 const *src, int blocks);
asmlinkage void sha512_block_data_order(struct sha512_state *state,
u8 const *src, int blocks);
int sha512_arm_update(struct shash_desc *desc, const u8 *data,
unsigned int len)
{
return sha512_base_do_update(desc, data, len,
(sha512_block_fn *)sha512_block_data_order);
return sha512_base_do_update(desc, data, len, sha512_block_data_order);
}
static int sha512_arm_final(struct shash_desc *desc, u8 *out)
{
sha512_base_do_finalize(desc,
(sha512_block_fn *)sha512_block_data_order);
sha512_base_do_finalize(desc, sha512_block_data_order);
return sha512_base_finish(desc, out);
}
int sha512_arm_finup(struct shash_desc *desc, const u8 *data,
unsigned int len, u8 *out)
{
sha512_base_do_update(desc, data, len,
(sha512_block_fn *)sha512_block_data_order);
sha512_base_do_update(desc, data, len, sha512_block_data_order);
return sha512_arm_final(desc, out);
}

2
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
View File

@@ -291,6 +291,8 @@
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx_pin>;
status = "okay";
};

2
arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
View File

@@ -166,6 +166,8 @@
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx_pin>;
status = "okay";
};

7
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
View File

@@ -406,6 +406,7 @@
function = "spi1";
};
/omit-if-no-ref/
spdif_tx_pin: spdif-tx-pin {
pins = "PH7";
function = "spdif";
@@ -655,10 +656,8 @@
clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
clock-names = "apb", "spdif";
resets = <&ccu RST_BUS_SPDIF>;
dmas = <&dma 2>;
dma-names = "tx";
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx_pin>;
dmas = <&dma 2>, <&dma 2>;
dma-names = "rx", "tx";
status = "disabled";
};

1
arch/arm64/boot/dts/amazon/alpine-v2.dtsi
View File

@@ -145,7 +145,6 @@
msix: msix@fbe00000 {
compatible = "al,alpine-msix";
reg = <0x0 0xfbe00000 0x0 0x100000>;
interrupt-controller;
msi-controller;
al,msi-base-spi = <160>;
al,msi-num-spis = <160>;

1
arch/arm64/boot/dts/amazon/alpine-v3.dtsi
View File

@@ -351,7 +351,6 @@
msix: msix@fbe00000 {
compatible = "al,alpine-msix";
reg = <0x0 0xfbe00000 0x0 0x100000>;
interrupt-controller;
msi-controller;
al,msi-base-spi = <336>;
al,msi-num-spis = <959>;

3
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
View File

@@ -180,9 +180,6 @@
brcm,num-gphy = <5>;
brcm,num-rgmii-ports = <2>;
#address-cells = <1>;
#size-cells = <0>;
ports: ports {
#address-cells = <1>;
#size-cells = <0>;

1
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
View File

@@ -584,6 +584,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
};

1
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
View File

@@ -442,6 +442,7 @@
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&pinmux 0 0 16>,
<&pinmux 16 71 2>,

38
arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts
View File

@@ -294,8 +294,8 @@
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083
>;
};
@@ -313,19 +313,19 @@
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0
>;
};
@@ -337,40 +337,40 @@
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
};

38
arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
View File

@@ -277,8 +277,8 @@
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083
>;
};
@@ -290,19 +290,19 @@
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0
>;
};
@@ -314,40 +314,40 @@
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0
>;
};
};

6
arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi
View File

@@ -205,7 +205,7 @@
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_LOW>;
trickle-diode-disable;
};
};
@@ -247,8 +247,8 @@
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083
>;
};

4
arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi
View File

@@ -237,8 +237,8 @@
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083
>;
};

29
arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
View File

@@ -47,17 +47,6 @@
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1_en>;
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
/* off-board header */
@@ -146,9 +135,10 @@
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
dr_mode = "otg";
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
@@ -206,14 +196,6 @@
>;
};
pinctrl_reg_usb1_en: regusb1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
>;
};
pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
@@ -236,4 +218,11 @@
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
>;
};
};

1
arch/arm64/boot/dts/lg/lg1312.dtsi
View File

@@ -124,7 +124,6 @@
amba {
#address-cells = <2>;
#size-cells = <1>;
#interrupt-cells = <3>;
compatible = "simple-bus";
interrupt-parent = <&gic>;

1
arch/arm64/boot/dts/lg/lg1313.dtsi
View File

@@ -124,7 +124,6 @@
amba {
#address-cells = <2>;
#size-cells = <1>;
#interrupt-cells = <3>;
compatible = "simple-bus";
interrupt-parent = <&gic>;

10
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View File

@@ -426,14 +426,14 @@
crypto: crypto@90000 {
compatible = "inside-secure,safexcel-eip97ies";
reg = <0x90000 0x20000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ring0", "ring1", "ring2",
"ring3", "eip", "mem";
clocks = <&nb_periph_clk 15>;
};

1
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
View File

@@ -133,7 +133,6 @@
odmi: odmi@300000 {
compatible = "marvell,odmi-controller";
interrupt-controller;
msi-controller;
marvell,odmi-frames = <4>;
reg = <0x300000 0x4000>,

10
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
View File

@@ -506,14 +506,14 @@
CP11X_LABEL(crypto): crypto@800000 {
compatible = "inside-secure,safexcel-eip197b";
reg = <0x800000 0x200000>;
interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
<88 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <88 IRQ_TYPE_LEVEL_HIGH>,
<89 IRQ_TYPE_LEVEL_HIGH>,
<90 IRQ_TYPE_LEVEL_HIGH>,
<91 IRQ_TYPE_LEVEL_HIGH>,
<92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
<92 IRQ_TYPE_LEVEL_HIGH>,
<87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ring0", "ring1", "ring2", "ring3",
"eip", "mem";
clock-names = "core", "reg";
clocks = <&CP11X_LABEL(clk) 1 26>,
<&CP11X_LABEL(clk) 1 17>;

1
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
View File

@@ -74,6 +74,7 @@
memory@40000000 {
reg = <0 0x40000000 0 0x40000000>;
device_type = "memory";
};
reg_1p8v: regulator-1p8v {

1
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
View File

@@ -56,6 +56,7 @@
memory@40000000 {
reg = <0 0x40000000 0 0x20000000>;
device_type = "memory";
};
reg_1p8v: regulator-1p8v {

1
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
View File

@@ -110,6 +110,7 @@
compatible = "mediatek,mt7986-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
wed_pcie: wed-pcie@10003000 {

2
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
View File

@@ -4,6 +4,8 @@
*/
#include "mt8183-kukui.dtsi"
/* Must come after mt8183-kukui.dtsi to modify cros_ec */
#include <arm/cros-ec-keyboard.dtsi>
/ {
panel: panel {

10
arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
View File

@@ -372,6 +372,16 @@
};
};
&cros_ec {
cbas {
compatible = "google,cros-cbas";
};
keyboard-controller {
compatible = "google,cros-ec-keyb-switches";
};
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_KAKADU";
};

10
arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi
View File

@@ -339,6 +339,16 @@
};
};
&cros_ec {
cbas {
compatible = "google,cros-cbas";
};
keyboard-controller {
compatible = "google,cros-ec-keyb-switches";
};
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_KODAMA";
};

10
arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi
View File

@@ -343,6 +343,16 @@
};
};
&cros_ec {
cbas {
compatible = "google,cros-cbas";
};
keyboard-controller {
compatible = "google,cros-ec-keyb-switches";
};
};
&qca_wifi {
qcom,ath10k-calibration-variant = "LE_Krane";
};

5
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@@ -896,10 +896,6 @@
google,usb-port-id = <0>;
};
cbas {
compatible = "google,cros-cbas";
};
typec {
compatible = "google,cros-ec-typec";
#address-cells = <1>;
@@ -999,5 +995,4 @@
};
};
#include <arm/cros-ec-keyboard.dtsi>
#include <arm/cros-ec-sbs.dtsi>

4
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
View File

@@ -819,10 +819,6 @@
#address-cells = <1>;
#size-cells = <0>;
base_detection: cbas {
compatible = "google,cros-cbas";
};
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";
#pwm-cells = <1>;

2
arch/arm64/boot/dts/mediatek/mt8192.dtsi
View File

@@ -1539,7 +1539,7 @@
mediatek,scp = <&scp>;
power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
clocks = <&vencsys CLK_VENC_SET1_VENC>;
clock-names = "venc-set1";
clock-names = "venc_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
};

4
arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts
View File

@@ -13,3 +13,7 @@
&ts_10 {
status = "okay";
};
&watchdog {
/delete-property/ mediatek,disable-extrst;
};

4
arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts
View File

@@ -33,3 +33,7 @@
&ts_10 {
status = "okay";
};
&watchdog {
/delete-property/ mediatek,disable-extrst;
};

4
arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts
View File

@@ -34,3 +34,7 @@
&ts_10 {
status = "okay";
};
&watchdog {
/delete-property/ mediatek,disable-extrst;
};

1
arch/arm64/boot/dts/mediatek/mt8195-demo.dts
View File

@@ -111,6 +111,7 @@
compatible = "mediatek,mt6360";
reg = <0x34>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
interrupt-names = "IRQB";

2
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
View File

@@ -2024,7 +2024,7 @@
status = "okay";
phy-handle = <&mgbe0_phy>;
phy-mode = "usxgmii";
phy-mode = "10gbase-r";
mdio {
#address-cells = <1>;

2
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View File

@@ -532,7 +532,7 @@
&pcie0 {
status = "okay";
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>;
wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
vddpe-3v3-supply = <&pcie0_3p3v_dual>;

6
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@@ -1822,8 +1822,8 @@
phys = <&pcie0_lane>;
phy-names = "pciephy";
perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
@@ -1925,7 +1925,7 @@
phys = <&pcie1_lane>;
phy-names = "pciephy";
perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";

28
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View File

@@ -656,8 +656,8 @@
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>;
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6800000 0 0x1000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
@@ -704,8 +704,8 @@
avb1: ethernet@e6810000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6810000 0 0x800>;
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6810000 0 0x1000>;
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
@@ -752,7 +752,7 @@
avb2: ethernet@e6820000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6820000 0 0x1000>;
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
@@ -800,7 +800,7 @@
avb3: ethernet@e6830000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6830000 0 0x1000>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
@@ -848,7 +848,7 @@
avb4: ethernet@e6840000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6840000 0 0x1000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
@@ -896,7 +896,7 @@
avb5: ethernet@e6850000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6850000 0 0x1000>;
interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
@@ -1019,7 +1019,7 @@
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
"renesas,rcar-gen4-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 618>;
@@ -1034,7 +1034,7 @@
msiof1: spi@e6ea0000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
"renesas,rcar-gen4-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 619>;
@@ -1049,7 +1049,7 @@
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 620>;
@@ -1064,7 +1064,7 @@
msiof3: spi@e6c10000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
@@ -1079,7 +1079,7 @@
msiof4: spi@e6c20000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c20000 0 0x0064>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
@@ -1094,7 +1094,7 @@
msiof5: spi@e6c28000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c28000 0 0x0064>;
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;

4
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
View File

@@ -337,7 +337,7 @@
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779g0",
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6800000 0 0x800>;
reg = <0 0xe6800000 0 0x1000>;
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
@@ -384,7 +384,7 @@
avb1: ethernet@e6810000 {
compatible = "renesas,etheravb-r8a779g0",
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6810000 0 0x800>;
reg = <0 0xe6810000 0 0x1000>;
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,

54
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2UL SoC
* Device Tree Source for the RZ/Five and RZ/G2UL SoCs
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
@@ -68,36 +68,8 @@
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
#cooling-cells = <2>;
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -545,12 +517,6 @@
sysc: system-controller@11020000 {
compatible = "renesas,r9a07g043-sysc";
reg = <0 0x11020000 0 0x10000>;
interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "lpm_int", "ca55stbydone_int",
"cm33stbyr_int", "ca55_deny";
status = "disabled";
};
@@ -603,16 +569,6 @@
dma-channels = <16>;
};
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x11900000 0 0x40000>,
<0x0 0x11940000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
@@ -893,12 +849,4 @@
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};

136
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
View File

@@ -10,3 +10,139 @@
#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
#include "r9a07g043.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
#cooling-cells = <2>;
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};
&soc {
interrupt-parent = <&gic>;
irqc: interrupt-controller@110a0000 {
compatible = "renesas,r9a07g043u-irqc",
"renesas,rzg2l-irqc";
reg = <0 0x110a0000 0 0x10000>;
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "nmi",
"irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
"tint0", "tint1", "tint2", "tint3",
"tint4", "tint5", "tint6", "tint7",
"tint8", "tint9", "tint10", "tint11",
"tint12", "tint13", "tint14", "tint15",
"tint16", "tint17", "tint18", "tint19",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31",
"bus-err", "ec7tie1-0", "ec7tie2-0",
"ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
"ec7tiovf-1";
clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>,
<&cpg CPG_MOD R9A07G043_IA55_PCLK>;
clock-names = "clk", "pclk";
power-domains = <&cpg>;
resets = <&cpg R9A07G043_IA55_RESETN>;
};
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x11900000 0 0x40000>,
<0x0 0x11940000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
};
&sysc {
interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "lpm_int", "ca55stbydone_int",
"cm33stbyr_int", "ca55_deny";
};

22
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@@ -698,7 +698,27 @@
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
"tint0", "tint1", "tint2", "tint3",
"tint4", "tint5", "tint6", "tint7",
"tint8", "tint9", "tint10", "tint11",
"tint12", "tint13", "tint14", "tint15",
"tint16", "tint17", "tint18", "tint19",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31",
"bus-err", "ec7tie1-0", "ec7tie2-0",
"ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
"ec7tiovf-1";
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
clock-names = "clk", "pclk";

22
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View File

@@ -704,7 +704,27 @@
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3",
"irq4", "irq5", "irq6", "irq7",
"tint0", "tint1", "tint2", "tint3",
"tint4", "tint5", "tint6", "tint7",
"tint8", "tint9", "tint10", "tint11",
"tint12", "tint13", "tint14", "tint15",
"tint16", "tint17", "tint18", "tint19",
"tint20", "tint21", "tint22", "tint23",
"tint24", "tint25", "tint26", "tint27",
"tint28", "tint29", "tint30", "tint31",
"bus-err", "ec7tie1-0", "ec7tie2-0",
"ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
"ec7tiovf-1";
clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
<&cpg CPG_MOD R9A07G054_IA55_PCLK>;
clock-names = "clk", "pclk";

4
arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
View File

@@ -251,6 +251,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio6>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
@@ -311,6 +312,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio6>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
};
@@ -331,6 +333,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio7>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
};
@@ -341,6 +344,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio5>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
};

1
arch/arm64/boot/dts/rockchip/rk356x.dtsi
View File

@@ -596,6 +596,7 @@
compatible = "rockchip,rk3568-vpu";
reg = <0x0 0xfdea0000 0x0 0x800>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vdpu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "hclk";
iommus = <&vdpu_mmu>;

12
arch/arm64/include/asm/fpsimd.h
View File

@@ -36,13 +36,13 @@
* When we defined the maximum SVE vector length we defined the ABI so
* that the maximum vector length included all the reserved for future
* expansion bits in ZCR rather than those just currently defined by
* the architecture. While SME follows a similar pattern the fact that
* it includes a square matrix means that any allocations that attempt
* to cover the maximum potential vector length (such as happen with
* the regset used for ptrace) end up being extremely large. Define
* the much lower actual limit for use in such situations.
* the architecture. Using this length to allocate worst size buffers
* results in excessively large allocations, and this effect is even
* more pronounced for SME due to ZA. Define more suitable VLs for
* these situations.
*/
#define SME_VQ_MAX 16
#define ARCH_SVE_VQ_MAX ((ZCR_ELx_LEN_MASK >> ZCR_ELx_LEN_SHIFT) + 1)
#define SME_VQ_MAX ((SMCR_ELx_LEN_MASK >> SMCR_ELx_LEN_SHIFT) + 1)
struct task_struct;

3
arch/arm64/kernel/ptrace.c
View File

@@ -1450,7 +1450,8 @@ static const struct user_regset aarch64_regsets[] = {
#ifdef CONFIG_ARM64_SVE
[REGSET_SVE] = { /* Scalable Vector Extension */
.core_note_type = NT_ARM_SVE,
.n = DIV_ROUND_UP(SVE_PT_SIZE(SVE_VQ_MAX, SVE_PT_REGS_SVE),
.n = DIV_ROUND_UP(SVE_PT_SIZE(ARCH_SVE_VQ_MAX,
SVE_PT_REGS_SVE),
SVE_VQ_BYTES),
.size = SVE_VQ_BYTES,
.align = SVE_VQ_BYTES,

1
arch/mips/include/asm/ptrace.h
View File

@@ -60,6 +60,7 @@ static inline void instruction_pointer_set(struct pt_regs *regs,
unsigned long val)
{
regs->cp0_epc = val;
regs->cp0_cause &= ~CAUSEF_BD;
}
/* Query offset/name of register from its name/offset */

2
arch/parisc/kernel/ftrace.c
View File

@@ -78,7 +78,7 @@ void notrace __hot ftrace_function_trampoline(unsigned long parent,
#endif
}
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
#if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_FUNCTION_GRAPH_TRACER)
int ftrace_enable_ftrace_graph_caller(void)
{
static_key_enable(&ftrace_graph_enable.key);

4
arch/powerpc/include/asm/vmalloc.h
View File

@@ -7,14 +7,14 @@
#ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
#define arch_vmap_pud_supported arch_vmap_pud_supported
static inline bool arch_vmap_pud_supported(pgprot_t prot)
static __always_inline bool arch_vmap_pud_supported(pgprot_t prot)
{
/* HPT does not cope with large pages in the vmalloc area */
return radix_enabled();
}
#define arch_vmap_pmd_supported arch_vmap_pmd_supported
static inline bool arch_vmap_pmd_supported(pgprot_t prot)
static __always_inline bool arch_vmap_pmd_supported(pgprot_t prot)
{
return radix_enabled();
}

29
arch/powerpc/perf/hv-gpci.c
View File

@@ -164,6 +164,20 @@ static unsigned long single_gpci_request(u32 req, u32 starting_index,
ret = plpar_hcall_norets(H_GET_PERF_COUNTER_INFO,
virt_to_phys(arg), HGPCI_REQ_BUFFER_SIZE);
/*
* ret value as 'H_PARAMETER' with detail_rc as 'GEN_BUF_TOO_SMALL',
* specifies that the current buffer size cannot accommodate
* all the information and a partial buffer returned.
* Since in this function we are only accessing data for a given starting index,
* we don't need to accommodate whole data and can get required count by
* accessing first entry data.
* Hence hcall fails only incase the ret value is other than H_SUCCESS or
* H_PARAMETER with detail_rc value as GEN_BUF_TOO_SMALL(0x1B).
*/
if (ret == H_PARAMETER && be32_to_cpu(arg->params.detail_rc) == 0x1B)
ret = 0;
if (ret) {
pr_devel("hcall failed: 0x%lx\n", ret);
goto out;
@@ -228,6 +242,7 @@ static int h_gpci_event_init(struct perf_event *event)
{
u64 count;
u8 length;
unsigned long ret;
/* Not our event */
if (event->attr.type != event->pmu->type)
@@ -258,13 +273,23 @@ static int h_gpci_event_init(struct perf_event *event)
}
/* check if the request works... */
if (single_gpci_request(event_get_request(event),
ret = single_gpci_request(event_get_request(event),
event_get_starting_index(event),
event_get_secondary_index(event),
event_get_counter_info_version(event),
event_get_offset(event),
length,
&count)) {
&count);
/*
* ret value as H_AUTHORITY implies that partition is not permitted to retrieve
* performance information, and required to set
* "Enable Performance Information Collection" option.
*/
if (ret == H_AUTHORITY)
return -EPERM;
if (ret) {
pr_devel("gpci hcall failed\n");
return -EINVAL;
}

3
arch/powerpc/platforms/embedded6xx/linkstation.c
View File

@@ -99,9 +99,6 @@ static void __init linkstation_init_IRQ(void)
mpic_init(mpic);
}
extern void avr_uart_configure(void);
extern void avr_uart_send(const char);
static void __noreturn linkstation_restart(char *cmd)
{
local_irq_disable();

3
arch/powerpc/platforms/embedded6xx/mpc10x.h
View File

@@ -156,4 +156,7 @@ int mpc10x_disable_store_gathering(struct pci_controller *hose);
/* For MPC107 boards that use the built-in openpic */
void mpc10x_set_openpic(void);
void avr_uart_configure(void);
void avr_uart_send(const char c);
#endif /* __PPC_KERNEL_MPC10X_H */

8
arch/powerpc/platforms/pseries/papr_platform_attributes.c
View File

@@ -101,10 +101,12 @@ retry:
esi_buf_size = ESI_HDR_SIZE + (CURR_MAX_ESI_ATTRS * max_esi_attrs);
temp_buf = krealloc(buf, esi_buf_size, GFP_KERNEL);
if (temp_buf)
if (temp_buf) {
buf = temp_buf;
else
return -ENOMEM;
} else {
ret = -ENOMEM;
goto out_buf;
}
goto retry;
}

1
arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
View File

@@ -123,6 +123,7 @@
interrupt-parent = <&gpio>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
onkey {
compatible = "dlg,da9063-onkey";

2
arch/s390/include/uapi/asm/dasd.h
View File

@@ -78,6 +78,7 @@ typedef struct dasd_information2_t {
* 0x040: give access to raw eckd data
* 0x080: enable discard support
* 0x100: enable autodisable for IFCC errors (default)
* 0x200: enable requeue of all requests on autoquiesce
*/
#define DASD_FEATURE_READONLY 0x001
#define DASD_FEATURE_USEDIAG 0x002
@@ -88,6 +89,7 @@ typedef struct dasd_information2_t {
#define DASD_FEATURE_USERAW 0x040
#define DASD_FEATURE_DISCARD 0x080
#define DASD_FEATURE_PATH_AUTODISABLE 0x100
#define DASD_FEATURE_REQUEUEQUIESCE 0x200
#define DASD_FEATURE_DEFAULT DASD_FEATURE_PATH_AUTODISABLE
#define DASD_PARTN_BITS 2

1
arch/s390/kernel/cache.c
View File

@@ -166,5 +166,6 @@ int populate_cache_leaves(unsigned int cpu)
ci_leaf_init(this_leaf++, pvt, ctype, level, cpu);
}
}
this_cpu_ci->cpu_map_populated = true;
return 0;
}

2
arch/s390/kernel/perf_pai_crypto.c
View File

@@ -647,7 +647,7 @@ static int __init attr_event_init(void)
for (i = 0; i < ARRAY_SIZE(paicrypt_ctrnames); i++) {
ret = attr_event_init_one(attrs, i);
if (ret) {
attr_event_free(attrs, i - 1);
attr_event_free(attrs, i);
return ret;
}
}

2
arch/s390/kernel/perf_pai_ext.c
View File

@@ -612,7 +612,7 @@ static int __init attr_event_init(void)
for (i = 0; i < ARRAY_SIZE(paiext_ctrnames); i++) {
ret = attr_event_init_one(attrs, i);
if (ret) {
attr_event_free(attrs, i - 1);
attr_event_free(attrs, i);
return ret;
}
}

2
arch/s390/kernel/vdso32/Makefile
View File

@@ -22,7 +22,7 @@ KBUILD_AFLAGS_32 += -m31 -s
KBUILD_CFLAGS_32 := $(filter-out -m64,$(KBUILD_CFLAGS))
KBUILD_CFLAGS_32 += -m31 -fPIC -shared -fno-common -fno-builtin
LDFLAGS_vdso32.so.dbg += -fPIC -shared -soname=linux-vdso32.so.1 \
LDFLAGS_vdso32.so.dbg += -shared -soname=linux-vdso32.so.1 \
--hash-style=both --build-id=sha1 -melf_s390 -T
$(targets:%=$(obj)/%.dbg): KBUILD_CFLAGS = $(KBUILD_CFLAGS_32)

2
arch/s390/kernel/vdso64/Makefile
View File

@@ -26,7 +26,7 @@ KBUILD_AFLAGS_64 += -m64 -s
KBUILD_CFLAGS_64 := $(filter-out -m64,$(KBUILD_CFLAGS))
KBUILD_CFLAGS_64 += -m64 -fPIC -fno-common -fno-builtin
ldflags-y := -fPIC -shared -soname=linux-vdso64.so.1 \
ldflags-y := -shared -soname=linux-vdso64.so.1 \
--hash-style=both --build-id=sha1 -T
$(targets:%=$(obj)/%.dbg): KBUILD_CFLAGS = $(KBUILD_CFLAGS_64)

4
arch/s390/kernel/vtime.c
View File

@@ -210,13 +210,13 @@ void vtime_flush(struct task_struct *tsk)
virt_timer_expire();
steal = S390_lowcore.steal_timer;
avg_steal = S390_lowcore.avg_steal_timer / 2;
avg_steal = S390_lowcore.avg_steal_timer;
if ((s64) steal > 0) {
S390_lowcore.steal_timer = 0;
account_steal_time(cputime_to_nsecs(steal));
avg_steal += steal;
}
S390_lowcore.avg_steal_timer = avg_steal;
S390_lowcore.avg_steal_timer = avg_steal / 2;
}
static u64 vtime_delta(void)

2
arch/sparc/kernel/leon_pci_grpci1.c
View File

@@ -696,7 +696,7 @@ err1:
return err;
}
static const struct of_device_id grpci1_of_match[] __initconst = {
static const struct of_device_id grpci1_of_match[] = {
{
.name = "GAISLER_PCIFBRG",
},

2
arch/sparc/kernel/leon_pci_grpci2.c
View File

@@ -887,7 +887,7 @@ err1:
return err;
}
static const struct of_device_id grpci2_of_match[] __initconst = {
static const struct of_device_id grpci2_of_match[] = {
{
.name = "GAISLER_GRPCI2",
},

1
arch/x86/events/amd/core.c
View File

@@ -604,7 +604,6 @@ static void amd_pmu_cpu_dead(int cpu)
kfree(cpuhw->lbr_sel);
cpuhw->lbr_sel = NULL;
amd_pmu_cpu_reset(cpu);
if (!x86_pmu.amd_nb_constraints)
return;

10
arch/x86/include/asm/vsyscall.h
View File

@@ -4,6 +4,7 @@
#include <linux/seqlock.h>
#include <uapi/asm/vsyscall.h>
#include <asm/page_types.h>
#ifdef CONFIG_X86_VSYSCALL_EMULATION
extern void map_vsyscall(void);
@@ -24,4 +25,13 @@ static inline bool emulate_vsyscall(unsigned long error_code,
}
#endif
/*
* The (legacy) vsyscall page is the long page in the kernel portion
* of the address space that has user-accessible permissions.
*/
static inline bool is_vsyscall_vaddr(unsigned long vaddr)
{
return unlikely((vaddr & PAGE_MASK) == VSYSCALL_ADDR);
}
#endif /* _ASM_X86_VSYSCALL_H */

2
arch/x86/kernel/acpi/cppc.c
View File

@@ -20,7 +20,7 @@ bool cpc_supported_by_cpu(void)
(boot_cpu_data.x86_model >= 0x20 && boot_cpu_data.x86_model <= 0x2f)))
return true;
else if (boot_cpu_data.x86 == 0x17 &&
boot_cpu_data.x86_model >= 0x70 && boot_cpu_data.x86_model <= 0x7f)
boot_cpu_data.x86_model >= 0x30 && boot_cpu_data.x86_model <= 0x7f)
return true;
return boot_cpu_has(X86_FEATURE_CPPC);
}

4
arch/x86/kernel/cpu/resctrl/internal.h
View File

@@ -281,14 +281,10 @@ struct rftype {
* struct mbm_state - status for each MBM counter in each domain
* @prev_bw_bytes: Previous bytes value read for bandwidth calculation
* @prev_bw: The most recent bandwidth in MBps
* @delta_bw: Difference between the current and previous bandwidth
* @delta_comp: Indicates whether to compute the delta_bw
*/
struct mbm_state {
u64 prev_bw_bytes;
u32 prev_bw;
u32 delta_bw;
bool delta_comp;
};
/**

42
arch/x86/kernel/cpu/resctrl/monitor.c
View File

@@ -428,9 +428,6 @@ static void mbm_bw_count(u32 rmid, struct rmid_read *rr)
cur_bw = bytes / SZ_1M;
if (m->delta_comp)
m->delta_bw = abs(cur_bw - m->prev_bw);
m->delta_comp = false;
m->prev_bw = cur_bw;
}
@@ -508,11 +505,11 @@ static void update_mba_bw(struct rdtgroup *rgrp, struct rdt_domain *dom_mbm)
{
u32 closid, rmid, cur_msr_val, new_msr_val;
struct mbm_state *pmbm_data, *cmbm_data;
u32 cur_bw, delta_bw, user_bw;
struct rdt_resource *r_mba;
struct rdt_domain *dom_mba;
struct list_head *head;
struct rdtgroup *entry;
u32 cur_bw, user_bw;
if (!is_mbm_local_enabled())
return;
@@ -531,7 +528,6 @@ static void update_mba_bw(struct rdtgroup *rgrp, struct rdt_domain *dom_mbm)
cur_bw = pmbm_data->prev_bw;
user_bw = dom_mba->mbps_val[closid];
delta_bw = pmbm_data->delta_bw;
/* MBA resource doesn't support CDP */
cur_msr_val = resctrl_arch_get_config(r_mba, dom_mba, closid, CDP_NONE);
@@ -543,49 +539,31 @@ static void update_mba_bw(struct rdtgroup *rgrp, struct rdt_domain *dom_mbm)
list_for_each_entry(entry, head, mon.crdtgrp_list) {
cmbm_data = &dom_mbm->mbm_local[entry->mon.rmid];
cur_bw += cmbm_data->prev_bw;
delta_bw += cmbm_data->delta_bw;
}
/*
* Scale up/down the bandwidth linearly for the ctrl group. The
* bandwidth step is the bandwidth granularity specified by the
* hardware.
*
* The delta_bw is used when increasing the bandwidth so that we
* dont alternately increase and decrease the control values
* continuously.
*
* For ex: consider cur_bw = 90MBps, user_bw = 100MBps and if
* bandwidth step is 20MBps(> user_bw - cur_bw), we would keep
* switching between 90 and 110 continuously if we only check
* cur_bw < user_bw.
* Always increase throttling if current bandwidth is above the
* target set by user.
* But avoid thrashing up and down on every poll by checking
* whether a decrease in throttling is likely to push the group
* back over target. E.g. if currently throttling to 30% of bandwidth
* on a system with 10% granularity steps, check whether moving to
* 40% would go past the limit by multiplying current bandwidth by
* "(30 + 10) / 30".
*/
if (cur_msr_val > r_mba->membw.min_bw && user_bw < cur_bw) {
new_msr_val = cur_msr_val - r_mba->membw.bw_gran;
} else if (cur_msr_val < MAX_MBA_BW &&
(user_bw > (cur_bw + delta_bw))) {
(user_bw > (cur_bw * (cur_msr_val + r_mba->membw.min_bw) / cur_msr_val))) {
new_msr_val = cur_msr_val + r_mba->membw.bw_gran;
} else {
return;
}
resctrl_arch_update_one(r_mba, dom_mba, closid, CDP_NONE, new_msr_val);
/*
* Delta values are updated dynamically package wise for each
* rdtgrp every time the throttle MSR changes value.
*
* This is because (1)the increase in bandwidth is not perfectly
* linear and only "approximately" linear even when the hardware
* says it is linear.(2)Also since MBA is a core specific
* mechanism, the delta values vary based on number of cores used
* by the rdtgrp.
*/
pmbm_data->delta_comp = true;
list_for_each_entry(entry, head, mon.crdtgrp_list) {
cmbm_data = &dom_mbm->mbm_local[entry->mon.rmid];
cmbm_data->delta_comp = true;
}
}
static void mbm_update(struct rdt_resource *r, struct rdt_domain *d, int rmid)

9
arch/x86/mm/fault.c
View File

@@ -818,15 +818,6 @@ show_signal_msg(struct pt_regs *regs, unsigned long error_code,
show_opcodes(regs, loglvl);
}
/*
* The (legacy) vsyscall page is the long page in the kernel portion
* of the address space that has user-accessible permissions.
*/
static bool is_vsyscall_vaddr(unsigned long vaddr)
{
return unlikely((vaddr & PAGE_MASK) == VSYSCALL_ADDR);
}
static void
__bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code,
unsigned long address, u32 pkey, int si_code)

10
arch/x86/mm/maccess.c
View File

@@ -3,6 +3,8 @@
#include <linux/uaccess.h>
#include <linux/kernel.h>
#include <asm/vsyscall.h>
#ifdef CONFIG_X86_64
bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size)
{
@@ -15,6 +17,14 @@ bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size)
if (vaddr < TASK_SIZE_MAX + PAGE_SIZE)
return false;
/*
* Reading from the vsyscall page may cause an unhandled fault in
* certain cases. Though it is at an address above TASK_SIZE_MAX, it is
* usually considered as a user space address.
*/
if (is_vsyscall_vaddr(vaddr))
return false;
/*
* Allow everything during early boot before 'x86_virt_bits'
* is initialized. Needed for instruction decoding in early

10
arch/x86/mm/mem_encrypt_identity.c
View File

@@ -507,7 +507,6 @@ void __init sme_enable(struct boot_params *bp)
const char *cmdline_ptr, *cmdline_arg, *cmdline_on, *cmdline_off;
unsigned int eax, ebx, ecx, edx;
unsigned long feature_mask;
bool active_by_default;
unsigned long me_mask;
char buffer[16];
bool snp;
@@ -593,22 +592,19 @@ void __init sme_enable(struct boot_params *bp)
: "p" (sme_cmdline_off));
if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT))
active_by_default = true;
else
active_by_default = false;
sme_me_mask = me_mask;
cmdline_ptr = (const char *)((u64)bp->hdr.cmd_line_ptr |
((u64)bp->ext_cmd_line_ptr << 32));
if (cmdline_find_option(cmdline_ptr, cmdline_arg, buffer, sizeof(buffer)) < 0)
return;
goto out;
if (!strncmp(buffer, cmdline_on, sizeof(buffer)))
sme_me_mask = me_mask;
else if (!strncmp(buffer, cmdline_off, sizeof(buffer)))
sme_me_mask = 0;
else
sme_me_mask = active_by_default ? me_mask : 0;
out:
if (sme_me_mask) {
physical_mask &= ~sme_me_mask;

8
arch/x86/tools/relocs.c
View File

@@ -653,6 +653,14 @@ static void print_absolute_relocs(void)
if (!(sec_applies->shdr.sh_flags & SHF_ALLOC)) {
continue;
}
/*
* Do not perform relocations in .notes section; any
* values there are meant for pre-boot consumption (e.g.
* startup_xen).
*/
if (sec_applies->shdr.sh_type == SHT_NOTE) {
continue;
}
sh_symtab = sec_symtab->symtab;
sym_strtab = sec_symtab->link->strtab;
for (j = 0; j < sec->shdr.sh_size/sizeof(Elf_Rel); j++) {

12
arch/x86/xen/smp.c
View File

@@ -65,6 +65,8 @@ int xen_smp_intr_init(unsigned int cpu)
char *resched_name, *callfunc_name, *debug_name;
resched_name = kasprintf(GFP_KERNEL, "resched%d", cpu);
if (!resched_name)
goto fail_mem;
per_cpu(xen_resched_irq, cpu).name = resched_name;
rc = bind_ipi_to_irqhandler(XEN_RESCHEDULE_VECTOR,
cpu,
@@ -77,6 +79,8 @@ int xen_smp_intr_init(unsigned int cpu)
per_cpu(xen_resched_irq, cpu).irq = rc;
callfunc_name = kasprintf(GFP_KERNEL, "callfunc%d", cpu);
if (!callfunc_name)
goto fail_mem;
per_cpu(xen_callfunc_irq, cpu).name = callfunc_name;
rc = bind_ipi_to_irqhandler(XEN_CALL_FUNCTION_VECTOR,
cpu,
@@ -90,6 +94,9 @@ int xen_smp_intr_init(unsigned int cpu)
if (!xen_fifo_events) {
debug_name = kasprintf(GFP_KERNEL, "debug%d", cpu);
if (!debug_name)
goto fail_mem;
per_cpu(xen_debug_irq, cpu).name = debug_name;
rc = bind_virq_to_irqhandler(VIRQ_DEBUG, cpu,
xen_debug_interrupt,
@@ -101,6 +108,9 @@ int xen_smp_intr_init(unsigned int cpu)
}
callfunc_name = kasprintf(GFP_KERNEL, "callfuncsingle%d", cpu);
if (!callfunc_name)
goto fail_mem;
per_cpu(xen_callfuncsingle_irq, cpu).name = callfunc_name;
rc = bind_ipi_to_irqhandler(XEN_CALL_FUNCTION_SINGLE_VECTOR,
cpu,
@@ -114,6 +124,8 @@ int xen_smp_intr_init(unsigned int cpu)
return 0;
fail_mem:
rc = -ENOMEM;
fail:
xen_smp_intr_free(cpu);
return rc;

1
block/opal_proto.h
View File

@@ -71,6 +71,7 @@ enum opal_response_token {
#define SHORT_ATOM_BYTE 0xBF
#define MEDIUM_ATOM_BYTE 0xDF
#define LONG_ATOM_BYTE 0xE3
#define EMPTY_ATOM_BYTE 0xFF
#define OPAL_INVAL_PARAM 12
#define OPAL_MANUFACTURED_INACTIVE 0x08

6
block/sed-opal.c
View File

@@ -935,16 +935,20 @@ static int response_parse(const u8 *buf, size_t length,
token_length = response_parse_medium(iter, pos);
else if (pos[0] <= LONG_ATOM_BYTE) /* long atom */
token_length = response_parse_long(iter, pos);
else if (pos[0] == EMPTY_ATOM_BYTE) /* empty atom */
token_length = 1;
else /* TOKEN */
token_length = response_parse_token(iter, pos);
if (token_length < 0)
return token_length;
if (pos[0] != EMPTY_ATOM_BYTE)
num_entries++;
pos += token_length;
total -= token_length;
iter++;
num_entries++;
}
resp->num = num_entries;

5
crypto/Kconfig
View File

@@ -1285,10 +1285,11 @@ config CRYPTO_JITTERENTROPY
A non-physical non-deterministic ("true") RNG (e.g., an entropy source
compliant with NIST SP800-90B) intended to provide a seed to a
deterministic RNG (e.g. per NIST SP800-90C).
deterministic RNG (e.g., per NIST SP800-90C).
This RNG does not perform any cryptographic whitening of the generated
random numbers.
See https://www.chronox.de/jent.html
See https://www.chronox.de/jent/
config CRYPTO_KDF800108_CTR
tristate

2
drivers/acpi/processor_idle.c
View File

@@ -1431,6 +1431,8 @@ int acpi_processor_power_exit(struct acpi_processor *pr)
acpi_processor_registered--;
if (acpi_processor_registered == 0)
cpuidle_unregister_driver(&acpi_idle_driver);
kfree(dev);
}
pr->flags.power_setup_done = 0;

33
drivers/acpi/resource.c
View File

@@ -543,6 +543,39 @@ static const struct dmi_system_id lg_laptop[] = {
DMI_MATCH(DMI_BOARD_NAME, "17U70P"),
},
},
{
/* Infinity E15-5A165-BM */
.matches = {
DMI_MATCH(DMI_BOARD_NAME, "GM5RG1E0009COM"),
},
},
{
/* Infinity E15-5A305-1M */
.matches = {
DMI_MATCH(DMI_BOARD_NAME, "GM5RGEE0016COM"),
},
},
{
/* Lunnen Ground 15 / AMD Ryzen 5 5500U */
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Lunnen"),
DMI_MATCH(DMI_BOARD_NAME, "LLL5DAW"),
},
},
{
/* Lunnen Ground 16 / AMD Ryzen 7 5800U */
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Lunnen"),
DMI_MATCH(DMI_BOARD_NAME, "LL6FA"),
},
},
{
/* MAIBENBEN X577 */
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "MAIBENBEN"),
DMI_MATCH(DMI_BOARD_NAME, "X577"),
},
},
{ }
};

8
drivers/acpi/scan.c
View File

@@ -315,18 +315,14 @@ static int acpi_scan_device_check(struct acpi_device *adev)
* again).
*/
if (adev->handler) {
dev_warn(&adev->dev, "Already enumerated\n");
return -EALREADY;
dev_dbg(&adev->dev, "Already enumerated\n");
return 0;
}
error = acpi_bus_scan(adev->handle);
if (error) {
dev_warn(&adev->dev, "Namespace scan failure\n");
return error;
}
if (!adev->handler) {
dev_warn(&adev->dev, "Enumeration failure\n");
error = -ENODEV;
}
} else {
error = acpi_scan_device_not_present(adev);
}

12
drivers/block/aoe/aoecmd.c
View File

@@ -419,13 +419,16 @@ aoecmd_cfg_pkts(ushort aoemajor, unsigned char aoeminor, struct sk_buff_head *qu
rcu_read_lock();
for_each_netdev_rcu(&init_net, ifp) {
dev_hold(ifp);
if (!is_aoe_netif(ifp))
goto cont;
if (!is_aoe_netif(ifp)) {
dev_put(ifp);
continue;
}
skb = new_skb(sizeof *h + sizeof *ch);
if (skb == NULL) {
printk(KERN_INFO "aoe: skb alloc failure\n");
goto cont;
dev_put(ifp);
continue;
}
skb_put(skb, sizeof *h + sizeof *ch);
skb->dev = ifp;
@@ -440,9 +443,6 @@ aoecmd_cfg_pkts(ushort aoemajor, unsigned char aoeminor, struct sk_buff_head *qu
h->major = cpu_to_be16(aoemajor);
h->minor = aoeminor;
h->cmd = AOECMD_CFG;
cont:
dev_put(ifp);
}
rcu_read_unlock();
}

1
drivers/block/aoe/aoenet.c
View File

@@ -64,6 +64,7 @@ tx(int id) __must_hold(&txlock)
pr_warn("aoe: packet could not be sent on %s. %s\n",
ifp ? ifp->name : "netif",
"consider increasing tx_queue_len");
dev_put(ifp);
spin_lock_irq(&txlock);
}
return 0;

6
drivers/block/nbd.c
View File

@@ -2408,6 +2408,12 @@ static int nbd_genl_status(struct sk_buff *skb, struct genl_info *info)
}
dev_list = nla_nest_start_noflag(reply, NBD_ATTR_DEVICE_LIST);
if (!dev_list) {
nlmsg_free(reply);
ret = -EMSGSIZE;
goto out;
}
if (index == -1) {
ret = idr_for_each(&nbd_index_idr, &status_cb, reply);
if (ret) {

6
drivers/bluetooth/hci_qca.c
View File

@@ -2254,7 +2254,7 @@ static int qca_serdev_probe(struct serdev_device *serdev)
qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable",
GPIOD_OUT_LOW);
if (IS_ERR_OR_NULL(qcadev->bt_en) &&
if (IS_ERR(qcadev->bt_en) &&
(data->soc_type == QCA_WCN6750 ||
data->soc_type == QCA_WCN6855)) {
dev_err(&serdev->dev, "failed to acquire BT_EN gpio\n");
@@ -2263,7 +2263,7 @@ static int qca_serdev_probe(struct serdev_device *serdev)
qcadev->sw_ctrl = devm_gpiod_get_optional(&serdev->dev, "swctrl",
GPIOD_IN);
if (IS_ERR_OR_NULL(qcadev->sw_ctrl) &&
if (IS_ERR(qcadev->sw_ctrl) &&
(data->soc_type == QCA_WCN6750 ||
data->soc_type == QCA_WCN6855 ||
data->soc_type == QCA_WCN7850))
@@ -2285,7 +2285,7 @@ static int qca_serdev_probe(struct serdev_device *serdev)
default:
qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable",
GPIOD_OUT_LOW);
if (IS_ERR_OR_NULL(qcadev->bt_en)) {
if (IS_ERR(qcadev->bt_en)) {
dev_warn(&serdev->dev, "failed to acquire enable gpio\n");
power_ctrl_enabled = false;
}

5
drivers/bus/Kconfig
View File

@@ -186,11 +186,12 @@ config SUNXI_RSB
config TEGRA_ACONNECT
tristate "Tegra ACONNECT Bus Driver"
depends on ARCH_TEGRA_210_SOC
depends on ARCH_TEGRA
depends on OF && PM
help
Driver for the Tegra ACONNECT bus which is used to interface with
the devices inside the Audio Processing Engine (APE) for Tegra210.
the devices inside the Audio Processing Engine (APE) for
Tegra210 and later.
config TEGRA_GMI
tristate "Tegra Generic Memory Interface bus driver"

3
drivers/clk/clk.c
View File

@@ -407,6 +407,9 @@ static struct clk_core *clk_core_get(struct clk_core *core, u8 p_index)
if (IS_ERR(hw))
return ERR_CAST(hw);
if (!hw)
return NULL;
return hw->core;
}

2
drivers/clk/hisilicon/clk-hi3519.c
View File

@@ -130,7 +130,7 @@ static void hi3519_clk_unregister(struct platform_device *pdev)
of_clk_del_provider(pdev->dev.of_node);
hisi_clk_unregister_gate(hi3519_gate_clks,
ARRAY_SIZE(hi3519_mux_clks),
ARRAY_SIZE(hi3519_gate_clks),
crg->clk_data);
hisi_clk_unregister_mux(hi3519_mux_clks,
ARRAY_SIZE(hi3519_mux_clks),

1
drivers/clk/hisilicon/clk-hi3559a.c
View File

@@ -491,7 +491,6 @@ static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
clk = clk_register(NULL, &p_clk->hw);
if (IS_ERR(clk)) {
devm_kfree(dev, p_clk);
dev_err(dev, "%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;

2
drivers/clk/meson/axg.c
View File

@@ -2144,7 +2144,9 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
&axg_vclk_input,
&axg_vclk2_input,
&axg_vclk_div,
&axg_vclk_div1,
&axg_vclk2_div,
&axg_vclk2_div1,
&axg_vclk_div2_en,
&axg_vclk_div4_en,
&axg_vclk_div6_en,

2
drivers/clk/qcom/dispcc-sdm845.c
View File

@@ -759,6 +759,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = {
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
.en_few_wait_val = 0x6,
.en_rest_wait_val = 0x5,
.pd = {
.name = "mdss_gdsc",
},

27
drivers/clk/qcom/reset.c
View File

@@ -22,8 +22,8 @@ static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id)
return 0;
}
static int
qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
static int qcom_reset_set_assert(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct qcom_reset_controller *rst;
const struct qcom_reset_map *map;
@@ -33,21 +33,22 @@ qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
map = &rst->reset_map[id];
mask = map->bitmask ? map->bitmask : BIT(map->bit);
return regmap_update_bits(rst->regmap, map->reg, mask, mask);
regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0);
/* Read back the register to ensure write completion, ignore the value */
regmap_read(rst->regmap, map->reg, &mask);
return 0;
}
static int
qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
static int qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
{
struct qcom_reset_controller *rst;
const struct qcom_reset_map *map;
u32 mask;
return qcom_reset_set_assert(rcdev, id, true);
}
rst = to_qcom_reset_controller(rcdev);
map = &rst->reset_map[id];
mask = map->bitmask ? map->bitmask : BIT(map->bit);
return regmap_update_bits(rst->regmap, map->reg, mask, 0);
static int qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
{
return qcom_reset_set_assert(rcdev, id, false);
}
const struct reset_control_ops qcom_reset_ops = {

2
drivers/clk/renesas/r8a779f0-cpg-mssr.c
View File

@@ -159,7 +159,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
DEF_MOD("cmt1", 911, R8A779F0_CLK_R),
DEF_MOD("cmt2", 912, R8A779F0_CLK_R),
DEF_MOD("cmt3", 913, R8A779F0_CLK_R),
DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M),
DEF_MOD("pfc0", 915, R8A779F0_CLK_CPEX),
DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M),
DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC),
};

18
drivers/clk/renesas/r8a779g0-cpg-mssr.c
View File

@@ -22,7 +22,7 @@
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A779G0_CLK_R,
LAST_DT_CORE_CLK = R8A779G0_CLK_CP,
/* External Input Clocks */
CLK_EXTAL,
@@ -139,6 +139,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
DEF_FIXED("svd2_vip", R8A779G0_CLK_SVD2_VIP, CLK_SV_VIP, 2, 1),
DEF_FIXED("cbfusa", R8A779G0_CLK_CBFUSA, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A779G0_CLK_CPEX, CLK_EXTAL, 2, 1),
DEF_FIXED("cp", R8A779G0_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("viobus", R8A779G0_CLK_VIOBUS, CLK_VIO, 1, 1),
DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
@@ -169,10 +170,17 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("i2c4", 522, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c5", 523, R8A779G0_CLK_S0D6_PER),
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
DEF_MOD("pfc0", 915, R8A779G0_CLK_CL16M),
DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M),
DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M),
DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M),
DEF_MOD("cmt0", 910, R8A779G0_CLK_R),
DEF_MOD("cmt1", 911, R8A779G0_CLK_R),
DEF_MOD("cmt2", 912, R8A779G0_CLK_R),
DEF_MOD("cmt3", 913, R8A779G0_CLK_R),
DEF_MOD("pfc0", 915, R8A779G0_CLK_CP),
DEF_MOD("pfc1", 916, R8A779G0_CLK_CP),
DEF_MOD("pfc2", 917, R8A779G0_CLK_CP),
DEF_MOD("pfc3", 918, R8A779G0_CLK_CP),
DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
};
/*

33
drivers/clk/samsung/clk-exynos850.c
View File

@@ -572,7 +572,7 @@ static const struct samsung_div_clock apm_div_clks[] __initconst = {
static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
GATE(CLK_GOUT_CLKCMU_CMGP_BUS, "gout_clkcmu_cmgp_bus", "dout_apm_bus",
CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, 0, 0),
CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_CLKCMU_CHUB_BUS, "gout_clkcmu_chub_bus",
"mout_clkcmu_chub_bus",
CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, 21, 0, 0),
@@ -936,19 +936,19 @@ static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = {
static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p,
CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1),
MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1),
MUX_F(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1, CLK_SET_RATE_PARENT, 0),
MUX_F(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus",
CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5),
DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5),
DIV_F(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5, CLK_SET_RATE_PARENT, 0),
DIV_F(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
@@ -963,12 +963,12 @@ static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
"gout_clkcmu_cmgp_bus",
CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0",
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0),
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk",
"gout_clkcmu_cmgp_bus",
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1",
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0),
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk",
"gout_clkcmu_cmgp_bus",
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
@@ -1409,8 +1409,9 @@ static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1),
MUX(CLK_MOUT_PERI_HSI2C_USER, "mout_peri_hsi2c_user",
mout_peri_hsi2c_user_p, PLL_CON0_MUX_CLKCMU_PERI_HSI2C_USER, 4, 1),
MUX(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user", mout_peri_spi_user_p,
PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1),
MUX_F(CLK_MOUT_PERI_SPI_USER, "mout_peri_spi_user",
mout_peri_spi_user_p, PLL_CON0_MUX_CLKCMU_PERI_SPI_USER, 4, 1,
CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_div_clock peri_div_clks[] __initconst = {
@@ -1420,8 +1421,8 @@ static const struct samsung_div_clock peri_div_clks[] __initconst = {
CLK_CON_DIV_DIV_CLK_PERI_HSI2C_1, 0, 5),
DIV(CLK_DOUT_PERI_HSI2C2, "dout_peri_hsi2c2", "gout_peri_hsi2c2",
CLK_CON_DIV_DIV_CLK_PERI_HSI2C_2, 0, 5),
DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user",
CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5),
DIV_F(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "mout_peri_spi_user",
CLK_CON_DIV_DIV_CLK_PERI_SPI_0, 0, 5, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
@@ -1463,7 +1464,7 @@ static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
"mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
GATE(CLK_GOUT_SPI0_IPCLK, "gout_spi0_ipclk", "dout_peri_spi0",
CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, 0, 0),
CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",

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