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arm64: zynqmp: Add L2 cache nodes

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Describe SoC L2 cache hierarchy.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/130e5a6acbee94809b63a61cde5450fbff88cc9c.1685964230.git.michal.simek@amd.com
This commit is contained in:
Radhey Shyam Pandey
2023-06-05 13:23:58 +02:00
committed by Michal Simek
parent 06c2afb862
commit 3011e0c813
1 changed files with 10 additions and 0 deletions
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10
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
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@@ -33,6 +33,7 @@
operating-points-v2 = <&cpu_opp_table>;
reg = <0x0>;
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2>;
};
cpu1: cpu@1 {
@@ -42,6 +43,7 @@
reg = <0x1>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2>;
};
cpu2: cpu@2 {
@@ -51,6 +53,7 @@
reg = <0x2>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2>;
};
cpu3: cpu@3 {
@@ -60,6 +63,13 @@
reg = <0x3>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
idle-states {