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drm/amd/powerplay: drop unnecessary uclk hard min setting

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We don't need to set uclk hard min here because this will
be set with other clocks on power state change.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan
2018-06-20 12:28:10 +08:00
committed by Alex Deucher
parent ac32b06ace
commit 3022256180
1 changed files with 0 additions and 10 deletions
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10
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
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@@ -1399,7 +1399,6 @@ static int vega12_notify_smc_display_config_after_ps_adjustment(
(struct vega12_hwmgr *)(hwmgr->backend);
struct PP_Clocks min_clocks = {0};
struct pp_display_clock_request clock_req;
uint32_t clk_request;
if ((hwmgr->display_config->num_display > 1) &&
!hwmgr->display_config->multi_monitor_in_sync)
@@ -1427,15 +1426,6 @@ static int vega12_notify_smc_display_config_after_ps_adjustment(
}
}
if (data->smu_features[GNLD_DPM_UCLK].enabled) {
clk_request = (PPCLK_UCLK << 16) | (min_clocks.memoryClock) / 100;
PP_ASSERT_WITH_CODE(
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetHardMinByFreq, clk_request) == 0,
"[PhwVega12_NotifySMCDisplayConfigAfterPowerStateAdjustment] Attempt to set UCLK HardMin Failed!",
return -1);
data->dpm_table.mem_table.dpm_state.hard_min_level = min_clocks.memoryClock;
}
return 0;
}