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Merge commit '1d795ddee4f73b2739410f99c22280b00f452187'
* commit '1d795ddee4f73b2739410f99c22280b00f452187': soc: rockchip: cpuinfo: optimize error log rtc: rockchip: fix the rtc suspend crash soc: rockchip: fiq debugger: check "target_cpu" before switch cpu clk/rockchip/regmap: rate should not be zero mmc: dw_mmc: Fix DM 4GB TF card write data errors in RV1106 arm64: rk3308_linux_defconfig: enable Rockchip RPMsg media: i2c: imx577: fix exposure control range according to datasheet arm64: configs: rockchip_linux: change RPMSG config to RPMSG_MBOX Change-Id: I77072f12b7734da6c0212a715633fee3ee574f65
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@@ -257,6 +257,8 @@ CONFIG_COMMON_CLK_RK808=y
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# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
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# CONFIG_IOMMU_SUPPORT is not set
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# CONFIG_CPU_PX30 is not set
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CONFIG_RPMSG_ROCKCHIP_SOFTIRQ=y
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CONFIG_RPMSG_VIRTIO=y
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CONFIG_CPU_RK3308=y
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# CONFIG_CPU_RK3328 is not set
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# CONFIG_CPU_RK3368 is not set
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@@ -501,7 +501,7 @@ CONFIG_MAILBOX=y
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CONFIG_ROCKCHIP_MBOX=y
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CONFIG_ROCKCHIP_IOMMU=y
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CONFIG_ARM_SMMU_V3=y
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CONFIG_RPMSG_ROCKCHIP=y
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CONFIG_RPMSG_ROCKCHIP_MBOX=y
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CONFIG_RPMSG_VIRTIO=y
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CONFIG_CPU_PX30=y
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CONFIG_CPU_RK1808=y
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@@ -47,6 +47,16 @@ static void clk_regmap_fractional_divider_approximation(struct clk_hw *hw,
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struct clk_hw *p_parent;
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unsigned long scale;
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if (!rate) {
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*m = 0;
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*n = 1;
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dev_dbg(fd->dev, "%s rate:(%ld) maybe invalid frequency setting!\n",
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clk_hw_get_name(hw), rate);
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return;
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}
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p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
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if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
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p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
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@@ -62,7 +62,7 @@
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#define IMX577_REG_EXPOSURE_H 0x0202
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#define IMX577_REG_EXPOSURE_L 0x0203
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#define IMX577_EXPOSURE_MIN 4
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#define IMX577_EXPOSURE_MIN 8
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#define IMX577_EXPOSURE_STEP 1
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#define IMX577_VTS_MAX 0xffff
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@@ -2022,7 +2022,7 @@ static int imx577_set_ctrl(struct v4l2_ctrl *ctrl)
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case V4L2_CID_VBLANK:
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if (imx577->cur_mode->hdr_mode == NO_HDR) {
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/* Update max exposure while meeting expected vblanking */
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max = imx577->cur_mode->height + ctrl->val - 4;
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max = imx577->cur_mode->height + ctrl->val - 22;
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__v4l2_ctrl_modify_range(imx577->exposure,
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imx577->exposure->minimum, max,
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imx577->exposure->step,
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@@ -2186,7 +2186,7 @@ static int imx577_initialize_controls(struct imx577 *imx577)
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IMX577_VTS_MAX - mode->height,
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1, vblank_def);
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imx577->cur_vts = mode->vts_def;
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exposure_max = mode->vts_def - 4;
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exposure_max = mode->vts_def - 22;
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imx577->exposure = v4l2_ctrl_new_std(handler, &imx577_ctrl_ops,
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V4L2_CID_EXPOSURE, IMX577_EXPOSURE_MIN,
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exposure_max, IMX577_EXPOSURE_STEP,
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@@ -2336,6 +2336,7 @@ static void dw_mci_tasklet_func(struct tasklet_struct *t)
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((fifo_count >> 17) & 0x7FF) <= RV1106_RAMDON_DATA_SIZE / 4,
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0, 5000 * USEC_PER_MSEC))
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data->error = -ETIMEDOUT;
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udelay(1);
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dw_mci_reset(host);
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}
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send_stop_abort(host, data);
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@@ -555,6 +555,31 @@ static void rockchip_rtc_compensation_delay_work(struct work_struct *work)
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return;
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}
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static bool rockchip_rtc_is_trimed(struct rockchip_rtc *rtc)
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{
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int ret, comp_done;
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ret = regmap_read(rtc->regmap, RTC_CTRL, &comp_done);
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if (ret) {
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pr_err("%s: Failed to read RTC_CTRL: %d\n", __func__, ret);
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return false;
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}
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return (comp_done & CLK32K_COMP_EN) == CLK32K_COMP_EN;
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}
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static void rockchip_rtc_trim_start(struct rockchip_rtc *rtc)
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{
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if (!rockchip_rtc_is_trimed(rtc))
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queue_delayed_work(system_long_wq, &rtc->trim_work,
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msecs_to_jiffies(5000));
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}
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static void __maybe_unused rockchip_rtc_trim_close(struct rockchip_rtc *rtc)
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{
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if (!rockchip_rtc_is_trimed(rtc))
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cancel_delayed_work_sync(&rtc->trim_work);
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}
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/* Enable the alarm if it should be enabled (in case it was disabled to
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* prevent use as a wake source).
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*/
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@@ -568,6 +593,8 @@ static int rockchip_rtc_suspend(struct device *dev)
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if (device_may_wakeup(dev))
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enable_irq_wake(rtc->irq);
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rockchip_rtc_trim_close(rtc);
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if (rtc->grf) {
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switch (rtc->mode) {
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case ROCKCHIP_RV1106_RTC:
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@@ -610,6 +637,7 @@ static int rockchip_rtc_resume(struct device *dev)
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dev_err(dev, "Cannot enable clock.\n");
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return ret;
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}
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rockchip_rtc_trim_start(rtc);
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return 0;
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}
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@@ -761,7 +789,7 @@ static int rockchip_rtc_probe(struct platform_device *pdev)
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rtc->irq);
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INIT_DELAYED_WORK(&rtc->trim_work, rockchip_rtc_compensation_delay_work);
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queue_delayed_work(system_long_wq, &rtc->trim_work, 3000);
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rockchip_rtc_trim_start(rtc);
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return devm_rtc_register_device(rtc->rtc);
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}
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@@ -763,6 +763,11 @@ static int fiq_debugger_cpu_offine_migrate_fiq(unsigned int cpu)
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if ((sip_fiq_debugger_is_enabled()) &&
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(sip_fiq_debugger_get_target_cpu() == cpu)) {
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target_cpu = cpumask_any_but(cpu_online_mask, cpu);
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if (target_cpu >= nr_cpu_ids) {
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pr_err("%s: migrate fiq fail!\n", __func__);
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return -EBUSY;
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}
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sip_fiq_debugger_switch_cpu(target_cpu);
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}
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@@ -57,12 +57,9 @@ static int rockchip_cpuinfo_probe(struct platform_device *pdev)
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}
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cell = nvmem_cell_get(dev, "id");
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if (IS_ERR(cell)) {
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dev_err(dev, "failed to get id cell: %ld\n", PTR_ERR(cell));
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if (PTR_ERR(cell) == -EPROBE_DEFER)
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return PTR_ERR(cell);
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return PTR_ERR(cell);
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}
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if (IS_ERR(cell))
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return dev_err_probe(dev, PTR_ERR(cell), "failed to get id cell\n");
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efuse_buf = nvmem_cell_read(cell, &len);
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nvmem_cell_put(cell);
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if (IS_ERR(efuse_buf))
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