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ARM: dts: rockchip: rk312x: dtsi for video codec

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Change-Id: I911f413d05a7ca10eeb7abbb808cc3165b6a56bc
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
This commit is contained in:
Ding Wei
2019-11-02 16:58:52 +08:00
committed by Tao Huang
parent d30a7f302e
commit 316a8ec31a
3 changed files with 71 additions and 37 deletions
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14
arch/arm/boot/dts/rk3126-bnd-d708.dtsi
View File

@@ -531,6 +531,10 @@
status = "okay";
};
&mpp_srv {
status = "okay";
};
&nandc {
status = "okay";
};
@@ -653,6 +657,14 @@
status = "okay";
};
&vpu {
&vdpu {
status = "okay";
};
&vepu {
status = "okay";
};
&vpu_mmu {
status = "okay";
};

14
arch/arm/boot/dts/rk3126-bnd-m88-emmc.dts
View File

@@ -471,6 +471,10 @@
status = "okay";
};
&mpp_srv {
status = "okay";
};
&nandc {
status = "disabled";
};
@@ -610,6 +614,14 @@
status = "okay";
};
&vpu {
&vdpu {
status = "okay";
};
&vepu {
status = "okay";
};
&vpu_mmu {
status = "okay";
};

80
arch/arm/boot/dts/rk312x.dtsi
View File

@@ -465,15 +465,29 @@
};
};
hevc: hevc_service@10104000 {
compatible = "rockchip,sub";
mpp_srv: mpp-srv {
compatible = "rockchip,mpp-service";
rockchip,taskqueue-count = <1>;
vdpu1,grf = <&grf 0x0144 0x04000400>;
vepu1,grf = <&grf 0x0144 0x04000400>;
status = "disabled";
};
hevc: hevc@10104000 {
compatible = "rockchip,hevc-decoder";
reg = <0x10104000 0x400>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
power-domains = <&power RK3128_PD_VIDEO>;
dev_mode = <1>;
name = "hevc_service";
clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
<&cru SCLK_HEVC_CORE>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
resets = <&cru SRST_VCODEC_H>, <&cru SRST_VCODEC_A>,
<&cru SRST_HEVC_CORE>;
reset-names = "video_h", "video_a", "video_core";
iommus = <&hevc_mmu>;
power-domains = <&power RK3128_PD_VIDEO>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <0>;
status = "disabled";
};
@@ -482,28 +496,42 @@
reg = <0x10104440 0x40>, <0x10104480 0x40>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
clock-names = "aclk", "iface";
clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>;
power-domains = <&power RK3128_PD_VIDEO>;
#iommu-cells = <0>;
status = "disabled";
};
vpu: vpu_service@10106000 {
compatible = "rockchip,sub";
reg = <0x10106000 0x800>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_enc", "irq_dec";
vepu: vepu@0x10106000 {
compatible = "rockchip,vpu-encoder-v1";
reg = <0x10106000 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_enc";
clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>;
clock-names = "aclk_vcodec", "hclk_vcodec";
resets = <&cru SRST_VCODEC_H>, <&cru SRST_VCODEC_A>;
reset-names = "video_h", "video_a";
power-domains = <&power RK3128_PD_VIDEO>;
name = "vpu_service";
dev_mode = <0>;
iommus = <&vpu_mmu>;
/* 0 means ion, 1 means drm */
allocator = <1>;
power-domains = <&power RK3128_PD_VIDEO>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <0>;
status = "disabled";
};
vdpu: vdpu@10106400 {
compatible = "rockchip,vpu-decoder-v1";
reg = <0x10106400 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>;
clock-names = "aclk_vcodec", "hclk_vcodec";
resets = <&cru SRST_VCODEC_H>, <&cru SRST_VCODEC_A>;
reset-names = "video_h", "video_a";
iommus = <&vpu_mmu>;
power-domains = <&power RK3128_PD_VIDEO>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <0>;
status = "disabled";
};
@@ -519,24 +547,6 @@
status = "disabled";
};
vpu_combo: vpu_combo {
compatible = "rockchip,vpu_combo";
subcnt = <2>;
rockchip,sub = <&vpu>, <&hevc>;
rockchip,grf = <&grf>;
clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
<&cru SCLK_HEVC_CORE>;
clock-names = "aclk_vcodec", "hclk_vcodec",
"clk_core";
resets = <&cru SRST_VCODEC_H>, <&cru SRST_VCODEC_A>,
<&cru SRST_HEVC_CORE>;
reset-names = "video_h", "video_a", "video";
mode_bit = <15>;
mode_ctrl = <0x144>;
name = "vpu_combo";
status = "disabled";
};
iep: iep@10108000 {
compatible = "rockchip,iep";
iommu_enabled = <1>;