mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-07 11:26:02 +09:00
rockchip: add reset-rockchip driver to support Generic Reset Controller framework
This commit is contained in:
dkl
@@ -239,6 +239,13 @@
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};
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};
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reset: reset@ff7601b8{
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compatible = "rockchip,reset";
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reg = <0xff7601b8 0x30>;
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rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
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#reset-cells = <1>;
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};
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nandc0: nandc@0xff400000 {
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compatible = "rockchip,rk-nandc";
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reg = <0xff400000 0x4000>;
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@@ -514,6 +514,7 @@ CONFIG_IIO=y
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CONFIG_ROCKCHIP_ADC=y
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CONFIG_PWM=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_RESET_CONTROLLER=y
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CONFIG_RK_HEADSET=y
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CONFIG_EXT2_FS=y
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CONFIG_EXT2_FS_XATTR=y
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@@ -1 +1,3 @@
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obj-$(CONFIG_RESET_CONTROLLER) += core.o
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obj-$(CONFIG_ARCH_ROCKCHIP) += reset-rockchip.o
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168
drivers/reset/reset-rockchip.c
Normal file
168
drivers/reset/reset-rockchip.c
Normal file
@@ -0,0 +1,168 @@
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/*
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* Copyright (c) 2014 ROCKCHIP, Inc.
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* Author: Dai Kelin <dkl@rock-chips.com>
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* Based on codes from Heiko Stuebner <heiko@sntech.de>.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/reset-controller.h>
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#include <linux/spinlock.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <dt-bindings/clock/rockchip.h>
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struct rockchip_reset {
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struct reset_controller_dev rcdev;
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void __iomem *reg_base;
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int num_regs;
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int num_per_reg;
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u8 flags;
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spinlock_t lock;
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};
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static int rockchip_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct rockchip_reset *reset = container_of(rcdev,
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struct rockchip_reset,
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rcdev);
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int bank = id / reset->num_per_reg;
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int offset = id % reset->num_per_reg;
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if (reset->flags & ROCKCHIP_RESET_HIWORD_MASK) {
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writel(BIT(offset) | (BIT(offset) << 16),
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reset->reg_base + (bank * 4));
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} else {
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&reset->lock, flags);
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reg = readl(reset->reg_base + (bank * 4));
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writel(reg | BIT(offset), reset->reg_base + (bank * 4));
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spin_unlock_irqrestore(&reset->lock, flags);
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}
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return 0;
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}
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static int rockchip_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct rockchip_reset *reset = container_of(rcdev,
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struct rockchip_reset,
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rcdev);
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int bank = id / reset->num_per_reg;
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int offset = id % reset->num_per_reg;
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if (reset->flags & ROCKCHIP_RESET_HIWORD_MASK) {
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writel((BIT(offset) << 16), reset->reg_base + (bank * 4));
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} else {
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&reset->lock, flags);
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reg = readl(reset->reg_base + (bank * 4));
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writel(reg & ~BIT(offset), reset->reg_base + (bank * 4));
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spin_unlock_irqrestore(&reset->lock, flags);
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}
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return 0;
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}
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static struct reset_control_ops rockchip_reset_ops = {
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.assert = rockchip_reset_assert,
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.deassert = rockchip_reset_deassert,
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};
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static int rockchip_register_reset(struct device_node *np,
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unsigned int num_regs,
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void __iomem *base, u8 flags)
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{
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struct rockchip_reset *reset;
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int ret;
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reset = kzalloc(sizeof(*reset), GFP_KERNEL);
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if (!reset)
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return -ENOMEM;
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reset->flags = flags;
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reset->reg_base = base;
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reset->num_regs = num_regs;
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reset->num_per_reg = (flags & ROCKCHIP_RESET_HIWORD_MASK) ? 16 : 32;
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spin_lock_init(&reset->lock);
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reset->rcdev.owner = THIS_MODULE;
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reset->rcdev.nr_resets = num_regs * reset->num_per_reg;
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reset->rcdev.ops = &rockchip_reset_ops;
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reset->rcdev.of_node = np;
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ret = reset_controller_register(&reset->rcdev);
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if (ret) {
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pr_err("%s: could not register reset controller, %d\n",
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__func__, ret);
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kfree(reset);
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return ret;
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}
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return 0;
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};
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static int rockchip_reset_probe(struct platform_device *pdev)
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{
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struct resource *res;
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void __iomem *base;
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resource_size_t size;
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u32 flag = 0;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base)) {
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pr_err("%s: ioremap err\n", __func__);
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return PTR_ERR(base);
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}
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size = resource_size(res);
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if (size%4) {
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pr_err("%s: wrong size value\n", __func__);
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return -EINVAL;
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}
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of_property_read_u32(pdev->dev.of_node, "rockchip,reset-flag", &flag);
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return rockchip_register_reset(pdev->dev.of_node, size/4, base, flag);
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}
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static const struct of_device_id rockchip_reset_dt_ids[] = {
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{ .compatible = "rockchip,reset", },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, rockchip_reset_dt_ids);
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static struct platform_driver rockchip_reset_driver = {
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.probe = rockchip_reset_probe,
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.driver = {
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.name = "rockchip-reset",
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.owner = THIS_MODULE,
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.of_match_table = rockchip_reset_dt_ids,
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},
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};
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module_platform_driver(rockchip_reset_driver);
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@@ -11,4 +11,210 @@
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#define RK3288_NPLL_ID 4
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#define RK3288_END_PLL_ID 5
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/* reset id */
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#define RK3288_SOFT_RST_CORE0 0
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#define RK3288_SOFT_RST_CORE1 1
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#define RK3288_SOFT_RST_CORE2 2
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#define RK3288_SOFT_RST_CORE3 3
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#define RK3288_SOFT_RST_CORE0_PO 4
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#define RK3288_SOFT_RST_CORE1_PO 5
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#define RK3288_SOFT_RST_CORE2_PO 6
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#define RK3288_SOFT_RST_CORE3_PO 7
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#define RK3288_SOFT_RST_PD_CORE_STR_SYS_A 8
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#define RK3288_SOFT_RST_PD_BUS_STR_SYS_A 9
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#define RK3288_SOFT_RST_L2C 10
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#define RK3288_SOFT_RST_TOPDBG 11
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#define RK3288_SOFT_RST_CORE0_DBG 12
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#define RK3288_SOFT_RST_CORE1_DBG 13
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#define RK3288_SOFT_RST_CORE2_DBG 14
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#define RK3288_SOFT_RST_CORE3_DBG 15
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#define RK3288_SOFT_RST_PD_BUS_AHB_ARBITOR 16
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#define RK3288_SOFT_RST_EFUSE_256BIT_P 17
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#define RK3288_SOFT_RST_DMA1 18
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#define RK3288_SOFT_RST_INTMEM 19
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#define RK3288_SOFT_RST_ROM 20
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#define RK3288_SOFT_RST_SPDIF_8CH 21
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#define RK3288_SOFT_RST_TIMER_P 22
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#define RK3288_SOFT_RST_I2S 23
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#define RK3288_SOFT_RST_SPDIF 24
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#define RK3288_SOFT_RST_TIMER0 25
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#define RK3288_SOFT_RST_TIMER1 26
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#define RK3288_SOFT_RST_TIMER2 27
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#define RK3288_SOFT_RST_TIMER3 28
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#define RK3288_SOFT_RST_TIMER4 29
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#define RK3288_SOFT_RST_TIMER5 30
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#define RK3288_SOFT_RST_EFUSE_P 31
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#define RK3288_SOFT_RST_GPIO0 32
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#define RK3288_SOFT_RST_GPIO1 33
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#define RK3288_SOFT_RST_GPIO2 34
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#define RK3288_SOFT_RST_GPIO3 35
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#define RK3288_SOFT_RST_GPIO4 36
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#define RK3288_SOFT_RST_GPIO5 37
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#define RK3288_SOFT_RST_GPIO6 38
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#define RK3288_SOFT_RST_GPIO7 39
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#define RK3288_SOFT_RST_GPIO8 40
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#define RK3288_SOFT_RST_2RES9 41
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#define RK3288_SOFT_RST_I2C0 42
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#define RK3288_SOFT_RST_I2C1 43
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#define RK3288_SOFT_RST_I2C2 44
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#define RK3288_SOFT_RST_I2C3 45
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#define RK3288_SOFT_RST_I2C4 46
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#define RK3288_SOFT_RST_I2C5 47
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#define RK3288_SOFT_RST_DW_PWM 48
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#define RK3288_SOFT_RST_MMC_PERI 49
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#define RK3288_SOFT_RST_PERIPH_MMU 50
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#define RK3288_SOFT_RST_DAP 51
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#define RK3288_SOFT_RST_DAP_SYS 52
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#define RK3288_SOFT_RST_TPIU_AT 53
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#define RK3288_SOFT_RST_PMU_P 54
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#define RK3288_SOFT_RST_GRF 55
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#define RK3288_SOFT_RST_PMU 56
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#define RK3288_SOFT_RST_PERIPHSYS_A 57
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#define RK3288_SOFT_RST_PERIPHSYS_H 58
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#define RK3288_SOFT_RST_PERIPHSYS_P 59
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#define RK3288_SOFT_RST_PERIPH_NIU 60
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#define RK3288_SOFT_RST_PD_PERI_AHB_ARBITOR 61
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#define RK3288_SOFT_RST_EMEM_PERI 62
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#define RK3288_SOFT_RST_USB_PERI 63
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#define RK3288_SOFT_RST_DMA2 64
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#define RK3288_SOFT_RST_4RES1 65
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#define RK3288_SOFT_RST_MAC 66
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#define RK3288_SOFT_RST_GPS 67
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#define RK3288_SOFT_RST_4RES4 68
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#define RK3288_SOFT_RST_RK_PWM 69
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#define RK3288_SOFT_RST_4RES6 70
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#define RK3288_SOFT_RST_CCP 71
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#define RK3288_SOFT_RST_USB_HOST0 72
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#define RK3288_SOFT_RST_HSIC 73
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#define RK3288_SOFT_RST_HSIC_AUX 74
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#define RK3288_SOFT_RST_HSICPHY 75
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#define RK3288_SOFT_RST_HSADC 76
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#define RK3288_SOFT_RST_NANDC0 77
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#define RK3288_SOFT_RST_NANDC1 78
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#define RK3288_SOFT_RST_4RES15 79
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#define RK3288_SOFT_RST_TZPC 80
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#define RK3288_SOFT_RST_5RES1 81
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#define RK3288_SOFT_RST_5RES2 82
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#define RK3288_SOFT_RST_SPI0 83
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#define RK3288_SOFT_RST_SPI1 84
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#define RK3288_SOFT_RST_SPI2 85
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#define RK3288_SOFT_RST_5RES6 86
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#define RK3288_SOFT_RST_SARADC 87
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#define RK3288_SOFT_RST_PD_ALIVE_NIU_P 88
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#define RK3288_SOFT_RST_PD_PMU_INTMEM_P 89
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#define RK3288_SOFT_RST_PD_PMU_NIU_P 90
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#define RK3288_SOFT_RST_SECURITY_GRF_P 91
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#define RK3288_SOFT_RST_5RES12 92
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#define RK3288_SOFT_RST_5RES13 93
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#define RK3288_SOFT_RST_5RES14 94
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#define RK3288_SOFT_RST_5RES15 95
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#define RK3288_SOFT_RST_VIO_ARBI_H 96
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#define RK3288_SOFT_RST_RGA_NIU_A 97
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#define RK3288_SOFT_RST_VIO0_NIU_A 98
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#define RK3288_SOFT_RST_VIO_NIU_H 99
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#define RK3288_SOFT_RST_LCDC0_A 100
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#define RK3288_SOFT_RST_LCDC0_H 101
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#define RK3288_SOFT_RST_LCDC0_D 102
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#define RK3288_SOFT_RST_VIO1_NIU_A 103
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#define RK3288_SOFT_RST_VIP 104
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#define RK3288_SOFT_RST_RGA_CORE 105
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#define RK3288_SOFT_RST_IEP_A 106
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#define RK3288_SOFT_RST_IEP_H 107
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#define RK3288_SOFT_RST_RGA_A 108
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#define RK3288_SOFT_RST_RGA_H 109
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#define RK3288_SOFT_RST_ISP 110
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#define RK3288_SOFT_RST_EDP 111
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#define RK3288_SOFT_RST_VCODEC_A 112
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#define RK3288_SOFT_RST_VCODEC_H 113
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#define RK3288_SOFT_RST_VIO_H2P_H 114
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#define RK3288_SOFT_RST_MIPIDSI0_P 115
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#define RK3288_SOFT_RST_MIPIDSI1_P 116
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#define RK3288_SOFT_RST_MIPICSI_P 117
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#define RK3288_SOFT_RST_LVDS_PHY_P 118
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#define RK3288_SOFT_RST_LVDS_CON 119
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#define RK3288_SOFT_RST_GPU 120
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#define RK3288_SOFT_RST_HDMI 121
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#define RK3288_SOFT_RST_7RES10 122
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#define RK3288_SOFT_RST_7RES11 123
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#define RK3288_SOFT_RST_CORE_PVTM 124
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#define RK3288_SOFT_RST_GPU_PVTM 125
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#define RK3288_SOFT_RST_7RES14 126
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#define RK3288_SOFT_RST_7RES15 127
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#define RK3288_SOFT_RST_MMC0 128
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#define RK3288_SOFT_RST_SDIO0 129
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#define RK3288_SOFT_RST_SDIO1 130
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#define RK3288_SOFT_RST_EMMC 131
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#define RK3288_SOFT_RST_USBOTG_H 132
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#define RK3288_SOFT_RST_USBOTGPHY 133
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#define RK3288_SOFT_RST_USBOTGC 134
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#define RK3288_SOFT_RST_USBHOST0_H 135
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#define RK3288_SOFT_RST_USBHOST0PHY 136
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#define RK3288_SOFT_RST_USBHOST0C 137
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#define RK3288_SOFT_RST_USBHOST1_H 138
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#define RK3288_SOFT_RST_USBHOST1PHY 139
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#define RK3288_SOFT_RST_USBHOST1C 140
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||||
#define RK3288_SOFT_RST_USB_ADP 141
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#define RK3288_SOFT_RST_ACC_EFUSE 142
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#define RK3288_SOFT_RST_8RES15 143
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#define RK3288_SOFT_RST_CORESIGHT 144
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#define RK3288_SOFT_RST_PD_CORE_AHB_NOC 145
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#define RK3288_SOFT_RST_PD_CORE_APB_NOC 146
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#define RK3288_SOFT_RST_PD_CORE_MP_AXI 147
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#define RK3288_SOFT_RST_GIC 148
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#define RK3288_SOFT_RST_LCDCPWM0 149
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#define RK3288_SOFT_RST_LCDCPWM1 150
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#define RK3288_SOFT_RST_VIO0_H2P_BRG 151
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||||
#define RK3288_SOFT_RST_VIO1_H2P_BRG 152
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#define RK3288_SOFT_RST_RGA_H2P_BRG 153
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#define RK3288_SOFT_RST_HEVC 154
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#define RK3288_SOFT_RST_9RES11 155
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#define RK3288_SOFT_RST_9RES12 156
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||||
#define RK3288_SOFT_RST_9RES13 157
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||||
#define RK3288_SOFT_RST_9RES14 158
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||||
#define RK3288_SOFT_RST_TSADC_P 159
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||||
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#define RK3288_SOFT_RST_DDRPHY0 160
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||||
#define RK3288_SOFT_RST_DDRPHY0_P 161
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||||
#define RK3288_SOFT_RST_DDRCTRL0 162
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||||
#define RK3288_SOFT_RST_DDRCTRL0_P 163
|
||||
#define RK3288_SOFT_RST_DDRPHY0_CTL 164
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||||
#define RK3288_SOFT_RST_DDRPHY1 165
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||||
#define RK3288_SOFT_RST_DDRPHY1_P 166
|
||||
#define RK3288_SOFT_RST_DDRCTRL1 167
|
||||
#define RK3288_SOFT_RST_DDRCTRL1_P 168
|
||||
#define RK3288_SOFT_RST_DDRPHY1_CTL 169
|
||||
#define RK3288_SOFT_RST_DDRMSCH0 170
|
||||
#define RK3288_SOFT_RST_DDRMSCH1 171
|
||||
#define RK3288_SOFT_RST_10RES12 172
|
||||
#define RK3288_SOFT_RST_10RES13 173
|
||||
#define RK3288_SOFT_RST_CRYPTO 174
|
||||
#define RK3288_SOFT_RST_C2C_HOST 175
|
||||
|
||||
#define RK3288_SOFT_RST_LCDC1_A 176
|
||||
#define RK3288_SOFT_RST_LCDC1_H 177
|
||||
#define RK3288_SOFT_RST_LCDC1_D 178
|
||||
#define RK3288_SOFT_RST_UART0 179
|
||||
#define RK3288_SOFT_RST_UART1 180
|
||||
#define RK3288_SOFT_RST_UART2 181
|
||||
#define RK3288_SOFT_RST_UART3 182
|
||||
#define RK3288_SOFT_RST_UART4 183
|
||||
#define RK3288_SOFT_RST_11RES8 184
|
||||
#define RK3288_SOFT_RST_11RES9 185
|
||||
#define RK3288_SOFT_RST_SIMC 186
|
||||
#define RK3288_SOFT_RST_PS2C 187
|
||||
#define RK3288_SOFT_RST_TSP 188
|
||||
#define RK3288_SOFT_RST_TSP_CLKIN0 189
|
||||
#define RK3288_SOFT_RST_TSP_CLKIN1 190
|
||||
#define RK3288_SOFT_RST_TSP_27M 191
|
||||
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3288_H */
|
||||
|
||||
@@ -79,5 +79,7 @@
|
||||
#define CLK_PD_VIO 13
|
||||
#define CLK_PD_VIRT 255
|
||||
|
||||
/* reset flag */
|
||||
#define ROCKCHIP_RESET_HIWORD_MASK BIT(0)
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_H */
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
#define __MACH_ROCKCHIP_CRU_H
|
||||
|
||||
#include <dt-bindings/clock/rockchip,rk3188.h>
|
||||
#include <dt-bindings/clock/rockchip,rk3288.h>
|
||||
#include <linux/rockchip/iomap.h>
|
||||
|
||||
|
||||
@@ -116,213 +117,7 @@ enum rk3288_cru_clk_gate {
|
||||
#define RK3288_CRU_SOFTRSTS_CON_CNT (12)
|
||||
#define RK3288_CRU_SOFTRSTS_CON(i) (RK3288_CRU_SOFTRST_CON + ((i) * 4))
|
||||
|
||||
enum rk3288_cru_soft_reset {
|
||||
RK3288_SOFT_RST_CORE0,
|
||||
RK3288_SOFT_RST_CORE1,
|
||||
RK3288_SOFT_RST_CORE2,
|
||||
RK3288_SOFT_RST_CORE3,
|
||||
RK3288_SOFT_RST_CORE0_PO,
|
||||
RK3288_SOFT_RST_CORE1_PO,
|
||||
RK3288_SOFT_RST_CORE2_PO,
|
||||
RK3288_SOFT_RST_CORE3_PO,
|
||||
RK3288_SOFT_RST_PD_CORE_STR_SYS_A,
|
||||
RK3288_SOFT_RST_PD_BUS_STR_SYS_A,
|
||||
RK3288_SOFT_RST_L2C,
|
||||
RK3288_SOFT_RST_TOPDBG,
|
||||
RK3288_SOFT_RST_CORE0_DBG,
|
||||
RK3288_SOFT_RST_CORE1_DBG,
|
||||
RK3288_SOFT_RST_CORE2_DBG,
|
||||
RK3288_SOFT_RST_CORE3_DBG,
|
||||
|
||||
RK3288_SOFT_RST_PD_BUS_AHB_ARBITOR,
|
||||
RK3288_SOFT_RST_EFUSE_256BIT_P,
|
||||
RK3288_SOFT_RST_DMA1,
|
||||
RK3288_SOFT_RST_INTMEM,
|
||||
RK3288_SOFT_RST_ROM,
|
||||
RK3288_SOFT_RST_SPDIF_8CH,
|
||||
RK3288_SOFT_RST_TIMER_P,
|
||||
RK3288_SOFT_RST_I2S,
|
||||
RK3288_SOFT_RST_SPDIF,
|
||||
RK3288_SOFT_RST_TIMER0,
|
||||
RK3288_SOFT_RST_TIMER1,
|
||||
RK3288_SOFT_RST_TIMER2,
|
||||
RK3288_SOFT_RST_TIMER3,
|
||||
RK3288_SOFT_RST_TIMER4,
|
||||
RK3288_SOFT_RST_TIMER5,
|
||||
RK3288_SOFT_RST_EFUSE_P,
|
||||
|
||||
RK3288_SOFT_RST_GPIO0,
|
||||
RK3288_SOFT_RST_GPIO1,
|
||||
RK3288_SOFT_RST_GPIO2,
|
||||
RK3288_SOFT_RST_GPIO3,
|
||||
RK3288_SOFT_RST_GPIO4,
|
||||
RK3288_SOFT_RST_GPIO5,
|
||||
RK3288_SOFT_RST_GPIO6,
|
||||
RK3288_SOFT_RST_GPIO7,
|
||||
RK3288_SOFT_RST_GPIO8,
|
||||
RK3288_SOFT_RST_2RES9,
|
||||
RK3288_SOFT_RST_I2C0,
|
||||
RK3288_SOFT_RST_I2C1,
|
||||
RK3288_SOFT_RST_I2C2,
|
||||
RK3288_SOFT_RST_I2C3,
|
||||
RK3288_SOFT_RST_I2C4,
|
||||
RK3288_SOFT_RST_I2C5,
|
||||
|
||||
RK3288_SOFT_RST_DW_PWM,
|
||||
RK3288_SOFT_RST_MMC_PERI,
|
||||
RK3288_SOFT_RST_PERIPH_MMU,
|
||||
RK3288_SOFT_RST_DAP,
|
||||
RK3288_SOFT_RST_DAP_SYS,
|
||||
RK3288_SOFT_RST_TPIU_AT,
|
||||
RK3288_SOFT_RST_PMU_P,
|
||||
RK3288_SOFT_RST_GRF,
|
||||
RK3288_SOFT_RST_PMU,
|
||||
RK3288_SOFT_RST_PERIPHSYS_A,
|
||||
RK3288_SOFT_RST_PERIPHSYS_H,
|
||||
RK3288_SOFT_RST_PERIPHSYS_P,
|
||||
RK3288_SOFT_RST_PERIPH_NIU,
|
||||
RK3288_SOFT_RST_PD_PERI_AHB_ARBITOR,
|
||||
RK3288_SOFT_RST_EMEM_PERI,
|
||||
RK3288_SOFT_RST_USB_PERI,
|
||||
|
||||
RK3288_SOFT_RST_DMA2,
|
||||
RK3288_SOFT_RST_4RES1,
|
||||
RK3288_SOFT_RST_MAC,
|
||||
RK3288_SOFT_RST_GPS,
|
||||
RK3288_SOFT_RST_4RES4,
|
||||
RK3288_SOFT_RST_RK_PWM,
|
||||
RK3288_SOFT_RST_4RES6,
|
||||
RK3288_SOFT_RST_CCP,
|
||||
RK3288_SOFT_RST_USB_HOST0,
|
||||
RK3288_SOFT_RST_HSIC,
|
||||
RK3288_SOFT_RST_HSIC_AUX,
|
||||
RK3288_SOFT_RST_HSICPHY,
|
||||
RK3288_SOFT_RST_HSADC,
|
||||
RK3288_SOFT_RST_NANDC0,
|
||||
RK3288_SOFT_RST_NANDC1,
|
||||
RK3288_SOFT_RST_4RES15,
|
||||
|
||||
RK3288_SOFT_RST_TZPC,
|
||||
RK3288_SOFT_RST_5RES1,
|
||||
RK3288_SOFT_RST_5RES2,
|
||||
RK3288_SOFT_RST_SPI0,
|
||||
RK3288_SOFT_RST_SPI1,
|
||||
RK3288_SOFT_RST_SPI2,
|
||||
RK3288_SOFT_RST_5RES6,
|
||||
RK3288_SOFT_RST_SARADC,
|
||||
RK3288_SOFT_RST_PD_ALIVE_NIU_P,
|
||||
RK3288_SOFT_RST_PD_PMU_INTMEM_P,
|
||||
RK3288_SOFT_RST_PD_PMU_NIU_P,
|
||||
RK3288_SOFT_RST_SECURITY_GRF_P,
|
||||
RK3288_SOFT_RST_5RES12,
|
||||
RK3288_SOFT_RST_5RES13,
|
||||
RK3288_SOFT_RST_5RES14,
|
||||
RK3288_SOFT_RST_5RES15,
|
||||
|
||||
RK3288_SOFT_RST_VIO_ARBI_H,
|
||||
RK3288_SOFT_RST_RGA_NIU_A,
|
||||
RK3288_SOFT_RST_VIO0_NIU_A,
|
||||
RK3288_SOFT_RST_VIO_NIU_H,
|
||||
RK3288_SOFT_RST_LCDC0_A,
|
||||
RK3288_SOFT_RST_LCDC0_H,
|
||||
RK3288_SOFT_RST_LCDC0_D,
|
||||
RK3288_SOFT_RST_VIO1_NIU_A,
|
||||
RK3288_SOFT_RST_VIP,
|
||||
RK3288_SOFT_RST_RGA_CORE,
|
||||
RK3288_SOFT_RST_IEP_A,
|
||||
RK3288_SOFT_RST_IEP_H,
|
||||
RK3288_SOFT_RST_RGA_A,
|
||||
RK3288_SOFT_RST_RGA_H,
|
||||
RK3288_SOFT_RST_ISP,
|
||||
RK3288_SOFT_RST_EDP,
|
||||
|
||||
RK3288_SOFT_RST_VCODEC_A,
|
||||
RK3288_SOFT_RST_VCODEC_H,
|
||||
RK3288_SOFT_RST_VIO_H2P_H,
|
||||
RK3288_SOFT_RST_MIPIDSI0_P,
|
||||
RK3288_SOFT_RST_MIPIDSI1_P,
|
||||
RK3288_SOFT_RST_MIPICSI_P,
|
||||
RK3288_SOFT_RST_LVDS_PHY_P,
|
||||
RK3288_SOFT_RST_LVDS_CON,
|
||||
RK3288_SOFT_RST_GPU,
|
||||
RK3288_SOFT_RST_HDMI,
|
||||
RK3288_SOFT_RST_7RES10,
|
||||
RK3288_SOFT_RST_7RES11,
|
||||
RK3288_SOFT_RST_CORE_PVTM,
|
||||
RK3288_SOFT_RST_GPU_PVTM,
|
||||
RK3288_SOFT_RST_7RES14,
|
||||
RK3288_SOFT_RST_7RES15,
|
||||
|
||||
RK3288_SOFT_RST_MMC0,
|
||||
RK3288_SOFT_RST_SDIO0,
|
||||
RK3288_SOFT_RST_SDIO1,
|
||||
RK3288_SOFT_RST_EMMC,
|
||||
RK3288_SOFT_RST_USBOTG_H,
|
||||
RK3288_SOFT_RST_USBOTGPHY,
|
||||
RK3288_SOFT_RST_USBOTGC,
|
||||
RK3288_SOFT_RST_USBHOST0_H,
|
||||
RK3288_SOFT_RST_USBHOST0PHY,
|
||||
RK3288_SOFT_RST_USBHOST0C,
|
||||
RK3288_SOFT_RST_USBHOST1_H,
|
||||
RK3288_SOFT_RST_USBHOST1PHY,
|
||||
RK3288_SOFT_RST_USBHOST1C,
|
||||
RK3288_SOFT_RST_USB_ADP,
|
||||
RK3288_SOFT_RST_ACC_EFUSE,
|
||||
RK3288_SOFT_RST_8RES15,
|
||||
|
||||
RK3288_SOFT_RST_CORESIGHT,
|
||||
RK3288_SOFT_RST_PD_CORE_AHB_NOC,
|
||||
RK3288_SOFT_RST_PD_CORE_APB_NOC,
|
||||
RK3288_SOFT_RST_PD_CORE_MP_AXI,
|
||||
RK3288_SOFT_RST_GIC,
|
||||
RK3288_SOFT_RST_LCDCPWM0,
|
||||
RK3288_SOFT_RST_LCDCPWM1,
|
||||
RK3288_SOFT_RST_VIO0_H2P_BRG,
|
||||
RK3288_SOFT_RST_VIO1_H2P_BRG,
|
||||
RK3288_SOFT_RST_RGA_H2P_BRG,
|
||||
RK3288_SOFT_RST_HEVC,
|
||||
RK3288_SOFT_RST_9RES11,
|
||||
RK3288_SOFT_RST_9RES12,
|
||||
RK3288_SOFT_RST_9RES13,
|
||||
RK3288_SOFT_RST_9RES14,
|
||||
RK3288_SOFT_RST_TSADC_P,
|
||||
|
||||
RK3288_SOFT_RST_DDRPHY0,
|
||||
RK3288_SOFT_RST_DDRPHY0_P,
|
||||
RK3288_SOFT_RST_DDRCTRL0,
|
||||
RK3288_SOFT_RST_DDRCTRL0_P,
|
||||
RK3288_SOFT_RST_DDRPHY0_CTL,
|
||||
RK3288_SOFT_RST_DDRPHY1,
|
||||
RK3288_SOFT_RST_DDRPHY1_P,
|
||||
RK3288_SOFT_RST_DDRCTRL1,
|
||||
RK3288_SOFT_RST_DDRCTRL1_P,
|
||||
RK3288_SOFT_RST_DDRPHY1_CTL,
|
||||
RK3288_SOFT_RST_DDRMSCH0,
|
||||
RK3288_SOFT_RST_DDRMSCH1,
|
||||
RK3288_SOFT_RST_10RES12,
|
||||
RK3288_SOFT_RST_10RES13,
|
||||
RK3288_SOFT_RST_CRYPTO,
|
||||
RK3288_SOFT_RST_C2C_HOST,
|
||||
|
||||
RK3288_SOFT_RST_LCDC1_A,
|
||||
RK3288_SOFT_RST_LCDC1_H,
|
||||
RK3288_SOFT_RST_LCDC1_D,
|
||||
RK3288_SOFT_RST_UART0,
|
||||
RK3288_SOFT_RST_UART1,
|
||||
RK3288_SOFT_RST_UART2,
|
||||
RK3288_SOFT_RST_UART3,
|
||||
RK3288_SOFT_RST_UART4,
|
||||
RK3288_SOFT_RST_11RES8,
|
||||
RK3288_SOFT_RST_11RES9,
|
||||
RK3288_SOFT_RST_SIMC,
|
||||
RK3288_SOFT_RST_PS2C,
|
||||
RK3288_SOFT_RST_TSP,
|
||||
RK3288_SOFT_RST_TSP_CLKIN0,
|
||||
RK3288_SOFT_RST_TSP_CLKIN1,
|
||||
RK3288_SOFT_RST_TSP_27M,
|
||||
};
|
||||
|
||||
static inline void rk3288_cru_set_soft_reset(enum rk3288_cru_soft_reset idx, bool on)
|
||||
static inline void rk3288_cru_set_soft_reset(u32 idx, bool on)
|
||||
{
|
||||
void __iomem *reg = RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(idx >> 4);
|
||||
u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
|
||||
|
||||
Reference in New Issue
Block a user