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rk3368: clk: add clocks-init and clocks-enable in DTS

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Signed-off-by: dkl <dkl@rock-chips.com>
This commit is contained in:
dkl
2014-11-13 14:54:22 +08:00
committed by Huang, Tao
parent c83fb066be
commit 322cfe7421
3 changed files with 82 additions and 3 deletions
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10
arch/arm64/boot/dts/rk3368-clocks.dtsi
View File

@@ -424,6 +424,7 @@
clock-output-names = "clkin_trace";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};
@@ -580,6 +581,7 @@
clock-output-names = "pclk_pmu_pre";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* 7:5 reserved */
@@ -591,6 +593,7 @@
clock-output-names = "pclk_alive_pre";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* 13 reserved */
@@ -676,8 +679,6 @@
/* 7:5 reserved */
/* usbphy_480m_en */
usbphy_480m: usbphy_480m_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 1>;
@@ -733,6 +734,7 @@
clock-output-names = "aclk_gpu_mem";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* 13 reserved */
@@ -1175,6 +1177,7 @@
clocks = <&clk_cpll>, <&clk_gpll>;
clock-output-names = "i2s_pll";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* 14:13 reserved */
@@ -1248,6 +1251,7 @@
clocks = <&clk_cpll>, <&clk_gpll>;
clock-output-names = "spdif_8ch_pll";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
/* 15:13 reserved */
@@ -1545,6 +1549,7 @@
clock-output-names = "clk_mac";
#clock-cells = <0>;
rockchip,flags = <CLK_SET_RATE_PARENT>;
#clock-init-cells = <1>;
};
/* 11:9 reserved */
@@ -1837,6 +1842,7 @@
clocks = <&clk_cpll>, <&clk_gpll>;
clock-output-names = "i2s_2ch_pll";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
};

74
arch/arm64/boot/dts/rk3368.dtsi
View File

@@ -44,7 +44,7 @@
};
chosen {
bootargs = "console=ttyS2 earlyprintk=uart8250-32bit,0xff690000";
bootargs = "console=ttyS2 earlyprintk=uart8250-32bit,0xff690000 clk_ignore_unused";
};
timer {
@@ -86,6 +86,78 @@
reg = <0x0 0xff770000 0x0 0x1000>;
};
rockchip_clocks_init: clocks-init{
compatible = "rockchip,clocks-init";
rockchip,clocks-init-parent =
<&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
<&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
<&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>;
rockchip,clocks-init-rate =
<&clk_core_b 792000000>, <&clk_core_l 600000000>,
<&clk_gpll 576000000>, <&clk_cpll 400000000>,
/*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
<&hclk_bus 150000000>, <&pclk_bus 75000000>,
<&clk_crypto 150000000>, <&aclk_peri 300000000>,
<&hclk_peri 150000000>, <&pclk_peri 75000000>,
<&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
<&aclk_vio0 400000000>, <&hclk_vio 100000000>,
<&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
<&clk_isp 400000000>, <&clk_edp 200000000>,
<&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
<&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
<&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
<&clk_hevc_cabac 300000000>, <&clk_mac 50000000>;
/*rockchip,clocks-uboot-has-init =
<&aclk_vio0>;*/
};
rockchip_clocks_enable: clocks-enable {
compatible = "rockchip,clocks-enable";
clocks =
/*PLL*/
<&clk_apllb>,
<&clk_aplll>,
<&clk_dpll>,
<&clk_gpll>,
<&clk_cpll>,
/*PD_CORE*/
<&clk_cs>,
<&clkin_trace>,
/*PD_BUS*/
<&aclk_bus>,
<&hclk_bus>,
<&pclk_bus>,
<&clk_gates12 12>,/*aclk_strc_sys*/
<&clk_gates12 6>,/*aclk_intmem1*/
<&clk_gates12 5>,/*aclk_intmem0*/
<&clk_gates12 4>,/*aclk_intmem*/
<&clk_gates13 9>,/*aclk_gic400*/
/*PD_ALIVE*/
<&clk_gates22 13>,/*pclk_timer1*/
<&clk_gates22 12>,/*pclk_timer0*/
<&clk_gates22 9>,/*pclk_alive_niu*/
<&clk_gates22 8>,/*pclk_grf*/
/*PD_PMU*/
<&clk_gates23 5>,/*pclk_pmugrf*/
<&clk_gates23 3>,/*pclk_sgrf*/
<&clk_gates23 2>,/*pclk_pmu_noc*/
<&clk_gates23 1>,/*pclk_intmem1*/
<&clk_gates23 0>,/*pclk_pmu*/
/*PD_PERI*/
<&clk_gates19 2>,/*aclk_peri_axi_matrix*/
<&clk_gates20 8>,/*aclk_peri_niu*/
<&clk_gates21 4>,/*aclk_peri_mmu*/
<&clk_gates19 0>,/*hclk_peri_axi_matrix*/
<&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
<&clk_gates19 1>;/*pclk_peri_axi_matrix*/
};
i2c0: i2c@ff650000 {
compatible = "rockchip,rk30-i2c";
reg = <0x0 0xff650000 0x0 0x1000>;

1
drivers/clk/rockchip/clk-pll.c
View File

@@ -31,6 +31,7 @@ static const struct pll_clk_set rk3188plus_pll_com_table[] = {
_RK3188PLUS_PLL_SET_CLKS(891000, 8, 594, 2),
_RK3188PLUS_PLL_SET_CLKS(768000, 1, 64, 2),
_RK3188PLUS_PLL_SET_CLKS(594000, 2, 198, 4),
_RK3188PLUS_PLL_SET_CLKS(576000, 1, 48, 2),
_RK3188PLUS_PLL_SET_CLKS(500000, 3, 250, 4),
_RK3188PLUS_PLL_SET_CLKS(408000, 1, 68, 4),
_RK3188PLUS_PLL_SET_CLKS(400000, 3, 200, 4),