drm/rockchip: vop2: update win dly for rk3562

Update win dly number according new TRM. Without this commit, the left 4
columns will display black when act width is 2048.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ie8b6d999c530c8836cb847e8809c5cdc6a3fdc7b
This commit is contained in:
Sandy Huang
2024-07-24 15:27:25 +08:00
committed by Tao Huang
parent 03f44b662b
commit 3248d77d05

View File

@@ -1235,7 +1235,7 @@ static const struct vop2_video_port_data rk3562_vop_video_ports[] = {
.cubic_lut_len = 729, /* 9x9x9 */
.dclk_max = 200000000,
.max_output = { 2048, 4096 },
.win_dly = 8,
.win_dly = 6,
.layer_mix_dly = 8,
.intr = &rk3568_vp0_intr,
.regs = &rk3562_vop_vp0_regs,