shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 20:07:46 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: rockchip: rv1126: Add CLK_32K_IOE support

Browse Source 
Add clk_32k_ioe to select 32k io as input or output.

Change-Id: I2c32af4bded53c91280a0dbbd54af17f2f90e843
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2020-11-24 16:01:38 +08:00
committed by Tao Huang
parent 9935afc20e
commit 3256732d55
2 changed files with 6 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/clk/rockchip/clk-rv1126.c
View File

@@ -14,6 +14,7 @@
#define RV1126_GMAC_CON 0x460
#define RV1126_GRF_IOFUNC_CON1 0x10264
#define RV1126_GRF_SOC_STATUS0 0x10
#define RV1126_PMUGRF_SOC_CON0 0x100
#define RV1126_FRAC_MAX_PRATE 1200000000
#define RV1126_CSIOUT_FRAC_MAX_PRATE 300000000
@@ -145,6 +146,7 @@ static const struct rockchip_cpuclk_reg_data rv1126_cpuclk_data = {
PNAME(mux_pll_p) = { "xin24m" };
PNAME(mux_rtc32k_p) = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
PNAME(mux_clk_32k_ioe_p) = { "xin32k", "clk_rtc32k" };
PNAME(mux_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
@@ -350,6 +352,9 @@ static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
RV1126_PMU_CLKGATE_CON(2), 9, GFLAGS,
&rv1126_rtc32k_fracmux, 0),
MUXPMUGRF(CLK_32K_IOE, "clk_32k_ioe", mux_clk_32k_ioe_p, 0,
RV1126_PMUGRF_SOC_CON0, 0, 1, MFLAGS),
COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "gpll", 0,
RV1126_PMU_CLKSEL_CON(12), 0, 6, DFLAGS,
RV1126_PMU_CLKGATE_CON(2), 10, GFLAGS),

1
include/dt-bindings/clock/rv1126-cru.h
View File

@@ -38,6 +38,7 @@
#define CLK_USBPHY_HOST_REF 24
#define CLK_REF24M 25
#define CLK_MIPIDSIPHY_REF 26
#define CLK_32K_IOE 27
/* pclk */
#define PCLK_PDPMU 30