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ARM: dts: enable some devices for rk3126-evb

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RK3126-evb use andriod as system, so we put the common nodes for
andriod into rk312x-andriod.dtsi. This patch enable devices:
emmc/sdmmc/sdio/fiq-debugger/ramoops/cpufreq/ddrfreq.

Change-Id: I24993486711dd5b6050c03667545c9cb147e1b64
Signed-off-by: Liang Chen <cl@rock-chips.com>
This commit is contained in:
Liang Chen
2017-09-05 20:15:40 +08:00
parent 85884ca6a0
commit 325c08fcda
3 changed files with 273 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

71
arch/arm/boot/dts/rk3126-evb.dts
View File

@@ -39,10 +39,11 @@
*/
/dts-v1/;
#include "rk3126.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3126.dtsi"
#include "rk312x-android.dtsi"
/ {
model = "Rockchip RK3126 Evaluation board";
@@ -88,10 +89,6 @@
enable-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
};
chosen {
bootargs = "console=uart8250,mmio32,0x20068000";
};
lvds_panel: lvds-panel {
status = "disabled";
ports {
@@ -101,17 +98,6 @@
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
drm_logo: drm-logo@00000000 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0>;
};
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
@@ -121,22 +107,40 @@
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&display_subsystem {
status = "okay";
memory-region = <&drm_logo>;
route {
route_lvds: route-lvds {
status = "okay";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vop_out_lvds>;
};
};
};
&dmc {
center-supply = <&vdd_log>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
supports-emmc;
disable-wp;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
&gpu {
status = "okay";
mali-supply = <&vdd_log>;
};
&i2c2 {
status = "okay";
clock-frequency = <400000>;
@@ -385,8 +389,25 @@
status = "okay";
};
&uart2 {
status = "okay";
&sdmmc {
cap-mmc-highspeed;
supports-sd;
broken-cd;
card-detect-delay = <800>;
ignore-pm-notify;
keep-power-in-suspend;
cd-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* CD GPIO */
status = "disabled";
};
&sdio {
cap-mmc-highspeed;
supports-sdio;
ignore-pm-notify;
keep-power-in-suspend;
non-removable;
cap-sdio-irq;
status = "disabled";
};
&vop {

72
arch/arm/boot/dts/rk3128-dram-default-timing.dtsi Normal file
View File

@@ -0,0 +1,72 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/rockchip-ddr.h>
#include <dt-bindings/memory/rk3128-dram.h>
/ {
ddr_timing: ddr_timing {
compatible = "rockchip,ddr-timing";
ddr3_speed_bin = <DDR3_DEFAULT>;
pd_idle = <0x40>;
sr_idle = <0x1>;
auto_pd_dis_freq = <300>;
auto_sr_dis_freq = <300>;
ddr3_dll_dis_freq = <300>;
lpddr2_dll_dis_freq = <300>;
phy_dll_dis_freq = <266>;
ddr3_odt_dis_freq = <333>;
phy_ddr3_odt_disb_freq = <333>;
ddr3_drv = <DDR3_DS_40ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
phy_ddr3_clk_drv = <PHY_RON_44ohm>;
phy_ddr3_cmd_drv = <PHY_RON_44ohm>;
phy_ddr3_dqs_drv = <PHY_RON_44ohm>;
phy_ddr3_odt = <PHY_RTT_216ohm>;
lpddr2_drv = <LP2_DS_34ohm>;
phy_lpddr2_clk_drv = <PHY_RON_44ohm>;
phy_lpddr2_cmd_drv = <PHY_RON_44ohm>;
phy_lpddr2_dqs_drv = <PHY_RON_44ohm>;
};
};

155
arch/arm/boot/dts/rk312x-android.dtsi Normal file
View File

@@ -0,0 +1,155 @@
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/soc/rockchip-system-status.h>
#include "rk3128-dram-default-timing.dtsi"
/ {
chosen {
bootargs = "earlycon=uart8250,mmio32,0x20068000";
};
cpuinfo {
compatible = "rockchip,cpuinfo";
nvmem-cells = <&efuse_id>;
nvmem-cell-names = "id";
};
dfi: dfi {
compatible = "rockchip,rk3128-dfi";
rockchip,pmu = <&pmu>;
rockchip,grf = <&grf>;
status = "okay";
};
dmc: dmc {
compatible = "rockchip,rk3128-dmc";
devfreq-events = <&dfi>;
clocks = <&cru SCLK_DDRC>;
clock-names = "dmc_clk";
upthreshold = <55>;
downdifferential = <10>;
operating-points-v2 = <&dmc_opp_table>;
vop-dclk-mode = <0>;
min-cpu-freq = <600000>;
rockchip,ddr_timing = <&ddr_timing>;
system-status-freq = <
/*system status freq(KHz)*/
SYS_STATUS_NORMAL 456000
SYS_STATUS_SUSPEND 200000
>;
auto-min-freq = <300000>;
auto-freq-en = <0>;
status = "okay";
};
dmc_opp_table: opp_table2 {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <950000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <950000>;
};
opp-396000000 {
opp-hz = /bits/ 64 <396000000>;
opp-microvolt = <1100000>;
};
opp-456000000 {
opp-hz = /bits/ 64 <456000000>;
opp-microvolt = <1200000>;
};
};
fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <2>;
rockchip,signal-irq = <159>;
rockchip,wake-irq = <0>;
/* If enable uart uses irq instead of fiq */
rockchip,irq-mode-enable = <1>;
rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
ramoops_mem: ramoops@00000000 {
reg = <0x68000000 0xf0000>;
};
drm_logo: drm-logo@00000000 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0>;
};
};
ramoops {
compatible = "ramoops";
record-size = <0x0 0x20000>;
console-size = <0x0 0x80000>;
ftrace-size = <0x0 0x00000>;
pmsg-size = <0x0 0x50000>;
memory-region = <&ramoops_mem>;
};
};
&display_subsystem {
memory-region = <&drm_logo>;
route {
route_lvds: route-lvds {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vop_out_lvds>;
};
};
};