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rk30: pmu: wait ack when idle request
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@@ -40,6 +40,10 @@ void pmu_set_power_domain(enum pmu_power_domain pd, bool on)
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unsigned long flags;
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spin_lock_irqsave(&pmu_pd_lock, flags);
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if (pmu_power_domain_is_on(pd) == on) {
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spin_unlock_irqrestore(&pmu_pd_lock, flags);
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return;
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}
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if (!on) {
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/* if power down, idle request to NIU first */
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if (pd == PD_VIO)
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@@ -69,6 +73,8 @@ void pmu_set_idle_request(enum pmu_idle_req req, bool idle)
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{
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u32 idle_mask = 1 << (26 - req);
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u32 idle_target = idle << (26 - req);
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u32 ack_mask = 1 << (31 - req);
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u32 ack_target = idle << (31 - req);
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u32 mask = 1 << (req + 1);
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u32 val;
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unsigned long flags;
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@@ -77,9 +83,13 @@ void pmu_set_idle_request(enum pmu_idle_req req, bool idle)
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if (req == IDLE_REQ_CORE) {
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idle_mask = 1 << 15;
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idle_target = idle << 15;
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ack_mask = 1 << 18;
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ack_target = idle << 18;
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} else if (req == IDLE_REQ_DMA) {
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idle_mask = 1 << 14;
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idle_target = idle << 14;
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ack_mask = 1 << 17;
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ack_target = idle << 17;
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}
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#endif
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@@ -92,6 +102,8 @@ void pmu_set_idle_request(enum pmu_idle_req req, bool idle)
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writel_relaxed(val, RK30_PMU_BASE + PMU_MISC_CON1);
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dsb();
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while ((readl_relaxed(RK30_PMU_BASE + PMU_PWRDN_ST) & ack_mask) != ack_target)
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;
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while ((readl_relaxed(RK30_PMU_BASE + PMU_PWRDN_ST) & idle_mask) != idle_target)
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;
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spin_unlock_irqrestore(&pmu_misc_con1_lock, flags);
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