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arm64: dts: fsl: adjust whitespace around '='

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Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment.  No functional
changes (same DTB).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
2022-05-26 22:42:56 +02:00
committed by Shawn Guo
parent 4a154e5ab9
commit 33597c6257
24 changed files with 88 additions and 88 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View File

@@ -204,7 +204,7 @@
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -212,7 +212,7 @@
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -220,7 +220,7 @@
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -228,7 +228,7 @@
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
};

2
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
View File

@@ -93,7 +93,7 @@
compatible = "mdio-mux-multiplexer";
mux-controls = <&mux 0>;
mdio-parent-bus = <&enetc_mdio_pf3>;
#address-cells=<1>;
#address-cells = <1>;
#size-cells = <0>;
/* on-board RGMII PHY */

16
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@@ -96,7 +96,7 @@
};
reboot {
compatible ="syscon-reboot";
compatible = "syscon-reboot";
regmap = <&rst>;
offset = <0>;
mask = <0x02>;
@@ -120,13 +120,13 @@
};
gic: interrupt-controller@6000000 {
compatible= "arm,gic-v3";
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
<0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
#interrupt-cells= <3>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_LOW)>;
@@ -769,28 +769,28 @@
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
};
};

10
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@@ -144,7 +144,7 @@
};
reboot {
compatible ="syscon-reboot";
compatible = "syscon-reboot";
regmap = <&dcfg>;
offset = <0xb0>;
mask = <0x02>;
@@ -354,7 +354,7 @@
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
reg = <0x10000 0x10000>;
interrupts = <0 71 0x4>;
};
@@ -362,7 +362,7 @@
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
reg = <0x20000 0x10000>;
interrupts = <0 72 0x4>;
};
@@ -370,7 +370,7 @@
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
reg = <0x30000 0x10000>;
interrupts = <0 73 0x4>;
};
@@ -378,7 +378,7 @@
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
reg = <0x40000 0x10000>;
interrupts = <0 74 0x4>;
};
};

10
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@@ -112,7 +112,7 @@
};
reboot {
compatible ="syscon-reboot";
compatible = "syscon-reboot";
regmap = <&dcfg>;
offset = <0xb0>;
mask = <0x02>;
@@ -360,7 +360,7 @@
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -368,7 +368,7 @@
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -376,7 +376,7 @@
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -384,7 +384,7 @@
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
};
};

8
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@@ -526,28 +526,28 @@
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
};
};

10
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@@ -73,7 +73,7 @@
};
reboot {
compatible ="syscon-reboot";
compatible = "syscon-reboot";
regmap = <&rstcr>;
offset = <0x0>;
mask = <0x2>;
@@ -479,28 +479,28 @@
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
};
};

4
arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
View File

@@ -36,7 +36,7 @@
compatible = "mdio-mux-multiplexer";
mux-controls = <&mux 0>;
mdio-parent-bus = <&emdio1>;
#address-cells=<1>;
#address-cells = <1>;
#size-cells = <0>;
mdio@0 { /* On-board PHY #1 RGMI1*/
@@ -104,7 +104,7 @@
compatible = "mdio-mux-multiplexer";
mux-controls = <&mux 1>;
mdio-parent-bus = <&emdio2>;
#address-cells=<1>;
#address-cells = <1>;
#size-cells = <0>;
mdio@0 { /* Slot #1 (secondary EMI) */

8
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@@ -632,28 +632,28 @@
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
};
};

4
arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
View File

@@ -34,7 +34,7 @@
compatible = "mdio-mux-multiplexer";
mux-controls = <&mux 0>;
mdio-parent-bus = <&emdio1>;
#address-cells=<1>;
#address-cells = <1>;
#size-cells = <0>;
mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */
@@ -114,7 +114,7 @@
compatible = "mdio-mux-multiplexer";
mux-controls = <&mux 1>;
mdio-parent-bus = <&emdio2>;
#address-cells=<1>;
#address-cells = <1>;
#size-cells = <0>;
mdio@0 { /* Slot #1 (secondary EMI) */

10
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
View File

@@ -54,7 +54,7 @@ conn_subsys: bus@5b000000 {
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
status = "disabled";
};
@@ -83,8 +83,8 @@ conn_subsys: bus@5b000000 {
assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
power-domains = <&pd IMX_SC_R_ENET_0>;
status = "disabled";
};
@@ -103,8 +103,8 @@ conn_subsys: bus@5b000000 {
assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
power-domains = <&pd IMX_SC_R_ENET_1>;
status = "disabled";
};

4
arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
View File

@@ -285,14 +285,14 @@
&usbotg1 {
vbus-supply = <&reg_usbotg1>;
disable-over-current;
dr_mode="otg";
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
disable-over-current;
dr_mode="host";
dr_mode = "host";
status = "okay";
};

12
arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi
View File

@@ -84,42 +84,42 @@
};
reg_buck1: buck1 {
regulator-min-microvolt = <400000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck2: buck2 {
regulator-min-microvolt = <400000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck3: buck3 {
regulator-min-microvolt = <400000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck4: buck4 {
regulator-min-microvolt = <400000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck5: buck5 {
regulator-min-microvolt = <400000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_buck6: buck6 {
regulator-min-microvolt = <400000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;

16
arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
View File

@@ -286,8 +286,8 @@
regulator-name = "buck1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
regulator-min-microamp = <3800000>;
regulator-max-microamp = <6800000>;
regulator-min-microamp = <3800000>;
regulator-max-microamp = <6800000>;
regulator-boot-on;
regulator-always-on;
};
@@ -297,8 +297,8 @@
regulator-name = "buck2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-min-microamp = <2200000>;
regulator-max-microamp = <5200000>;
regulator-min-microamp = <2200000>;
regulator-max-microamp = <5200000>;
regulator-boot-on;
regulator-always-on;
};
@@ -308,8 +308,8 @@
regulator-name = "buck3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
regulator-min-microamp = <3800000>;
regulator-max-microamp = <6800000>;
regulator-min-microamp = <3800000>;
regulator-max-microamp = <6800000>;
regulator-always-on;
};
@@ -318,8 +318,8 @@
regulator-name = "buck4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-min-microamp = <2200000>;
regulator-max-microamp = <5200000>;
regulator-min-microamp = <2200000>;
regulator-max-microamp = <5200000>;
regulator-boot-on;
regulator-always-on;
};

8
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@@ -212,7 +212,7 @@
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <133000000>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext4";
};
@@ -1000,7 +1000,7 @@
<&clk IMX8MM_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -1014,7 +1014,7 @@
<&clk IMX8MM_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -1028,7 +1028,7 @@
<&clk IMX8MM_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};

4
arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi
View File

@@ -146,7 +146,7 @@
};
&easrc {
fsl,asrc-rate = <48000>;
fsl,asrc-rate = <48000>;
status = "okay";
};
@@ -182,7 +182,7 @@
&usbotg1 {
vbus-supply = <&reg_usb_otg_vbus>;
disable-over-current;
dr_mode="otg";
dr_mode = "otg";
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
View File

@@ -78,7 +78,7 @@
};
&easrc {
fsl,asrc-rate = <48000>;
fsl,asrc-rate = <48000>;
status = "okay";
};

10
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@@ -212,7 +212,7 @@
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <133000000>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext4";
};
@@ -422,7 +422,7 @@
"ctx2_rx", "ctx2_tx",
"ctx3_rx", "ctx3_tx";
firmware-name = "imx/easrc/easrc-imx8mn.bin";
fsl,asrc-rate = <8000>;
fsl,asrc-rate = <8000>;
fsl,asrc-format = <2>;
status = "disabled";
};
@@ -941,7 +941,7 @@
<&clk IMX8MN_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -955,7 +955,7 @@
<&clk IMX8MN_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -969,7 +969,7 @@
<&clk IMX8MN_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};

8
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@@ -195,7 +195,7 @@
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <133000000>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext4";
};
@@ -903,7 +903,7 @@
<&clk IMX8MP_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -917,7 +917,7 @@
<&clk IMX8MP_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -931,7 +931,7 @@
<&clk IMX8MP_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};

4
arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
View File

@@ -152,7 +152,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_arm_dram>;
reg = <0x60>;
regulator-min-microvolt = <900000>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
@@ -186,7 +186,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
reg = <0x60>;
regulator-min-microvolt = <900000>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;

2
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
View File

@@ -443,7 +443,7 @@
status = "okay";
usbhub: usbhub@2c {
compatible ="microchip,usb2513b";
compatible = "microchip,usb2513b";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbhub>;
reg = <0x2c>;

4
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@@ -94,7 +94,7 @@
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <133000000>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext4";
};
@@ -507,7 +507,7 @@
<0x00030005 0x00000053>,
<0x00030006 0x0000005f>,
<0x00030007 0x00000071>;
#thermal-sensor-cells = <1>;
#thermal-sensor-cells = <1>;
};
wdog1: watchdog@30280000 {

6
arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
View File

@@ -38,17 +38,17 @@
/* Colibri UART_B */
&lpuart0 {
status= "okay";
status = "okay";
};
/* Colibri UART_C */
&lpuart2 {
status= "okay";
status = "okay";
};
/* Colibri UART_A */
&lpuart3 {
status= "okay";
status = "okay";
};
/* Colibri FastEthernet */

6
arch/arm64/boot/dts/freescale/imx8ulp.dtsi
View File

@@ -331,7 +331,7 @@
clock-names = "ipg", "ahb", "per";
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -346,7 +346,7 @@
clock-names = "ipg", "ahb", "per";
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};
@@ -361,7 +361,7 @@
clock-names = "ipg", "ahb", "per";
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
bus-width = <4>;
status = "disabled";
};