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drm/amd/display: Support amdgpu "max bpc" connector property (v2)
[ Upstream commit07e3a1cfb0] [Why] Many panels support more than 8bpc but some modes are unavailable while running at greater than 8bpc due to DP/HDMI bandwidth constraints. Support for more than 8bpc was added recently in the driver but it defaults to the maximum supported bpc - locking out these modes. This should be a user configurable option such that the user can select what bpc configuration they would like. [How] This patch adds support for getting and setting the amdgpu driver specific "max bpc" property on the connector. It also adds support for limiting the output bpc based on the property value. The default limitation is the lowest value in the range, 8bpc. This was the old value before the range was uncapped. This patch should be updated/replaced later once common drm support for max bpc lands. Bugzilla: https://bugs.freedesktop.org/108542 Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=201585 Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=200645 Fixes:e03fd3f300("drm/amd/display: Do not limit color depth to 8bpc") v2: rebase on upstream (Alex) Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
a0c25b4098
commit
3374518d4d
@@ -2213,8 +2213,15 @@ static void update_stream_scaling_settings(const struct drm_display_mode *mode,
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static enum dc_color_depth
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convert_color_depth_from_display_info(const struct drm_connector *connector)
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{
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struct dm_connector_state *dm_conn_state =
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to_dm_connector_state(connector->state);
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uint32_t bpc = connector->display_info.bpc;
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/* TODO: Remove this when there's support for max_bpc in drm */
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if (dm_conn_state && bpc > dm_conn_state->max_bpc)
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/* Round down to nearest even number. */
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bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
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switch (bpc) {
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case 0:
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/* Temporary Work around, DRM don't parse color depth for
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@@ -2796,6 +2803,9 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
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} else if (property == adev->mode_info.underscan_property) {
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dm_new_state->underscan_enable = val;
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ret = 0;
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} else if (property == adev->mode_info.max_bpc_property) {
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dm_new_state->max_bpc = val;
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ret = 0;
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}
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return ret;
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@@ -2838,6 +2848,9 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
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} else if (property == adev->mode_info.underscan_property) {
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*val = dm_state->underscan_enable;
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ret = 0;
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} else if (property == adev->mode_info.max_bpc_property) {
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*val = dm_state->max_bpc;
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ret = 0;
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}
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return ret;
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}
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@@ -3658,6 +3671,9 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
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drm_object_attach_property(&aconnector->base.base,
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adev->mode_info.underscan_vborder_property,
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0);
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drm_object_attach_property(&aconnector->base.base,
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adev->mode_info.max_bpc_property,
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0);
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}
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@@ -213,6 +213,7 @@ struct dm_connector_state {
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enum amdgpu_rmx_type scaling;
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uint8_t underscan_vborder;
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uint8_t underscan_hborder;
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uint8_t max_bpc;
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bool underscan_enable;
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struct mod_freesync_user_enable user_enable;
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bool freesync_capable;
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