mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-06 02:50:49 +09:00
Merge commit 'b5fd7789c8033d1431dcd6dc7ab5a095e6cb913a'
* commit 'b5fd7789c8033d1431dcd6dc7ab5a095e6cb913a': (57 commits) arm64: dts: rockchip: rv1126b: add pvtpll node for aisp clk: rockchip: add aisp pvtpll clk for rv1126b media: rockchip: vpss: fix wrap for vpss online spi: rockchip-slave: Add VER3_TYPE2 support spi: spidev-rkmst: Fix wait for ready timeout ARM: dts: rockchip: Add rv1126b-evb1-v10-dual-4k board arm64: dts: rockchip: Add rv1126b-evb1-v10-dual-4k board arm64: dts: rockchip: Add rv1126b-evb1-v10 dtsi drm/rockchip: ebc-dev: remove no use file media: i2c: gc8613 use 30fps setting default arm64: dts: rockchip: rk3576-evb1: enable logo display for module NV140QUM-N61 edp display board arm64: dts: rockchip: add wifibt node for rv1126b evb2/3/4 arm64: dts: rockchip: rv1126b-evb2-v10: add sleep-pin-config media: rockchip: vicap fixes error of proc info media: rockchip: vicap fixes error of sensor power cnt ASoC: rockchip: asrc: support rv1126b asrc media: i2c: add imx766 sensor driver media: i2c: dw9800v add sleep to wait power on arm64/configs: rockchip_linux_defconfig: Add RV1126B SoCs support arm64: dts: rockchip: Enable IRQ mode for fiq-debugger on RV1126B ... Change-Id: I19950686e35aea96e50899a4a6ec427ca5480f8b
This commit is contained in:
Tao Huang
@@ -1177,6 +1177,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
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||||
rv1126-evb-ddr3-v13.dtb \
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||||
rv1126b-evb1-v10.dtb \
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rv1126b-evb1-v10-bt-sco.dtb \
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rv1126b-evb1-v10-dual-4k.dtb \
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||||
rv1126b-evb1-v10-spi-nor.dtb \
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rv1126b-evb2-v10.dtb \
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rv1126b-evb2-v10-mcu-k350c4516t.dtb \
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rv1126b-evb2-v10-rgb-Q7050ITH2641AA1T.dtb \
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6
arch/arm/boot/dts/rv1126b-evb1-v10-dual-4k.dts
Normal file
6
arch/arm/boot/dts/rv1126b-evb1-v10-dual-4k.dts
Normal file
@@ -0,0 +1,6 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
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*/
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#include "arm64/rockchip/rv1126b-evb1-v10-dual-4k.dts"
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6
arch/arm/boot/dts/rv1126b-evb1-v10-spi-nor.dts
Normal file
6
arch/arm/boot/dts/rv1126b-evb1-v10-spi-nor.dts
Normal file
@@ -0,0 +1,6 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
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*/
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#include "arm64/rockchip/rv1126b-evb1-v10-spi-nor.dts"
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@@ -29,6 +29,7 @@ CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
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CONFIG_RK_CMA_PROCFS=y
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CONFIG_RK_DMABUF_PROCFS=y
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CONFIG_RK_MEMBLOCK_PROCFS=y
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CONFIG_ROCKCHIP_DEBUG=y
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CONFIG_ROCKCHIP_OPP=y
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CONFIG_ROCKCHIP_RGA_PROC_FS=y
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CONFIG_ROCKCHIP_VENDOR_STORAGE=y
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6
arch/arm/configs/rv1126b-pm.config
Normal file
6
arch/arm/configs/rv1126b-pm.config
Normal file
@@ -0,0 +1,6 @@
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CONFIG_PM_DEBUG=y
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CONFIG_PM_SLEEP=y
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CONFIG_PM_SLEEP_DEBUG=y
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CONFIG_PM_WAKELOCKS=y
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CONFIG_SUSPEND=y
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CONFIG_ROCKCHIP_SUSPEND_MODE=y
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5
arch/arm/configs/rv1126b-wakeup.config
Normal file
5
arch/arm/configs/rv1126b-wakeup.config
Normal file
@@ -0,0 +1,5 @@
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CONFIG_INPUT=y
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CONFIG_INPUT_EVDEV=y
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CONFIG_INPUT_KEYBOARD=y
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CONFIG_KEYBOARD_GPIO=y
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CONFIG_SND_JACK_INPUT_DEV=y
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@@ -125,6 +125,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y
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CONFIG_MEDIA_PLATFORM_SUPPORT=y
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CONFIG_V4L_PLATFORM_DRIVERS=y
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CONFIG_VIDEO_ROCKCHIP_AIISP=m
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CONFIG_VIDEO_ROCKCHIP_AVSP=m
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CONFIG_VIDEO_ROCKCHIP_CIF=m
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CONFIG_VIDEO_ROCKCHIP_ISP=m
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CONFIG_VIDEO_ROCKCHIP_VPSS=m
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@@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3358-evb-ddr3-v10-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3358m-automotive-ddr3-v11-linux.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3358m-automotive-ddr3-v11-linux-tb.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3358m-vehicle-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
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@@ -365,6 +366,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v11.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-bt-sco.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-dual-4k.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb1-v10-spi-nor.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-mcu-k350c4516t.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rv1126b-evb2-v10-rgb-Q7050ITH2641AA1T.dtb
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@@ -0,0 +1,59 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "rk3358m-automotive-ddr3-v11-linux.dts"
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/ {
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model = "Rockchip RK3358M AUTOMOTIVE DDR3 V11 Linux TB board";
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compatible = "rockchip,rk3358m-automotive-ddr3-v11-linux", "rockchip,px30", "rockchip,rk3358";
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 skip_initramfs root=/dev/rd0 rootfstype=squashfs init=/sbin/init";
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};
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|
||||
/*
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* This memory mapping range represents a 512MB memory space
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* starting from the physical address 0x00000000
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* where:
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* 0x00000000 - base address
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* 0x0 - address cells
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* 0x0 - size cells
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* 0x20000000 - memory size (512MB)
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* Note: The actual available memory size depends on the hardware design
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* and may differ from the 512MB defined here.
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* Adjustment is needed based on the specific hardware memory configuration.
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*/
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memory: memory {
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device_type = "memory";
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reg = <0x00000000 0x0 0x0 0x20000000>;
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};
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ramdisk: ramdisk {
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compatible = "rockchip,ramdisk";
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memory-region = <&ramdisk_r>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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atf: atf@0 {
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reg = <0x0 0x00000 0x0 0x200000>;
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no-map;
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};
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mmc_dma_buf@200000 {
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reg = <0x0 0x200000 0x0 0x200000>;
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};
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ramdisk_r: ramdisk_r@4000000 {
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/* Do not exceed 132MB which used by TEE */
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reg = <0x0 0x4000000 0x0 0x2000000>;
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};
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};
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};
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@@ -10,51 +10,6 @@
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#include "rk3358-linux.dtsi"
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/ {
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model = "Rockchip RK3358M AUTOMOTIVE DDR3 V11 board";
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model = "Rockchip RK3358M AUTOMOTIVE DDR3 V11 Linux board";
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compatible = "rockchip,rk3358m-automotive-ddr3-v11-linux", "rockchip,px30", "rockchip,rk3358";
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 skip_initramfs root=/dev/rd0 rootfstype=squashfs init=/sbin/init";
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};
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||||
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||||
/*
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* This memory mapping range represents a 512MB memory space
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||||
* starting from the physical address 0x00000000
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||||
* where:
|
||||
* 0x00000000 - base address
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||||
* 0x0 - address cells
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||||
* 0x0 - size cells
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||||
* 0x20000000 - memory size (512MB)
|
||||
* Note: The actual available memory size depends on the hardware design
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||||
* and may differ from the 512MB defined here.
|
||||
* Adjustment is needed based on the specific hardware memory configuration.
|
||||
*/
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||||
memory: memory {
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device_type = "memory";
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||||
reg = <0x00000000 0x0 0x0 0x20000000>;
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||||
};
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||||
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ramdisk: ramdisk {
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compatible = "rockchip,ramdisk";
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memory-region = <&ramdisk_r>;
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};
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||||
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||||
reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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atf: atf@0 {
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reg = <0x0 0x00000 0x0 0x200000>;
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no-map;
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};
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||||
mmc_dma_buf@200000 {
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reg = <0x0 0x200000 0x0 0x200000>;
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};
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||||
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ramdisk_r: ramdisk_r@4000000 {
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/* Do not exceed 132MB which used by TEE */
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reg = <0x0 0x4000000 0x0 0x2000000>;
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};
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};
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};
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@@ -201,6 +201,8 @@
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snps,reset-gpio = <&gpio2 12 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 50000 50000>;
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pinctrl-names = "default";
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pinctrl-0 = <&rmii_pins_fixed &mac_refclk_12ma>;
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status = "okay";
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};
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@@ -422,6 +424,7 @@
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};
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||||
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vcc1v8_ser: LDO_REG8 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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@@ -434,6 +437,7 @@
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};
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vdd1v2_ser: LDO_REG9 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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@@ -553,6 +557,21 @@
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};
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&pinctrl {
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gmac {
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rmii_pins_fixed: rmii-pins-fixed {
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rockchip,pins =
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<2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
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<2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
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<2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
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<2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
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<2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
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//<2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
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<2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
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<2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
|
||||
<2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
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};
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||||
};
|
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|
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lcd {
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lcd0_pwren: lcd0-pwren {
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rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_output_high>;
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@@ -90,7 +90,7 @@
|
||||
};
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||||
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||||
&route_edp {
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status = "disabled";
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status = "okay";
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||||
connect = <&vp0_out_edp>;
|
||||
};
|
||||
|
||||
|
||||
@@ -46,7 +46,7 @@
|
||||
};
|
||||
|
||||
csi_dphy_input5: endpoint@6 {
|
||||
reg = <5>;
|
||||
reg = <6>;
|
||||
remote-endpoint = <&gc8613_out>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
|
||||
15
arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10-dual-4k.dts
Normal file
15
arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10-dual-4k.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rv1126b.dtsi"
|
||||
#include "rv1126b-evb.dtsi"
|
||||
#include "rv1126b-evb-dual-cam-4k.dtsi"
|
||||
#include "rv1126b-evb1-v10.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RV1126B EVB1 V10 DUAL 4K Board";
|
||||
compatible = "rockchip,rv1126b-evb1-v10-dual-4k", "rockchip,rv1126b";
|
||||
};
|
||||
25
arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10-spi-nor.dts
Normal file
25
arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10-spi-nor.dts
Normal file
@@ -0,0 +1,25 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rv1126b-evb1-v10.dts"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RV1126B EVB1 V10 Board";
|
||||
compatible = "rockchip,rv1126b-evb1-v10-spi-nor", "rockchip,rv1126b";
|
||||
|
||||
};
|
||||
|
||||
&fspi0 {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <75000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <1>;
|
||||
};
|
||||
};
|
||||
@@ -7,484 +7,9 @@
|
||||
#include "rv1126b.dtsi"
|
||||
#include "rv1126b-evb.dtsi"
|
||||
#include "rv1126b-evb-cam-csi0.dtsi"
|
||||
#include "rv1126b-evb1-v10.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RV1126B EVB1 V10 Board";
|
||||
compatible = "rockchip,rv1126b-evb1-v10", "rockchip,rv1126b";
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card populated):
|
||||
* - SDIO_RESET_L_WL_REG_ON
|
||||
* - PDN (power down when low)
|
||||
*/
|
||||
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
vbus5v0_typec: vbus5v0-typec {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbus5v0_typec";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio5 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&typec5v_pwren>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio5 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
};
|
||||
|
||||
vcc_mipi: vcc-mipi {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_mipi";
|
||||
gpio = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_sd: vcc-sd {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-low;
|
||||
regulator-boot-on; // The legacy U-Boot GPIO driver needs this to set correct SDMMC0_PWREN value
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vccio_sd: vccio-sd {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-boot-on;
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_volt>;
|
||||
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
states = <1800000 0x0
|
||||
3300000 0x1>;
|
||||
};
|
||||
|
||||
vdd_npu: vdd-npu {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm0_8ch_0 0 25000 1>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <950000>;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
pwm-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
compatible = "bluetooth-platdata";
|
||||
uart_rts_gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default", "rts_gpio";
|
||||
pinctrl-0 = <&uart2m0_rtsn_pins>;
|
||||
pinctrl-1 = <&uart2_gpios>;
|
||||
BT,power_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
compatible = "wlan-platdata";
|
||||
rockchip,grf = <&grf>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_wake_host>;
|
||||
wifi_chip_type = "rk96x";
|
||||
WIFI,host_wake_irq = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&acdcdig_dsm {
|
||||
status = "okay";
|
||||
pa-ctl-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&acodec_sound {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&audio_codec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&backlight {
|
||||
pwms = <&pwm2_8ch_4 0 25000 0>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&display_subsystem {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi_in_vop {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi_panel {
|
||||
power-supply = <&vcc_mipi>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
non-removable;
|
||||
mmc-hs200-1_8v;
|
||||
rockchip,default-sample-phase = <90>;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fspi0 {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spi-nand";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <75000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac {
|
||||
phy-mode = "rmii";
|
||||
clock_in_out = "input";
|
||||
phy-handle = <&rmii_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rk801: rk801@27 {
|
||||
compatible = "rockchip,rk801";
|
||||
status = "okay";
|
||||
reg = <0x27>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PC0 IRQ_TYPE_LEVEL_LOW>;
|
||||
pwrctrl-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc12v_dcin>;
|
||||
vcc2-supply = <&vcc12v_dcin>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_cpu: DCDC_REG1 {
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-initial-mode = <0x1>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-mode = <0x2>;
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sys: DCDC_REG2 {
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-initial-mode = <0x1>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-mode = <0x2>;
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-mode = <0x2>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_logic: DCDC_REG4 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-initial-mode = <0x1>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-mode = <0x2>;
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd0v9_sys: LDO_REG1 {
|
||||
regulator-name = "vdd0v9_sys";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: LDO_REG2 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4m3_pins>;
|
||||
|
||||
gt1x: gt1x@14 {
|
||||
compatible = "goodix,gt1x";
|
||||
reg = <0x14>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&touch_gpio>;
|
||||
power-supply = <&vcc_mipi>;
|
||||
goodix,rst-gpio = <&gpio7 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
goodix,irq-gpio = <&gpio7 RK_PA6 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
rmii_phy: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-id0680.8101", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <2>;
|
||||
clocks = <&cru CLK_MACPHY>;
|
||||
clock-frequency = <50000000>;
|
||||
resets = <&cru SRST_RESETN_MACPHY>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&fephym1_pins>;
|
||||
phy-is-integrated;
|
||||
};
|
||||
};
|
||||
|
||||
&mipi_dphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pmic {
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
/omit-if-no-ref/
|
||||
sdmmc_volt: sdmmc-volt {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
touch {
|
||||
touch_gpio: touch-gpio {
|
||||
rockchip,pins =
|
||||
<7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
typec5v_pwren: typec5v-pwren {
|
||||
rockchip,pins = <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <5 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
uart2_gpios: uart2-gpios {
|
||||
rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
wifi_wake_host: wifi-wake-host {
|
||||
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0_8ch_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2_8ch_4 {
|
||||
pinctrl-0 = <&pwm2m1_ch4_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkaiisp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkaiisp_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkaiisp_vir0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkfec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkfec_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rknpu {
|
||||
rknpu-supply = <&vdd_npu>;
|
||||
};
|
||||
|
||||
&route_dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
status = "okay";
|
||||
/delete-property/ pinctrl-names;
|
||||
/delete-property/ pinctrl-0;
|
||||
};
|
||||
|
||||
&saradc0 {
|
||||
vref-supply = <&vcc_1v8>;
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
max-frequency = <200000000>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
no-sd;
|
||||
no-mmc;
|
||||
max-frequency = <200000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_clk_pins &sdmmc1_cmd_pins &sdmmc1_bus4_pins>;
|
||||
keep-power-in-suspend;
|
||||
non-removable;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
//sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2m0_xfer_pins &uart2m0_ctsn_pins>;
|
||||
};
|
||||
|
||||
&usb2phy_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
};
|
||||
|
||||
&usb2phy_otg {
|
||||
vbus-supply = <&vbus5v0_typec>;
|
||||
};
|
||||
|
||||
&usb_drd_dwc3 {
|
||||
dr_mode = "otg";
|
||||
extcon = <&usb2phy>;
|
||||
};
|
||||
|
||||
491
arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10.dtsi
Normal file
491
arch/arm64/boot/dts/rockchip/rv1126b-evb1-v10.dtsi
Normal file
@@ -0,0 +1,491 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card populated):
|
||||
* - SDIO_RESET_L_WL_REG_ON
|
||||
* - PDN (power down when low)
|
||||
*/
|
||||
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
vbus5v0_typec: vbus5v0-typec {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbus5v0_typec";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio5 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&typec5v_pwren>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio5 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
};
|
||||
|
||||
vcc_mipi: vcc-mipi {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_mipi";
|
||||
gpio = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_sd: vcc-sd {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-low;
|
||||
regulator-boot-on; // The legacy U-Boot GPIO driver needs this to set correct SDMMC0_PWREN value
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vccio_sd: vccio-sd {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-boot-on;
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_volt>;
|
||||
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
states = <1800000 0x0
|
||||
3300000 0x1>;
|
||||
};
|
||||
|
||||
vdd_npu: vdd-npu {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm0_8ch_0 0 25000 1>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <950000>;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
pwm-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
compatible = "bluetooth-platdata";
|
||||
uart_rts_gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default", "rts_gpio";
|
||||
pinctrl-0 = <&uart2m0_rtsn_pins>;
|
||||
pinctrl-1 = <&uart2_gpios>;
|
||||
BT,power_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
compatible = "wlan-platdata";
|
||||
rockchip,grf = <&grf>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_wake_host>;
|
||||
wifi_chip_type = "rk96x";
|
||||
WIFI,host_wake_irq = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&acdcdig_dsm {
|
||||
status = "okay";
|
||||
pa-ctl-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&acodec_sound {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&audio_codec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&backlight {
|
||||
pwms = <&pwm2_8ch_4 0 25000 0>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&display_subsystem {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi_in_vop {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi_panel {
|
||||
power-supply = <&vcc_mipi>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
non-removable;
|
||||
mmc-hs200-1_8v;
|
||||
rockchip,default-sample-phase = <90>;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fspi0 {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spi-nand";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <75000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac {
|
||||
phy-mode = "rmii";
|
||||
clock_in_out = "input";
|
||||
phy-handle = <&rmii_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rk801: rk801@27 {
|
||||
compatible = "rockchip,rk801";
|
||||
status = "okay";
|
||||
reg = <0x27>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PC0 IRQ_TYPE_LEVEL_LOW>;
|
||||
pwrctrl-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc12v_dcin>;
|
||||
vcc2-supply = <&vcc12v_dcin>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_cpu: DCDC_REG1 {
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-initial-mode = <0x1>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-mode = <0x2>;
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sys: DCDC_REG2 {
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-initial-mode = <0x1>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-mode = <0x2>;
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-mode = <0x2>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_logic: DCDC_REG4 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-initial-mode = <0x1>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-mode = <0x2>;
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd0v9_sys: LDO_REG1 {
|
||||
regulator-name = "vdd0v9_sys";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: LDO_REG2 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4m3_pins>;
|
||||
|
||||
gt1x: gt1x@14 {
|
||||
compatible = "goodix,gt1x";
|
||||
reg = <0x14>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&touch_gpio>;
|
||||
power-supply = <&vcc_mipi>;
|
||||
goodix,rst-gpio = <&gpio7 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
goodix,irq-gpio = <&gpio7 RK_PA6 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
rmii_phy: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-id0680.8101", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <2>;
|
||||
clocks = <&cru CLK_MACPHY>;
|
||||
clock-frequency = <50000000>;
|
||||
resets = <&cru SRST_RESETN_MACPHY>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&fephym1_pins>;
|
||||
phy-is-integrated;
|
||||
};
|
||||
};
|
||||
|
||||
&mipi_dphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pmic {
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
/omit-if-no-ref/
|
||||
sdmmc_volt: sdmmc-volt {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
touch {
|
||||
touch_gpio: touch-gpio {
|
||||
rockchip,pins =
|
||||
<7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
typec5v_pwren: typec5v-pwren {
|
||||
rockchip,pins = <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <5 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
uart2_gpios: uart2-gpios {
|
||||
rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
wifi_wake_host: wifi-wake-host {
|
||||
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0_8ch_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2_8ch_4 {
|
||||
pinctrl-0 = <&pwm2m1_ch4_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkaiisp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkaiisp_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkaiisp_vir0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkavsp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkavsp_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkfec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkfec_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rknpu {
|
||||
rknpu-supply = <&vdd_npu>;
|
||||
};
|
||||
|
||||
&route_dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
status = "okay";
|
||||
/delete-property/ pinctrl-names;
|
||||
/delete-property/ pinctrl-0;
|
||||
};
|
||||
|
||||
&saradc0 {
|
||||
vref-supply = <&vcc_1v8>;
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
max-frequency = <200000000>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
no-sd;
|
||||
no-mmc;
|
||||
max-frequency = <200000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_clk_pins &sdmmc1_cmd_pins &sdmmc1_bus4_pins>;
|
||||
keep-power-in-suspend;
|
||||
non-removable;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
//sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2m0_xfer_pins &uart2m0_ctsn_pins>;
|
||||
};
|
||||
|
||||
&usb2phy_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
};
|
||||
|
||||
&usb2phy_otg {
|
||||
vbus-supply = <&vbus5v0_typec>;
|
||||
};
|
||||
|
||||
&usb_drd_dwc3 {
|
||||
dr_mode = "otg";
|
||||
extcon = <&usb2phy>;
|
||||
};
|
||||
@@ -12,6 +12,21 @@
|
||||
model = "Rockchip RV1126B EVB2 V10 Board";
|
||||
compatible = "rockchip,rv1126b-evb2-v10", "rockchip,rv1126b";
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwr_key>;
|
||||
power-key {
|
||||
gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
label ="GPIO Key Power";
|
||||
debounce-interval = <100>;
|
||||
wakeup-source;
|
||||
/* gpio-key,wakeup; */
|
||||
};
|
||||
};
|
||||
|
||||
vcc5v0_dcin: vcc5v0-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_dcin";
|
||||
@@ -203,6 +218,26 @@
|
||||
pwm-supply = <&vccsys_stb>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
compatible = "bluetooth-platdata";
|
||||
uart_rts_gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default", "rts_gpio";
|
||||
pinctrl-0 = <&uart2m0_rtsn_pins>;
|
||||
pinctrl-1 = <&uart2_gpios>;
|
||||
BT,power_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
compatible = "wlan-platdata";
|
||||
rockchip,grf = <&grf>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_wake_host>;
|
||||
wifi_chip_type = "rk96x";
|
||||
WIFI,host_wake_irq = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&acdcdig_dsm {
|
||||
@@ -296,6 +331,12 @@
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
buttons {
|
||||
pwr_key: pwr-key {
|
||||
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
/omit-if-no-ref/
|
||||
sdmmc_volt: sdmmc-volt {
|
||||
@@ -316,6 +357,18 @@
|
||||
rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
uart2_gpios: uart2-gpios {
|
||||
rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
wifi_wake_host: wifi-wake-host {
|
||||
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0_8ch_0 {
|
||||
@@ -350,10 +403,28 @@
|
||||
rknpu-supply = <&vdd_npu>;
|
||||
};
|
||||
|
||||
&rockchip_suspend {
|
||||
status = "okay";
|
||||
|
||||
rockchip,sleep-pin-config = <
|
||||
(0
|
||||
| RKPM_SLEEP_PIN0_EN
|
||||
)
|
||||
(0
|
||||
| RKPM_SLEEP_PIN0_ACT_LOW
|
||||
)
|
||||
>;
|
||||
};
|
||||
|
||||
&route_dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
rockchip,rtc-suspend-bypass;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
rockchip,sai-rx-route = <1 0 2 3>;
|
||||
status = "okay";
|
||||
@@ -387,6 +458,27 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
bus-width = <1>;
|
||||
cap-sd-highspeed;
|
||||
no-sd;
|
||||
no-mmc;
|
||||
max-frequency = <200000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_clk_pins &sdmmc1_cmd_pins &sdmmc1_bus4_pins>;
|
||||
keep-power-in-suspend;
|
||||
non-removable;
|
||||
//mmc-pwrseq = <&sdio_pwrseq>;
|
||||
//sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2m0_xfer_pins &uart2m0_ctsn_pins>;
|
||||
};
|
||||
|
||||
&usb2phy_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
};
|
||||
|
||||
@@ -11,6 +11,20 @@
|
||||
model = "Rockchip RV1126B EVB3 V10 Board";
|
||||
compatible = "rockchip,rv1126b-evb3-v10", "rockchip,rv1126b";
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card populated):
|
||||
* - SDIO_RESET_L_WL_REG_ON
|
||||
* - PDN (power down when low)
|
||||
*/
|
||||
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vcc5v0_dcin: vcc5v0-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_dcin";
|
||||
@@ -95,6 +109,14 @@
|
||||
vin-supply = <&vcc1v8_pmu>;
|
||||
};
|
||||
|
||||
vcc_mipi: vcc-mipi {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_mipi";
|
||||
gpio = <&gpio7 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_1v8: vcc-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v8";
|
||||
@@ -115,6 +137,28 @@
|
||||
vin-supply = <&vccsys_stb>;
|
||||
};
|
||||
|
||||
vcc_sd: vcc-sd {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio7 RK_PA2 GPIO_ACTIVE_LOW>;
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-low;
|
||||
vin-supply = <&vcc_3v3>;
|
||||
};
|
||||
|
||||
vccio_sd: vccio-sd {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-boot-on;
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&gpio7 RK_PA3 GPIO_ACTIVE_LOW>;
|
||||
vin-supply = <&vccsys_stb>;
|
||||
states = <1800000 0x0
|
||||
3300000 0x1>;
|
||||
};
|
||||
|
||||
vdd_log: vdd-log {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm1_4ch_2 0 25000 1>;
|
||||
@@ -144,7 +188,7 @@
|
||||
vdd_npu: vdd-npu {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm1_4ch_1 0 25000 1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <950000>;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
@@ -153,12 +197,52 @@
|
||||
pwm-supply = <&vccsys_stb>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
compatible = "bluetooth-platdata";
|
||||
uart_rts_gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default", "rts_gpio";
|
||||
pinctrl-0 = <&uart2m0_rtsn_pins>;
|
||||
pinctrl-1 = <&uart2_gpios>;
|
||||
BT,power_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
compatible = "wlan-platdata";
|
||||
rockchip,grf = <&grf>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_wake_host>;
|
||||
wifi_chip_type = "rk96x";
|
||||
WIFI,host_wake_irq = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&backlight {
|
||||
pwms = <&pwm2_8ch_7 0 25000 0>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&display_subsystem {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi_in_vop {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi_panel {
|
||||
power-supply = <&vcc_mipi>;
|
||||
};
|
||||
|
||||
&fspi0 {
|
||||
status = "okay";
|
||||
|
||||
@@ -171,6 +255,26 @@
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4m3_pins>;
|
||||
|
||||
gt1x: gt1x@14 {
|
||||
compatible = "goodix,gt1x";
|
||||
reg = <0x14>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&touch_gpio>;
|
||||
power-supply = <&vcc_mipi>;
|
||||
goodix,rst-gpio = <&gpio5 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
goodix,irq-gpio = <&gpio3 RK_PB7 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&mipi_dphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkaiisp {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -187,12 +291,42 @@
|
||||
rknpu-supply = <&vdd_npu>;
|
||||
};
|
||||
|
||||
&route_dsi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
touch {
|
||||
touch_gpio: touch-gpio {
|
||||
rockchip,pins =
|
||||
<3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
|
||||
<5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <7 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
uart2_gpios: uart2-gpios {
|
||||
rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
wifi_wake_host: wifi-wake-host {
|
||||
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1_4ch_0 {
|
||||
@@ -210,6 +344,34 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2_8ch_7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc0 {
|
||||
vref-supply = <&vcc_1v8>;
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
max-frequency = <200000000>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2m0_xfer_pins &uart2m0_ctsn_pins>;
|
||||
};
|
||||
|
||||
&usb2phy_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
};
|
||||
|
||||
@@ -12,6 +12,20 @@
|
||||
model = "Rockchip RV1126B EVB4 V10 Board";
|
||||
compatible = "rockchip,rv1126b-evb4-v10", "rockchip,rv1126b";
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card populated):
|
||||
* - SDIO_RESET_L_WL_REG_ON
|
||||
* - PDN (power down when low)
|
||||
*/
|
||||
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vcc_mipi: vcc-mipi {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_mipi";
|
||||
@@ -69,6 +83,26 @@
|
||||
enable-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
pwm-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
compatible = "bluetooth-platdata";
|
||||
uart_rts_gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default", "rts_gpio";
|
||||
pinctrl-0 = <&uart2m0_rtsn_pins>;
|
||||
pinctrl-1 = <&uart2_gpios>;
|
||||
BT,power_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
compatible = "wlan-platdata";
|
||||
rockchip,grf = <&grf>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_wake_host>;
|
||||
wifi_chip_type = "rk96x";
|
||||
WIFI,host_wake_irq = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&backlight {
|
||||
@@ -243,6 +277,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
typec5v_pwren: typec5v-pwren {
|
||||
rockchip,pins = <5 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
@@ -252,6 +292,18 @@
|
||||
rockchip,pins = <6 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
uart2_gpios: uart2-gpios {
|
||||
rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
wifi_wake_host: wifi-wake-host {
|
||||
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0_8ch_0 {
|
||||
@@ -270,6 +322,27 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
no-sd;
|
||||
no-mmc;
|
||||
max-frequency = <200000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_clk_pins &sdmmc1_cmd_pins &sdmmc1_bus4_pins>;
|
||||
keep-power-in-suspend;
|
||||
non-removable;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
//sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2m0_xfer_pins &uart2m0_ctsn_pins>;
|
||||
};
|
||||
|
||||
&usb2phy_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
};
|
||||
|
||||
@@ -12,6 +12,7 @@
|
||||
#include <dt-bindings/power/rockchip,rv1126b-power.h>
|
||||
#include <dt-bindings/soc/rockchip,boot-mode.h>
|
||||
#include <dt-bindings/soc/rockchip-system-status.h>
|
||||
#include <dt-bindings/suspend/rockchip-rv1126b.h>
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rv1126b";
|
||||
@@ -214,6 +215,15 @@
|
||||
assigned-clock-rates = <550000000>;
|
||||
};
|
||||
|
||||
pvtpll_aisp: pvtpll-aisp@21fc0000 {
|
||||
compatible = "rockchip,rv1126b-aisp-pvtpll";
|
||||
reg = <0x21fc0000 0x100>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "clk_vcp_pvtpll";
|
||||
assigned-clocks = <&pvtpll_aisp>;
|
||||
assigned-clock-rates = <775000000>;
|
||||
};
|
||||
|
||||
pvtpll_npu: pvtpll-npu@22080000 {
|
||||
compatible = "rockchip,rv1126b-npu-pvtpll", "syscon";
|
||||
reg = <0x22080000 0x100>;
|
||||
@@ -393,7 +403,7 @@
|
||||
compatible = "rockchip,fiq-debugger";
|
||||
rockchip,serial-id = <0>;
|
||||
rockchip,wake-irq = <0>;
|
||||
rockchip,irq-mode-enable = <0>;
|
||||
rockchip,irq-mode-enable = <1>;
|
||||
rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
|
||||
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
@@ -749,6 +759,25 @@
|
||||
};
|
||||
};
|
||||
|
||||
rockchip_suspend: rockchip-suspend {
|
||||
compatible = "rockchip,pm-config";
|
||||
status = "disabled";
|
||||
|
||||
rockchip,sleep-mode-config = <
|
||||
(0
|
||||
| RKPM_SLP_ARMOFF_PMUOFF
|
||||
| RKPM_SLP_PMU_PMUALIVE_32K
|
||||
| RKPM_SLP_PMU_DIS_OSC
|
||||
| RKPM_SLP_32K_EXT
|
||||
)
|
||||
>;
|
||||
rockchip,wakeup-config = <
|
||||
(0
|
||||
| RKPM_GPIO0_WKUP_EN
|
||||
)
|
||||
>;
|
||||
};
|
||||
|
||||
rockchip_system_monitor: rockchip-system-monitor {
|
||||
compatible = "rockchip,system-monitor";
|
||||
};
|
||||
|
||||
@@ -22,7 +22,6 @@ CONFIG_CPU_IDLE_GOV_TEO=y
|
||||
# CONFIG_CPU_RK3528 is not set
|
||||
# CONFIG_CPU_RK3562 is not set
|
||||
# CONFIG_CPU_RK3568 is not set
|
||||
# CONFIG_CRYPTO_DEV_ROCKCHIP_V1 is not set
|
||||
# CONFIG_CRYPTO_DEV_ROCKCHIP_V3 is not set
|
||||
# CONFIG_DRM_MAXIM_MAX96745 is not set
|
||||
# CONFIG_DRM_MAXIM_MAX96755F is not set
|
||||
@@ -34,13 +33,15 @@ CONFIG_GPIO_NCA9539=y
|
||||
# CONFIG_HALL_DEVICE is not set
|
||||
CONFIG_HZ=1000
|
||||
CONFIG_HZ_1000=y
|
||||
# CONFIG_HZ_300 is not set
|
||||
# CONFIG_HZ_250 is not set
|
||||
# CONFIG_IIO_ST_LSM6DSR is not set
|
||||
# CONFIG_INPUT_TABLET is not set
|
||||
# CONFIG_LIGHT_DEVICE is not set
|
||||
CONFIG_LOG_BUF_SHIFT=20
|
||||
# CONFIG_MALI400 is not set
|
||||
# CONFIG_MALI_MIDGARD is not set
|
||||
# CONFIG_MFD_MAX96745 is not set
|
||||
# CONFIG_MFD_MAX96755F is not set
|
||||
# CONFIG_MFD_RK618 is not set
|
||||
# CONFIG_MFD_RK630_I2C is not set
|
||||
# CONFIG_MFD_RKX110_X120 is not set
|
||||
@@ -56,15 +57,9 @@ CONFIG_REALTEK_PHY=y
|
||||
# CONFIG_REGULATOR_WL2868C is not set
|
||||
# CONFIG_REGULATOR_XZ3216 is not set
|
||||
# CONFIG_ROCKCHIP_CHARGER_MANAGER is not set
|
||||
# CONFIG_ROCKCHIP_CLK_BOOST is not set
|
||||
# CONFIG_ROCKCHIP_CLK_INV is not set
|
||||
# CONFIG_ROCKCHIP_CLK_PVTM is not set
|
||||
# CONFIG_ROCKCHIP_DDRCLK_SIP is not set
|
||||
# CONFIG_ROCKCHIP_DDRCLK_SIP_V2 is not set
|
||||
CONFIG_ROCKCHIP_DRM_DIRECT_SHOW=y
|
||||
# CONFIG_ROCKCHIP_PLL_RK3066 is not set
|
||||
# CONFIG_ROCKCHIP_PLL_RK3399 is not set
|
||||
# CONFIG_ROCKCHIP_SERDES_DRM_PANEL is not set
|
||||
CONFIG_RTC_DRV_S35390A=y
|
||||
# CONFIG_SLUB_SYSFS is not set
|
||||
# CONFIG_SND_SOC_AW883XX is not set
|
||||
@@ -118,9 +113,6 @@ CONFIG_VIDEO_MAXIM_SERDES=y
|
||||
# CONFIG_VIDEO_RK628_BT1120 is not set
|
||||
# CONFIG_VIDEO_RK628_CSI is not set
|
||||
# CONFIG_VIDEO_RK_IRCUT is not set
|
||||
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V1X is not set
|
||||
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21 is not set
|
||||
# CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32 is not set
|
||||
# CONFIG_VIDEO_S5K3L6XX is not set
|
||||
# CONFIG_VIDEO_S5KJN1 is not set
|
||||
# CONFIG_VIDEO_SGM3784 is not set
|
||||
@@ -141,10 +133,10 @@ CONFIG_SERDES_DISPLAY_CHIP_ROHM=y
|
||||
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18RL82=y
|
||||
CONFIG_SERDES_DISPLAY_CHIP_ROHM_BU18TL82=y
|
||||
CONFIG_VIDEO_MAXIM_CAM_DUMMY=y
|
||||
CONFIG_VIDEO_MAXIM_CAM_OS04A10=y
|
||||
CONFIG_VIDEO_MAXIM_CAM_OV231X=y
|
||||
CONFIG_VIDEO_MAXIM_CAM_OX01F10=y
|
||||
CONFIG_VIDEO_MAXIM_CAM_OX03J10=y
|
||||
CONFIG_VIDEO_MAXIM_CAM_OS04A10=y
|
||||
CONFIG_VIDEO_MAXIM_CAM_SC320AT=y
|
||||
# CONFIG_VIDEO_MAXIM_DES_MAXIM2C is not set
|
||||
CONFIG_VIDEO_MAXIM_DES_MAXIM4C=y
|
||||
|
||||
@@ -117,7 +117,9 @@ CONFIG_IP_NF_MANGLE=y
|
||||
CONFIG_CAN=y
|
||||
CONFIG_BT=y
|
||||
CONFIG_BT_RFCOMM=y
|
||||
CONFIG_BT_RFCOMM_TTY=y
|
||||
CONFIG_BT_HIDP=y
|
||||
CONFIG_BT_HS=y
|
||||
CONFIG_BT_HCIBTUSB=y
|
||||
CONFIG_BT_HCIUART=y
|
||||
CONFIG_BT_HCIUART_ATH3K=y
|
||||
@@ -205,6 +207,7 @@ CONFIG_R8168=y
|
||||
# CONFIG_NET_VENDOR_SIS is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
# CONFIG_DWMAC_GENERIC is not set
|
||||
# CONFIG_NET_VENDOR_SUN is not set
|
||||
# CONFIG_NET_VENDOR_SYNOPSYS is not set
|
||||
# CONFIG_NET_VENDOR_TEHUTI is not set
|
||||
@@ -212,6 +215,7 @@ CONFIG_STMMAC_ETH=y
|
||||
# CONFIG_NET_VENDOR_VIA is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
CONFIG_MOTORCOMM_PHY=y
|
||||
CONFIG_ROCKCHIP_FEPHY=y
|
||||
CONFIG_ROCKCHIP_PHY=y
|
||||
CONFIG_RK630_PHY=y
|
||||
CONFIG_CANFD_RK3576=y
|
||||
@@ -305,6 +309,7 @@ CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_LP8752=y
|
||||
CONFIG_REGULATOR_MP8865=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_RK801=y
|
||||
CONFIG_REGULATOR_RK806=y
|
||||
CONFIG_REGULATOR_RK808=y
|
||||
CONFIG_REGULATOR_RK860X=y
|
||||
@@ -317,6 +322,7 @@ CONFIG_USB_VIDEO_CLASS=y
|
||||
# CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set
|
||||
CONFIG_V4L_PLATFORM_DRIVERS=y
|
||||
CONFIG_V4L_MEM2MEM_DRIVERS=y
|
||||
CONFIG_VIDEO_ROCKCHIP_AIISP=y
|
||||
CONFIG_VIDEO_ROCKCHIP_CIF=y
|
||||
CONFIG_VIDEO_ROCKCHIP_RKISP1=y
|
||||
CONFIG_VIDEO_ROCKCHIP_ISP=y
|
||||
@@ -334,7 +340,10 @@ CONFIG_VIDEO_OV4689=y
|
||||
CONFIG_VIDEO_OV50C40=y
|
||||
CONFIG_VIDEO_OV5695=y
|
||||
CONFIG_VIDEO_OV7251=y
|
||||
CONFIG_VIDEO_SC200AI=y
|
||||
CONFIG_VIDEO_SC4336=y
|
||||
CONFIG_VIDEO_SC450AI=y
|
||||
CONFIG_VIDEO_SC850SL=y
|
||||
CONFIG_VIDEO_LT6911UXC=y
|
||||
CONFIG_VIDEO_LT6911UXE=y
|
||||
CONFIG_VIDEO_LT7911D=y
|
||||
@@ -396,6 +405,7 @@ CONFIG_ROCKCHIP_MPP_IEP2=y
|
||||
CONFIG_ROCKCHIP_MPP_JPGDEC=y
|
||||
CONFIG_ROCKCHIP_MPP_JPGENC=y
|
||||
CONFIG_ROCKCHIP_MPP_AV1DEC=y
|
||||
CONFIG_ROCKCHIP_MPP_OSAL=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_HRTIMER=y
|
||||
@@ -430,6 +440,7 @@ CONFIG_SND_SOC_ES8323=y
|
||||
CONFIG_SND_SOC_ES8326=y
|
||||
CONFIG_SND_SOC_RK3308=y
|
||||
CONFIG_SND_SOC_RK3328=y
|
||||
CONFIG_SND_SOC_RK3506=y
|
||||
CONFIG_SND_SOC_RK3528=y
|
||||
CONFIG_SND_SOC_RK817=y
|
||||
CONFIG_SND_SOC_RK_CODEC_DIGITAL=y
|
||||
@@ -511,22 +522,28 @@ CONFIG_RTC_DRV_HYM8563=y
|
||||
CONFIG_RTC_DRV_RK808=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_ROCKCHIP_DMA=y
|
||||
CONFIG_RK_DMABUF_DEBUG=y
|
||||
CONFIG_SW_SYNC=y
|
||||
CONFIG_DMABUF_HEAPS=y
|
||||
CONFIG_DMABUF_SYSFS_STATS=y
|
||||
CONFIG_DMABUF_HEAPS_SYSTEM=y
|
||||
CONFIG_DMABUF_HEAPS_CMA=y
|
||||
CONFIG_DMABUF_HEAPS_ROCKCHIP=y
|
||||
CONFIG_DMABUF_HEAPS_ROCKCHIP_CMA_HEAP=y
|
||||
CONFIG_DMABUF_RK_HEAPS_DEBUG=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_COMMON_CLK_RK808=y
|
||||
CONFIG_COMMON_CLK_SCMI=y
|
||||
CONFIG_COMMON_CLK_PWM=y
|
||||
CONFIG_ROCKCHIP_CLK_PVTPLL=y
|
||||
CONFIG_MAILBOX=y
|
||||
CONFIG_ROCKCHIP_MBOX=y
|
||||
CONFIG_ROCKCHIP_IOMMU=y
|
||||
CONFIG_ARM_SMMU_V3=y
|
||||
CONFIG_RPMSG_ROCKCHIP_MBOX=y
|
||||
CONFIG_RPMSG_VIRTIO=y
|
||||
CONFIG_CPU_RV1126B=y
|
||||
CONFIG_CPU_PX30=y
|
||||
CONFIG_CPU_RK1808=y
|
||||
CONFIG_CPU_RK3328=y
|
||||
@@ -558,7 +575,6 @@ CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
|
||||
CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
|
||||
CONFIG_RK_CONSOLE_THREAD=y
|
||||
CONFIG_ROCKCHIP_DEBUG=y
|
||||
CONFIG_PM_DEVFREQ=y
|
||||
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
|
||||
CONFIG_DEVFREQ_GOV_POWERSAVE=y
|
||||
CONFIG_DEVFREQ_GOV_USERSPACE=y
|
||||
|
||||
@@ -225,19 +225,6 @@ CONFIG_BACKLIGHT_PWM=y
|
||||
CONFIG_ROCKCHIP_MULTI_RGA=y
|
||||
CONFIG_ROCKCHIP_RGA_PROC_FS=y
|
||||
# CONFIG_ROCKCHIP_RGA_DEBUG_FS is not set
|
||||
CONFIG_ROCKCHIP_MPP_SERVICE=y
|
||||
CONFIG_ROCKCHIP_MPP_RKVDEC=y
|
||||
CONFIG_ROCKCHIP_MPP_RKVDEC2=y
|
||||
CONFIG_ROCKCHIP_MPP_RKVENC=y
|
||||
CONFIG_ROCKCHIP_MPP_RKVENC2=y
|
||||
CONFIG_ROCKCHIP_MPP_VDPU1=y
|
||||
CONFIG_ROCKCHIP_MPP_VEPU1=y
|
||||
CONFIG_ROCKCHIP_MPP_VDPU2=y
|
||||
CONFIG_ROCKCHIP_MPP_VEPU2=y
|
||||
CONFIG_ROCKCHIP_MPP_IEP2=y
|
||||
CONFIG_ROCKCHIP_MPP_JPGDEC=y
|
||||
CONFIG_ROCKCHIP_MPP_JPGENC=y
|
||||
CONFIG_ROCKCHIP_MPP_AV1DEC=y
|
||||
CONFIG_ROCKCHIP_MPP_OSAL=y
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
@@ -292,6 +279,7 @@ CONFIG_RTC_DRV_RK808=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_ROCKCHIP_DMA=y
|
||||
CONFIG_DMABUF_HEAPS=y
|
||||
CONFIG_DMABUF_HEAPS_SYSTEM=y
|
||||
CONFIG_DMABUF_HEAPS_ROCKCHIP=y
|
||||
CONFIG_DMABUF_HEAPS_ROCKCHIP_CMA_HEAP=y
|
||||
CONFIG_DMABUF_RK_HEAPS_DEBUG=y
|
||||
|
||||
@@ -139,6 +139,11 @@ static struct pvtpll_table rv1103b_npu_pvtpll_table[] = {
|
||||
ROCKCHIP_PVTPLL_VOLT_SEL(700000000, 1, 32, 4),
|
||||
};
|
||||
|
||||
static struct pvtpll_table rv1126b_aisp_pvtpll_table[] = {
|
||||
/* rate_hz, ring_se, length */
|
||||
ROCKCHIP_PVTPLL(775000000, 0, 28),
|
||||
};
|
||||
|
||||
static struct pvtpll_table rv1126b_core_pvtpll_table[] = {
|
||||
/* rate_hz, ring_sel, length */
|
||||
ROCKCHIP_PVTPLL_VOLT_SEL(1608000000, 0, 30, 0),
|
||||
@@ -590,6 +595,12 @@ static const struct rockchip_clock_pvtpll_info rv1103b_npu_pvtpll_data = {
|
||||
.pvtpll_calibrate = rv1103b_pvtpll_calibrate,
|
||||
};
|
||||
|
||||
static const struct rockchip_clock_pvtpll_info rv1126b_aisp_pvtpll_data = {
|
||||
.config = rv1103b_pvtpll_configs,
|
||||
.table_size = ARRAY_SIZE(rv1126b_aisp_pvtpll_table),
|
||||
.table = rv1126b_aisp_pvtpll_table,
|
||||
};
|
||||
|
||||
static const struct rockchip_clock_pvtpll_info rv1126b_core_pvtpll_data = {
|
||||
.config = rv1103b_pvtpll_configs,
|
||||
.table_size = ARRAY_SIZE(rv1126b_core_pvtpll_table),
|
||||
@@ -635,6 +646,10 @@ static const struct of_device_id rockchip_clock_pvtpll_match[] = {
|
||||
.compatible = "rockchip,rv1103b-npu-pvtpll",
|
||||
.data = (void *)&rv1103b_npu_pvtpll_data,
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rv1126b-aisp-pvtpll",
|
||||
.data = (void *)&rv1126b_aisp_pvtpll_data,
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rv1126b-core-pvtpll",
|
||||
.data = (void *)&rv1126b_core_pvtpll_data,
|
||||
@@ -719,9 +734,27 @@ static int rockchip_clock_pvtpll_remove(struct platform_device *pdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_clock_pvtpll_resume(struct device *dev)
|
||||
{
|
||||
struct rockchip_clock_pvtpll *pvtpll = dev_get_drvdata(dev);
|
||||
struct pvtpll_table *table;
|
||||
|
||||
table = rockchip_get_pvtpll_settings(pvtpll, pvtpll->cur_rate);
|
||||
if (!table)
|
||||
return 0;
|
||||
|
||||
pvtpll->info->config(pvtpll, table);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static DEFINE_SIMPLE_DEV_PM_OPS(rockchip_clock_pvtpll_pm_ops, NULL,
|
||||
rockchip_clock_pvtpll_resume);
|
||||
|
||||
static struct platform_driver rockchip_clock_pvtpll_driver = {
|
||||
.driver = {
|
||||
.name = "rockchip-clcok-pvtpll",
|
||||
.pm = pm_sleep_ptr(&rockchip_clock_pvtpll_pm_ops),
|
||||
.of_match_table = rockchip_clock_pvtpll_match,
|
||||
},
|
||||
.probe = rockchip_clock_pvtpll_probe,
|
||||
|
||||
@@ -91,6 +91,7 @@ static struct rockchip_pll_rate_table rk3576_pll_rates[] = {
|
||||
RK3588_PLL_RATE(773000000, 2, 258, 2, 43690),
|
||||
RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
|
||||
RK3588_PLL_RATE(697000000, 2, 232, 2, 21845),
|
||||
RK3588_PLL_RATE(610400000, 3, 305, 2, 13107),
|
||||
RK3588_PLL_RATE(604800000, 1, 101, 2, 52428),
|
||||
RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
|
||||
RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
|
||||
|
||||
@@ -421,7 +421,7 @@ static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = {
|
||||
COMPOSITE_NODIV(TCLK_WDT_NS_SRC, "tclk_wdt_ns_src", mux_100m_24m_p, 0,
|
||||
RV1126B_CLKSEL_CON(46), 12, 1, MFLAGS,
|
||||
RV1126B_CLKGATE_CON(8), 0, GFLAGS),
|
||||
COMPOSITE_NODIV(TCLK_WDT_S, "tclk_wdt_s", mux_100m_24m_p, 0,
|
||||
COMPOSITE_NODIV(TCLK_WDT_S_SRC, "tclk_wdt_s_src", mux_100m_24m_p, 0,
|
||||
RV1126B_CLKSEL_CON(46), 13, 1, MFLAGS,
|
||||
RV1126B_CLKGATE_CON(8), 1, GFLAGS),
|
||||
COMPOSITE_NODIV(TCLK_WDT_HPMCU, "tclk_wdt_hpmcu", mux_100m_24m_p, 0,
|
||||
@@ -459,10 +459,10 @@ static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = {
|
||||
COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_24m_p, 0,
|
||||
RV1126B_CLKSEL_CON(50), 11, 1, MFLAGS,
|
||||
RV1126B_CLKGATE_CON(9), 3, GFLAGS),
|
||||
COMPOSITE_NODIV(CLK_PKA_RKCE_SRC, "clk_pka_rkce_src", mux_300m_200m_p, 0,
|
||||
COMPOSITE_NODIV(CLK_PKA_RKCE_SRC, "clk_pka_rkce_src", mux_300m_200m_p, CLK_IS_CRITICAL,
|
||||
RV1126B_CLKSEL_CON(50), 12, 1, MFLAGS,
|
||||
RV1126B_CLKGATE_CON(9), 4, GFLAGS),
|
||||
COMPOSITE_NODIV(ACLK_RKCE_SRC, "aclk_rkce_src", mux_200m_24m_p, 0,
|
||||
COMPOSITE_NODIV(ACLK_RKCE_SRC, "aclk_rkce_src", mux_200m_24m_p, CLK_IS_CRITICAL,
|
||||
RV1126B_CLKSEL_CON(50), 13, 1, MFLAGS,
|
||||
RV1126B_CLKGATE_CON(9), 5, GFLAGS),
|
||||
COMPOSITE_NODIV(ACLK_VCP_ROOT, "aclk_vcp_root", mux_500m_400m_200m_p, CLK_IS_CRITICAL,
|
||||
@@ -865,6 +865,10 @@ static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = {
|
||||
COMPOSITE_NODIV(CLK_TIMER4, "clk_timer4", clk_timer4_parents_p, 0,
|
||||
RV1126B_BUSCLKSEL_CON(2), 8, 2, MFLAGS,
|
||||
RV1126B_BUSCLKGATE_CON(2), 10, GFLAGS),
|
||||
GATE(HCLK_RKRNG_NS, "hclk_rkrng_ns", "hclk_bus_root", 0,
|
||||
RV1126B_BUSCLKGATE_CON(2), 15, GFLAGS),
|
||||
GATE(HCLK_RKRNG_S_NS, "hclk_rkrng_s_ns", "hclk_bus_root", 0,
|
||||
RV1126B_BUSCLKGATE_CON(2), 14, GFLAGS),
|
||||
GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
|
||||
RV1126B_BUSCLKGATE_CON(2), 11, GFLAGS),
|
||||
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_root", 0,
|
||||
@@ -948,7 +952,7 @@ static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = {
|
||||
GATE(MCLK_AUDIO_ADC_BUS, "mclk_audio_adc_bus", "mclk_sai2", 0,
|
||||
RV1126B_BUSCLKGATE_CON(5), 14, GFLAGS),
|
||||
FACTOR(MCLK_AUDIO_ADC_DIV4_BUS, "mclk_audio_adc_div4_bus", "mclk_audio_adc_bus", 0, 1, 4),
|
||||
GATE(PCLK_RKCE, "pclk_rkce", "pclk_bus_root", 0,
|
||||
GATE(PCLK_RKCE, "pclk_rkce", "pclk_bus_root", CLK_IS_CRITICAL,
|
||||
RV1126B_BUSCLKGATE_CON(6), 0, GFLAGS),
|
||||
GATE(HCLK_NS_RKCE, "hclk_ns_rkce", "hclk_bus_root", 0,
|
||||
RV1126B_BUSCLKGATE_CON(6), 1, GFLAGS),
|
||||
|
||||
@@ -620,7 +620,7 @@ static void sii902x_bridge_mode_set(struct drm_bridge *bridge,
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
if (sii902x->mode.flags & DRM_MODE_FLAG_INTERLACE)
|
||||
if (sii902x->mode.flags & DRM_MODE_FLAG_DBLCLK)
|
||||
ratio = SII902X_TPI_CLK_RATIO_2X;
|
||||
else
|
||||
ratio = SII902X_TPI_CLK_RATIO_1X;
|
||||
|
||||
@@ -2646,10 +2646,13 @@ dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
|
||||
}
|
||||
|
||||
out:
|
||||
if (result == connector_status_connected)
|
||||
if (result == connector_status_connected) {
|
||||
extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true);
|
||||
else
|
||||
handle_plugged_change(hdmi, true);
|
||||
} else {
|
||||
extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, false);
|
||||
handle_plugged_change(hdmi, false);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
@@ -3577,7 +3580,6 @@ static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge,
|
||||
|
||||
dw_hdmi_qp_hdcp_disable(hdmi, conn_state);
|
||||
|
||||
handle_plugged_change(hdmi, false);
|
||||
if (hdmi->plat_data->crtc_pre_disable)
|
||||
hdmi->plat_data->crtc_pre_disable(data, bridge->encoder->crtc);
|
||||
mutex_lock(&hdmi->mutex);
|
||||
@@ -3661,8 +3663,6 @@ static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge,
|
||||
dw_hdmi_qp_audio_enable(hdmi);
|
||||
hdmi_clk_regenerator_update_pixel_clock(hdmi);
|
||||
|
||||
handle_plugged_change(hdmi, true);
|
||||
|
||||
if (hdmi->panel)
|
||||
drm_panel_enable(hdmi->panel);
|
||||
|
||||
|
||||
@@ -1,3 +1,3 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
obj-$(CONFIG_ROCKCHIP_EBC_DEV) += ebc_tcon.o eink_tcon.o
|
||||
obj-$(CONFIG_ROCKCHIP_EBC_DEV) += ebc_tcon.o
|
||||
|
||||
@@ -1,301 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
* Author: Zorro Liu <zorro.liu@rock-chips.com>
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/regmap.h>
|
||||
#include "ebc_tcon.h"
|
||||
|
||||
#define HIWORD_UPDATE(x, l, h) (((x) << (l)) | (GENMASK(h, l) << 16))
|
||||
#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
|
||||
|
||||
/* eink register define */
|
||||
#define EINK_IP_ENABLE 0x00
|
||||
#define EINK_SFT_UPDATE 0x04
|
||||
#define EINK_SIT_UPDATE 0x08
|
||||
#define EINK_PRE_IMAGE_BUF_ADDR 0x0c
|
||||
#define EINK_CUR_IMAGE_BUF_ADDR 0x10
|
||||
#define EINK_IMAGE_PROCESS_BUF_ADDR 0x14
|
||||
#define EINK_LINE_DATA_ADDR_OFFSET 0x18
|
||||
#define EINK_IMAGE_WIDTH 0x1c
|
||||
#define EINK_IMAGE_HEIGHT 0x20
|
||||
#define EINK_DATA_FORMAT 0x24
|
||||
#define EINK_IP_STATUS 0x28
|
||||
#define EINK_IP_VERSION 0x2c
|
||||
#define EINK_IP_CLR_INT 0x30
|
||||
#define EINK_INT_SETTING0 0x34
|
||||
#define EINK_INT_SETTING1 0x38
|
||||
#define EINK_INT_SETTING2 0x3c
|
||||
#define EINK_INT_SETTING3 0x40
|
||||
#define EINK_INT_SETTING4 0x44
|
||||
#define EINK_INT_SETTING5 0x48
|
||||
#define EINK_INT_SETTING6 0x4c
|
||||
#define EINK_INT_SETTING7 0x50
|
||||
#define EINK_WF_SETTING0 0x54
|
||||
#define EINK_WF_SETTING1 0x58
|
||||
#define EINK_WF_SETTING2 0x5c
|
||||
#define EINK_WF_SETTING3 0x60
|
||||
#define EINK_WF_SETTING4 0x64
|
||||
#define EINK_WF_SETTING5 0x68
|
||||
#define EINK_WF_SETTING6 0x6c
|
||||
#define EINK_WF_SETTING7 0x70
|
||||
|
||||
struct eink_reg_data {
|
||||
int addr;
|
||||
int value;
|
||||
};
|
||||
|
||||
static const struct eink_reg_data PANEL_1200x825_INIT[] = {
|
||||
{ EINK_SFT_UPDATE, 0x00030001 },
|
||||
{ EINK_SIT_UPDATE, 0x00050000 },
|
||||
{ EINK_LINE_DATA_ADDR_OFFSET, 0x000004b0 }, //width
|
||||
{ EINK_IMAGE_WIDTH, 0x000004af }, //width - 1
|
||||
{ EINK_IMAGE_HEIGHT, 0x00000338 }, //height - 1
|
||||
|
||||
{ EINK_INT_SETTING0, 0x0e56676f },
|
||||
{ EINK_INT_SETTING1, 0x40674408 },
|
||||
{ EINK_INT_SETTING2, 0xd7eb7743 },
|
||||
{ EINK_INT_SETTING3, 0x19414d35 },
|
||||
{ EINK_INT_SETTING4, 0x12561c00 },
|
||||
{ EINK_INT_SETTING5, 0x05552e0a },
|
||||
{ EINK_INT_SETTING6, 0x4a400e10 },
|
||||
{ EINK_INT_SETTING7, 0x15496e2b },
|
||||
|
||||
{ EINK_WF_SETTING0, 0xb3f33a52 },
|
||||
{ EINK_WF_SETTING1, 0x2042b122 },
|
||||
{ EINK_WF_SETTING2, 0xbdb0f3be },
|
||||
{ EINK_WF_SETTING3, 0xe289a0ca },
|
||||
{ EINK_WF_SETTING4, 0xb0d3b2c8 },
|
||||
{ EINK_WF_SETTING5, 0x3a32ab20 },
|
||||
{ EINK_WF_SETTING6, 0xa69a634c },
|
||||
{ EINK_WF_SETTING7, 0xd87af2c0 },
|
||||
};
|
||||
|
||||
static const struct eink_reg_data PANEL_1872x1404_INIT[] = {
|
||||
{ EINK_SFT_UPDATE, 0x00030001 },
|
||||
{ EINK_SIT_UPDATE, 0x00050000 },
|
||||
{ EINK_LINE_DATA_ADDR_OFFSET, 0x00000750 }, //width
|
||||
{ EINK_IMAGE_WIDTH, 0x0000074f }, //width - 1
|
||||
{ EINK_IMAGE_HEIGHT, 0x0000057c }, //height -1
|
||||
|
||||
{ EINK_INT_SETTING0, 0x0e56676f },
|
||||
{ EINK_INT_SETTING1, 0x40674408 },
|
||||
{ EINK_INT_SETTING2, 0xb14a4643 },
|
||||
{ EINK_INT_SETTING3, 0x19414d35 },
|
||||
{ EINK_INT_SETTING4, 0x12561c00 },
|
||||
{ EINK_INT_SETTING5, 0x05552e0a },
|
||||
{ EINK_INT_SETTING6, 0x4a400e10 },
|
||||
{ EINK_INT_SETTING7, 0x15496e2b },
|
||||
|
||||
{ EINK_WF_SETTING0, 0xb3f33a52 },
|
||||
{ EINK_WF_SETTING1, 0x2042b122 },
|
||||
{ EINK_WF_SETTING2, 0x34b0708b },
|
||||
{ EINK_WF_SETTING3, 0xe289a0ca },
|
||||
{ EINK_WF_SETTING4, 0xb0d3b2c8 },
|
||||
{ EINK_WF_SETTING5, 0x3a32ab20 },
|
||||
{ EINK_WF_SETTING6, 0x2f9ae079 },
|
||||
{ EINK_WF_SETTING7, 0xd87af2c0 },
|
||||
};
|
||||
|
||||
static inline void tcon_write(struct eink_tcon *tcon, unsigned int reg,
|
||||
unsigned int value)
|
||||
{
|
||||
regmap_write(tcon->regmap_base, reg, value);
|
||||
}
|
||||
|
||||
static inline unsigned int tcon_read(struct eink_tcon *tcon, unsigned int reg)
|
||||
{
|
||||
unsigned int value;
|
||||
|
||||
regmap_read(tcon->regmap_base, reg, &value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static inline void tcon_update_bits(struct eink_tcon *tcon, unsigned int reg,
|
||||
unsigned int mask, unsigned int val)
|
||||
{
|
||||
regmap_update_bits(tcon->regmap_base, reg, mask, val);
|
||||
}
|
||||
|
||||
static int tcon_enable(struct eink_tcon *tcon, struct ebc_panel *panel)
|
||||
{
|
||||
int reg_num = 0;
|
||||
int i;
|
||||
const struct eink_reg_data *pre_init_reg;
|
||||
|
||||
clk_prepare_enable(tcon->pclk);
|
||||
clk_prepare_enable(tcon->hclk);
|
||||
pm_runtime_get_sync(tcon->dev);
|
||||
|
||||
if ((panel->width == 1872) && (panel->height == 1404)) {
|
||||
pre_init_reg = PANEL_1872x1404_INIT;
|
||||
reg_num = ARRAY_SIZE(PANEL_1872x1404_INIT);
|
||||
} else if ((panel->width == 1200) && (panel->height == 825)) {
|
||||
pre_init_reg = PANEL_1200x825_INIT;
|
||||
reg_num = ARRAY_SIZE(PANEL_1200x825_INIT);
|
||||
} else {
|
||||
pre_init_reg = PANEL_1872x1404_INIT;
|
||||
reg_num = ARRAY_SIZE(PANEL_1872x1404_INIT);
|
||||
}
|
||||
for (i = 0; i < reg_num; i++) {
|
||||
tcon_write(tcon, pre_init_reg[i].addr, pre_init_reg[i].value);
|
||||
}
|
||||
|
||||
enable_irq(tcon->irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tcon_disable(struct eink_tcon *tcon)
|
||||
{
|
||||
disable_irq(tcon->irq);
|
||||
|
||||
pm_runtime_put_sync(tcon->dev);
|
||||
clk_disable_unprepare(tcon->hclk);
|
||||
clk_disable_unprepare(tcon->pclk);
|
||||
}
|
||||
|
||||
static void tcon_image_addr_set(struct eink_tcon *tcon, u32 pre_image_buf_addr,
|
||||
u32 cur_image_buf_addr, u32 image_process_buf_addr)
|
||||
{
|
||||
tcon_write(tcon, EINK_PRE_IMAGE_BUF_ADDR, pre_image_buf_addr);
|
||||
tcon_write(tcon, EINK_CUR_IMAGE_BUF_ADDR, cur_image_buf_addr);
|
||||
tcon_write(tcon, EINK_IMAGE_PROCESS_BUF_ADDR, image_process_buf_addr);
|
||||
}
|
||||
|
||||
static void tcon_frame_start(struct eink_tcon *tcon)
|
||||
{
|
||||
tcon_write(tcon, EINK_IP_ENABLE, 1);
|
||||
}
|
||||
|
||||
static irqreturn_t tcon_irq_hanlder(int irq, void *dev_id)
|
||||
{
|
||||
struct eink_tcon *tcon = (struct eink_tcon *)dev_id;
|
||||
u32 intr_status;
|
||||
|
||||
intr_status = tcon_read(tcon, EINK_IP_STATUS);
|
||||
|
||||
if (intr_status & 0x1) {
|
||||
tcon_update_bits(tcon, EINK_IP_CLR_INT, 0x1, 0x1);
|
||||
|
||||
if (tcon->dsp_end_callback)
|
||||
tcon->dsp_end_callback();
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct regmap_config eink_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
};
|
||||
|
||||
static int eink_tcon_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct eink_tcon *tcon;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
|
||||
if (!tcon)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
tcon->regs = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(tcon->regs))
|
||||
return PTR_ERR(tcon->regs);
|
||||
|
||||
tcon->len = resource_size(res);
|
||||
eink_regmap_config.max_register = resource_size(res) - 4;
|
||||
eink_regmap_config.name = "rockchip,eink_tcon";
|
||||
tcon->regmap_base = devm_regmap_init_mmio(dev, tcon->regs, &eink_regmap_config);
|
||||
if (IS_ERR(tcon->regmap_base))
|
||||
return PTR_ERR(tcon->regmap_base);
|
||||
|
||||
tcon->hclk = devm_clk_get(dev, "hclk");
|
||||
if (IS_ERR(tcon->hclk)) {
|
||||
ret = PTR_ERR(tcon->hclk);
|
||||
dev_err(dev, "failed to get hclk clock: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
tcon->pclk = devm_clk_get(dev, "pclk");
|
||||
if (IS_ERR(tcon->pclk)) {
|
||||
ret = PTR_ERR(tcon->pclk);
|
||||
dev_err(dev, "failed to get dclk clock: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
tcon->irq = platform_get_irq(pdev, 0);
|
||||
if (tcon->irq < 0) {
|
||||
dev_err(dev, "No IRQ resource!\n");
|
||||
return tcon->irq;
|
||||
}
|
||||
|
||||
irq_set_status_flags(tcon->irq, IRQ_NOAUTOEN);
|
||||
ret = devm_request_irq(dev, tcon->irq, tcon_irq_hanlder,
|
||||
0, dev_name(dev), tcon);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to requeset irq: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
tcon->dev = dev;
|
||||
tcon->enable = tcon_enable;
|
||||
tcon->disable = tcon_disable;
|
||||
tcon->image_addr_set = tcon_image_addr_set;
|
||||
tcon->frame_start = tcon_frame_start;
|
||||
platform_set_drvdata(pdev, tcon);
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int eink_tcon_remove(struct platform_device *pdev)
|
||||
{
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id eink_tcon_of_match[] = {
|
||||
{ .compatible = "rockchip,rk3568-eink-tcon" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, eink_tcon_of_match);
|
||||
|
||||
static struct platform_driver eink_tcon_driver = {
|
||||
.driver = {
|
||||
.name = "rk-eink-tcon",
|
||||
.of_match_table = eink_tcon_of_match,
|
||||
},
|
||||
.probe = eink_tcon_probe,
|
||||
.remove = eink_tcon_remove,
|
||||
};
|
||||
module_platform_driver(eink_tcon_driver);
|
||||
|
||||
MODULE_AUTHOR("Zorro Liu <zorro.liu@rock-chips.com>");
|
||||
MODULE_DESCRIPTION("ROCKCHIP EINK tcon driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@@ -1906,6 +1906,7 @@ static int rockchip_drm_bind(struct device *dev)
|
||||
goto err_drm_fbdev_fini;
|
||||
|
||||
rockchip_drm_error_event_init(drm_dev);
|
||||
rockchip_clocks_loader_unprotect();
|
||||
|
||||
return 0;
|
||||
err_drm_fbdev_fini:
|
||||
|
||||
@@ -1311,7 +1311,7 @@ static const char *const loader_protect_clocks[] __initconst = {
|
||||
"dclk_vp3",
|
||||
};
|
||||
|
||||
static struct clk **loader_clocks __initdata;
|
||||
static struct clk **loader_clocks;
|
||||
static int __init rockchip_clocks_loader_protect(void)
|
||||
{
|
||||
int nclocks = ARRAY_SIZE(loader_protect_clocks);
|
||||
@@ -1335,7 +1335,7 @@ static int __init rockchip_clocks_loader_protect(void)
|
||||
}
|
||||
arch_initcall_sync(rockchip_clocks_loader_protect);
|
||||
|
||||
static int __init rockchip_clocks_loader_unprotect(void)
|
||||
int rockchip_clocks_loader_unprotect(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
@@ -1349,8 +1349,8 @@ static int __init rockchip_clocks_loader_unprotect(void)
|
||||
clk_disable_unprepare(clk);
|
||||
}
|
||||
kfree(loader_clocks);
|
||||
loader_clocks = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
late_initcall_sync(rockchip_clocks_loader_unprotect);
|
||||
#endif
|
||||
|
||||
@@ -42,5 +42,13 @@ struct rockchip_drm_mode_set {
|
||||
|
||||
void rockchip_drm_show_logo(struct drm_device *drm_dev);
|
||||
void rockchip_free_loader_memory(struct drm_device *drm);
|
||||
#ifndef MODULE
|
||||
int rockchip_clocks_loader_unprotect(void);
|
||||
#else
|
||||
static inline int rockchip_clocks_loader_unprotect(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -2626,7 +2626,8 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
|
||||
}
|
||||
if ((vop->version == VOP_VERSION_RK3036 ||
|
||||
vop->version == VOP_VERSION_RK3506 ||
|
||||
vop->version == VOP_VERSION_RK3576_LITE) &&
|
||||
vop->version == VOP_VERSION_RK3576_LITE ||
|
||||
vop->version == VOP_VERSION_RV1126B) &&
|
||||
(adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE))
|
||||
dsp_h = dsp_h / 2;
|
||||
|
||||
@@ -2643,7 +2644,8 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
|
||||
dsp_sty = dest->y1 + mode->crtc_vtotal - mode->crtc_vsync_start;
|
||||
if ((vop->version == VOP_VERSION_RK3036 ||
|
||||
vop->version == VOP_VERSION_RK3506 ||
|
||||
vop->version == VOP_VERSION_RK3576_LITE) &&
|
||||
vop->version == VOP_VERSION_RK3576_LITE ||
|
||||
vop->version == VOP_VERSION_RV1126B) &&
|
||||
(adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE))
|
||||
dsp_sty = dest->y1 / 2 + mode->crtc_vtotal - mode->crtc_vsync_start;
|
||||
dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
|
||||
@@ -3444,10 +3446,10 @@ vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
|
||||
|
||||
/*
|
||||
* Dclk need to be double if BT656 interface and vop version >= 2.12.
|
||||
* That is RV1126/RV1106/RK3576_LITE/RK3506
|
||||
* That is RV1126/RV1106/RK3576_LITE/RK3506/RV1126B
|
||||
*/
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLCLK ||
|
||||
(VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) >= 12 &&
|
||||
(vop->version >= VOP_VERSION_RV1106 && vop->version <= VOP_VERSION_RK3288 &&
|
||||
s->output_if & VOP_OUTPUT_IF_BT656))
|
||||
request_clock *= 2;
|
||||
clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
|
||||
@@ -3719,21 +3721,26 @@ static void vop_crtc_send_mcu_cmd(struct drm_crtc *crtc, u32 type, u32 value)
|
||||
if (vop && vop->is_enabled) {
|
||||
switch (type) {
|
||||
case MCU_WRCMD:
|
||||
VOP_CTRL_SET(vop, mcu_force_rdn, 1);
|
||||
VOP_CTRL_SET(vop, mcu_rs, 0);
|
||||
VOP_CTRL_SET(vop, mcu_rw_bypass_port, value);
|
||||
VOP_CTRL_SET(vop, mcu_rs, 1);
|
||||
break;
|
||||
case MCU_WRDATA:
|
||||
VOP_CTRL_SET(vop, mcu_force_rdn, 1);
|
||||
VOP_CTRL_SET(vop, mcu_rs, 1);
|
||||
VOP_CTRL_SET(vop, mcu_rw_bypass_port, value);
|
||||
break;
|
||||
case MCU_RDDATA:
|
||||
VOP_CTRL_SET(vop, mcu_force_rdn, 0);
|
||||
VOP_CTRL_SET(vop, mcu_rs, 1);
|
||||
val = VOP_CTRL_GET(vop, mcu_rw_bypass_port);
|
||||
DRM_DEBUG_DRIVER("mcu read reg[0x%02x] = 0x%02x", value, val);
|
||||
break;
|
||||
case MCU_SETBYPASS:
|
||||
VOP_CTRL_SET(vop, mcu_bypass, value ? 1 : 0);
|
||||
if (!value)
|
||||
VOP_CTRL_SET(vop, mcu_force_rdn, 1);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
@@ -3898,10 +3905,10 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
|
||||
|
||||
/*
|
||||
* Dclk need to be double if BT656 interface and vop version >= 2.12.
|
||||
* That is RV1126/RV1106/RK3576_LITE/RK3506
|
||||
* That is RV1126/RV1106/RK3576_LITE/RK3506/RV1126B
|
||||
*/
|
||||
if (mode->flags & DRM_MODE_FLAG_DBLCLK ||
|
||||
(VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) >= 12 &&
|
||||
(vop->version >= VOP_VERSION_RV1106 && vop->version <= VOP_VERSION_RK3288 &&
|
||||
s->output_if & VOP_OUTPUT_IF_BT656))
|
||||
adj_mode->crtc_clock *= 2;
|
||||
|
||||
@@ -4005,11 +4012,11 @@ static void vop_update_csc(struct drm_crtc *crtc)
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* When using BT656, set RV1126/RV1106/RK3576_LITE/RK3506 to P8888 mode.
|
||||
* When using BT656, set RV1126/RV1106/RK3576_LITE/RK3506/RV1126B to P8888 mode.
|
||||
*/
|
||||
if ((s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
|
||||
!(vop->data->feature & VOP_FEATURE_OUTPUT_10BIT)) ||
|
||||
(VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) >= 12 &&
|
||||
(vop->version >= VOP_VERSION_RV1106 && vop->version <= VOP_VERSION_RK3288 &&
|
||||
s->output_if & VOP_OUTPUT_IF_BT656))
|
||||
s->output_mode = ROCKCHIP_OUT_MODE_P888;
|
||||
|
||||
|
||||
@@ -457,6 +457,7 @@ struct vop_ctrl {
|
||||
struct vop_reg mcu_bypass;
|
||||
struct vop_reg mcu_type;
|
||||
struct vop_reg mcu_rw_bypass_port;
|
||||
struct vop_reg mcu_force_rdn;
|
||||
|
||||
/* bt1120 */
|
||||
struct vop_reg bt1120_uv_swap;
|
||||
|
||||
@@ -1549,20 +1549,27 @@ static void vop2_load_sdr2hdr_table(struct vop2_video_port *vp, int sdr2hdr_tf)
|
||||
const struct vop2_video_port_regs *regs = vp->regs;
|
||||
uint32_t sdr2hdr_eotf_oetf_yn[65];
|
||||
uint32_t sdr2hdr_oetf_dx_dxpow[64];
|
||||
int i;
|
||||
int i, bt1886_eotf_coe = 1;
|
||||
|
||||
for (i = 0; i < 65; i++) {
|
||||
/*
|
||||
* rk3568/rk3588 sdr2hdr bt1886 eotf dx << 1 by mistake, so add
|
||||
* bt1886_eotf_coe to adapt it.
|
||||
*/
|
||||
if (i == 64)
|
||||
bt1886_eotf_coe = 0;
|
||||
|
||||
if (sdr2hdr_tf == SDR2HDR_FOR_BT2020)
|
||||
sdr2hdr_eotf_oetf_yn[i] =
|
||||
table->sdr2hdr_bt1886eotf_yn_for_bt2020[i] +
|
||||
(table->sdr2hdr_bt1886eotf_yn_for_bt2020[i] << bt1886_eotf_coe) +
|
||||
(table->sdr2hdr_st2084oetf_yn_for_bt2020[i] << 18);
|
||||
else if (sdr2hdr_tf == SDR2HDR_FOR_HDR)
|
||||
sdr2hdr_eotf_oetf_yn[i] =
|
||||
table->sdr2hdr_bt1886eotf_yn_for_hdr[i] +
|
||||
(table->sdr2hdr_bt1886eotf_yn_for_hdr[i] << bt1886_eotf_coe) +
|
||||
(table->sdr2hdr_st2084oetf_yn_for_hdr[i] << 18);
|
||||
else if (sdr2hdr_tf == SDR2HDR_FOR_HLG_HDR)
|
||||
sdr2hdr_eotf_oetf_yn[i] =
|
||||
table->sdr2hdr_bt1886eotf_yn_for_hlg_hdr[i] +
|
||||
(table->sdr2hdr_bt1886eotf_yn_for_hlg_hdr[i] << bt1886_eotf_coe) +
|
||||
(table->sdr2hdr_st2084oetf_yn_for_hlg_hdr[i] << 18);
|
||||
}
|
||||
|
||||
@@ -11070,7 +11077,7 @@ static void vop2_setup_hdr10(struct vop2_video_port *vp, uint8_t win_phys_id)
|
||||
bool sdr2hdr_en = 0;
|
||||
bool sdr2hdr_tf = 0;
|
||||
bool hdr2sdr_tf_update = 1;
|
||||
bool sdr2hdr_tf_update = 0; /* default sdr2hdr curve is 1000 nit */
|
||||
bool sdr2hdr_tf_update = 1;
|
||||
unsigned long win_mask = vp->win_mask;
|
||||
int phys_id;
|
||||
bool have_sdr_layer = false;
|
||||
|
||||
@@ -415,24 +415,24 @@ static const u32 sdr2hdr_bt1886eotf_yn_for_bt2020[65] = {
|
||||
};
|
||||
|
||||
static u32 sdr2hdr_bt1886eotf_yn_for_hdr[65] = {
|
||||
/* dst_range 425int */
|
||||
/* dst_range 500 nit */
|
||||
0,
|
||||
5, 21, 49, 91,
|
||||
150, 225, 320, 434,
|
||||
569, 726, 905, 1108,
|
||||
1336, 1588, 1866, 2171,
|
||||
2502, 2862, 3250, 3667,
|
||||
3887, 4114, 4349, 4591,
|
||||
4841, 5099, 5364, 5638,
|
||||
5920, 6209, 6507, 6812,
|
||||
6968, 7126, 7287, 7449,
|
||||
7613, 7779, 7948, 8118,
|
||||
8291, 8466, 8643, 8822,
|
||||
9003, 9187, 9372, 9560,
|
||||
9655, 9750, 9846, 9942,
|
||||
10039, 10136, 10234, 10333,
|
||||
10432, 10531, 10631, 10732,
|
||||
10833, 10935, 11038, 11141,
|
||||
6, 29, 72, 135,
|
||||
221, 330, 463, 621,
|
||||
804, 1014, 1251, 1515,
|
||||
1807, 2126, 2475, 2853,
|
||||
3260, 3696, 4163, 4661,
|
||||
4921, 5189, 5464, 5748,
|
||||
6039, 6338, 6646, 6961,
|
||||
7284, 7615, 7954, 8301,
|
||||
8477, 8656, 8837, 9019,
|
||||
9204, 9391, 9580, 9771,
|
||||
9964, 10159, 10356, 10555,
|
||||
10756, 10959, 11165, 11372,
|
||||
11477, 11582, 11687, 11793,
|
||||
11900, 12007, 12115, 12223,
|
||||
12332, 12441, 12551, 12661,
|
||||
12772, 12883, 12995, 13107,
|
||||
};
|
||||
|
||||
static const u32 sdr2hdr_st2084oetf_yn_for_hlg_hdr[65] = {
|
||||
|
||||
@@ -1639,6 +1639,7 @@ static const struct vop_win_phy px30_win23_data = {
|
||||
.csc_mode = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 2),
|
||||
.format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
|
||||
.rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
|
||||
.interlace_read = VOP_REG_VER(RK3368_WIN2_CTRL0, 0x1, 1, 2, 0xf, -1),
|
||||
.dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
|
||||
.dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
|
||||
.yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
|
||||
@@ -1942,6 +1943,9 @@ static const struct vop_ctrl rv1126b_ctrl_data = {
|
||||
.mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26),
|
||||
.bt1120_yc_swap = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 30),
|
||||
.bt1120_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 31),
|
||||
.bt656_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 6),
|
||||
|
||||
.mcu_force_rdn = VOP_REG(RV1126B_DSP_CTRL1, 0x1, 21),
|
||||
|
||||
.dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
|
||||
.dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
|
||||
|
||||
@@ -1039,6 +1039,7 @@
|
||||
|
||||
#define RV1126_GRF_IOFUNC_CON3 0x1026c
|
||||
|
||||
#define RV1126B_DSP_CTRL1 0x0024
|
||||
#define RV1126B_CLK_CNT 0x0040
|
||||
#define RV1126B_GRF_VOP_LCDC_CON 0x30b9c
|
||||
#define RV1126B_WB_CTRL 0x0280
|
||||
|
||||
@@ -837,6 +837,19 @@ config VIDEO_IMX586
|
||||
To compile this driver as a module, choose M here: the
|
||||
module will be called imx586.
|
||||
|
||||
config VIDEO_IMX766
|
||||
tristate "Sony IMX766 sensor support"
|
||||
depends on I2C && VIDEO_DEV
|
||||
depends on MEDIA_CAMERA_SUPPORT
|
||||
select MEDIA_CONTROLLER
|
||||
select VIDEO_V4L2_SUBDEV_API
|
||||
help
|
||||
This is a Video4Linux2 sensor driver for the Sony
|
||||
IMX766 camera.
|
||||
|
||||
To compile this driver as a module, choose M here: the
|
||||
module will be called imx766.
|
||||
|
||||
config VIDEO_JX_F37
|
||||
tristate "Soi JX_F37 sensor support"
|
||||
depends on I2C && VIDEO_DEV
|
||||
|
||||
@@ -105,6 +105,7 @@ obj-$(CONFIG_VIDEO_IMX492) += imx492.o
|
||||
obj-$(CONFIG_VIDEO_IMX498) += imx498.o
|
||||
obj-$(CONFIG_VIDEO_IMX577) += imx577.o
|
||||
obj-$(CONFIG_VIDEO_IMX586) += imx586.o
|
||||
obj-$(CONFIG_VIDEO_IMX766) += imx766.o
|
||||
obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o
|
||||
obj-$(CONFIG_VIDEO_ISL7998X) += isl7998x.o
|
||||
obj-$(CONFIG_VIDEO_IT6616) += it6616.o
|
||||
|
||||
@@ -713,6 +713,7 @@ static int __dw9800v_set_power(struct dw9800v_device *dw9800v, bool on)
|
||||
goto unlock_and_return;
|
||||
}
|
||||
dw9800v->power_on = true;
|
||||
usleep_range(5000, 6000);
|
||||
} else {
|
||||
ret = regulator_disable(dw9800v->supply);
|
||||
if (ret < 0) {
|
||||
|
||||
@@ -32,6 +32,12 @@
|
||||
#define DW9800W_CHIP_ID 0xF2
|
||||
#define DW9800W_REG_CHIP_ID 0x00
|
||||
|
||||
static const char * const dw9800w_supply_names[] = {
|
||||
"avdd", /* Analog power */
|
||||
};
|
||||
|
||||
#define DW9800W_NUM_SUPPLIES ARRAY_SIZE(dw9800w_supply_names)
|
||||
|
||||
enum mode_e {
|
||||
SAC2_MODE,
|
||||
SAC3_MODE,
|
||||
@@ -43,6 +49,7 @@ enum mode_e {
|
||||
|
||||
/* dw9800w device structure */
|
||||
struct dw9800w_device {
|
||||
struct regulator_bulk_data supplies[DW9800W_NUM_SUPPLIES];
|
||||
struct v4l2_ctrl_handler ctrls_vcm;
|
||||
struct v4l2_ctrl *focus;
|
||||
struct i2c_client *client;
|
||||
@@ -564,9 +571,19 @@ static int dw9800w_init_controls(struct dw9800w_device *dev_vcm)
|
||||
|
||||
static int __dw9800w_set_power(struct dw9800w_device *dw9800w_dev, bool on)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (dw9800w_dev->power_gpio)
|
||||
gpiod_direction_output(dw9800w_dev->power_gpio, on);
|
||||
|
||||
if (on) {
|
||||
ret = regulator_bulk_enable(DW9800W_NUM_SUPPLIES, dw9800w_dev->supplies);
|
||||
if (ret < 0)
|
||||
dev_err(&dw9800w_dev->client->dev, "Failed to enable regulators\n");
|
||||
usleep_range(5000, 6000);
|
||||
} else {
|
||||
regulator_bulk_disable(DW9800W_NUM_SUPPLIES, dw9800w_dev->supplies);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -604,6 +621,18 @@ err:
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int dw9800w_configure_regulators(struct dw9800w_device *dw9800w_dev)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < DW9800W_NUM_SUPPLIES; i++)
|
||||
dw9800w_dev->supplies[i].supply = dw9800w_supply_names[i];
|
||||
|
||||
return devm_regulator_bulk_get(&dw9800w_dev->client->dev,
|
||||
DW9800W_NUM_SUPPLIES,
|
||||
dw9800w_dev->supplies);
|
||||
}
|
||||
|
||||
static int dw9800w_probe(struct i2c_client *client,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
@@ -693,6 +722,12 @@ static int dw9800w_probe(struct i2c_client *client,
|
||||
"Failed to get power-gpios, maybe no use\n");
|
||||
}
|
||||
|
||||
ret = dw9800w_configure_regulators(dw9800w_dev);
|
||||
if (ret) {
|
||||
dev_err(&client->dev, "Failed to get power regulators\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = dw9800w_check_id(dw9800w_dev);
|
||||
if (ret)
|
||||
goto err_power_off;
|
||||
|
||||
@@ -443,12 +443,12 @@ static const struct regval gc8613ya_dag_12bit_3840x2160_30fps_regs[] = {
|
||||
{0x025a, 0x98},
|
||||
|
||||
//30fps 0x08f8
|
||||
//{0x0340, 0x08},
|
||||
//{0x0341, 0xf8},
|
||||
{0x0340, 0x08},
|
||||
{0x0341, 0xf8},
|
||||
|
||||
//15fps:0x11f0
|
||||
{0x0340, 0x11},
|
||||
{0x0341, 0xf0},
|
||||
//{0x0340, 0x11},
|
||||
//{0x0341, 0xf0},
|
||||
|
||||
{0x0345, 0x02},
|
||||
{0x0347, 0x02},
|
||||
@@ -864,12 +864,12 @@ static const struct regval gc8613yn_dag_12bit_3840x2160_30fps_regs[] = {
|
||||
{0x025a, 0x98},
|
||||
|
||||
//30fps 0x08f8
|
||||
//{0x0340, 0x08},
|
||||
//{0x0341, 0xf8},
|
||||
{0x0340, 0x08},
|
||||
{0x0341, 0xf8},
|
||||
|
||||
//15fps:0x11f0
|
||||
{0x0340, 0x11},
|
||||
{0x0341, 0xf0},
|
||||
//{0x0340, 0x11},
|
||||
//{0x0341, 0xf0},
|
||||
|
||||
{0x0345, 0x02},
|
||||
{0x0347, 0x02},
|
||||
@@ -1253,11 +1253,11 @@ static const struct gc8613_mode supported_modes[] = {
|
||||
.height = 2160,
|
||||
.max_fps = {
|
||||
.numerator = 10000,
|
||||
.denominator = 150000,
|
||||
.denominator = 300000,
|
||||
},
|
||||
.exp_def = 0x0327,
|
||||
.hts_def = 0x0310 * 8,
|
||||
.vts_def = 0x08f8 * 2,
|
||||
.vts_def = 0x08f8,
|
||||
.bus_fmt = MEDIA_BUS_FMT_SRGGB12_1X12,
|
||||
.reg_list[0] = gc8613yn_dag_12bit_3840x2160_30fps_regs,
|
||||
.reg_list[1] = gc8613ya_dag_12bit_3840x2160_30fps_regs,
|
||||
|
||||
2359
drivers/media/i2c/imx766.c
Normal file
2359
drivers/media/i2c/imx766.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -731,6 +731,58 @@ static void rkotp_read_af(struct eeprom_device *eeprom_dev,
|
||||
|
||||
}
|
||||
|
||||
static void rkotp_read_qsc(struct eeprom_device *eeprom_dev,
|
||||
struct otp_info *otp_ptr,
|
||||
u32 base_addr)
|
||||
{
|
||||
struct i2c_client *client = eeprom_dev->client;
|
||||
struct device *dev = &eeprom_dev->client->dev;
|
||||
u8 *qsc_calib = &otp_ptr->qsc_data.qsc_calib[0];
|
||||
u32 checksum = 0;
|
||||
u32 temp = 0;
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
|
||||
ret = read_reg_otp(client, base_addr,
|
||||
4, &otp_ptr->qsc_data.size);
|
||||
checksum += otp_ptr->qsc_data.size;
|
||||
base_addr += 4;
|
||||
ret |= read_reg_otp(client, base_addr,
|
||||
2, &otp_ptr->qsc_data.version);
|
||||
checksum += otp_ptr->qsc_data.version;
|
||||
base_addr += 2;
|
||||
ret |= read_reg_otp(client, base_addr,
|
||||
2, &otp_ptr->qsc_data.qsc_size);
|
||||
checksum += otp_ptr->qsc_data.qsc_size;
|
||||
base_addr += 2;
|
||||
|
||||
ret |= read_reg_otp_buf(client, base_addr, RK_QSC_SIZE, qsc_calib);
|
||||
base_addr += RK_QSC_SIZE;
|
||||
|
||||
for (i = 0; i < RK_QSC_SIZE; i++)
|
||||
checksum += qsc_calib[i];
|
||||
|
||||
for (i = 0; i < RK_QSC_RESERVED_SIZE; i++) {
|
||||
ret |= read_reg_otp(client, base_addr, 1, &temp);
|
||||
checksum += temp;
|
||||
base_addr += 1;
|
||||
}
|
||||
|
||||
ret |= read_reg_otp(client, base_addr,
|
||||
1, &otp_ptr->qsc_data.checksum);
|
||||
if ((checksum % 255 + 1) == otp_ptr->qsc_data.checksum && (!ret)) {
|
||||
otp_ptr->qsc_data.flag = 0x01;
|
||||
dev_info(dev, "qsc info:(data[0] 0x%x, checksum 0x%x)\n",
|
||||
otp_ptr->qsc_data.qsc_calib[0],
|
||||
(int)otp_ptr->qsc_data.checksum);
|
||||
} else {
|
||||
otp_ptr->qsc_data.flag = 0x00;
|
||||
dev_info(dev, "qsc info: checksum err, checksum %d, reg_checksum %d\n",
|
||||
(int)(checksum % 255 + 1),
|
||||
(int)otp_ptr->qsc_data.checksum);
|
||||
}
|
||||
}
|
||||
|
||||
static int rkotp_read_data(struct eeprom_device *eeprom_dev)
|
||||
{
|
||||
struct i2c_client *client = eeprom_dev->client;
|
||||
@@ -780,6 +832,12 @@ static int rkotp_read_data(struct eeprom_device *eeprom_dev)
|
||||
base_addr + 1);
|
||||
base_addr += 0x20;
|
||||
break;
|
||||
case RKOTP_QSC_ID:
|
||||
rkotp_read_qsc(eeprom_dev,
|
||||
otp_ptr,
|
||||
base_addr + 1);
|
||||
base_addr += 0x1010;
|
||||
break;
|
||||
default:
|
||||
id = -1;
|
||||
break;
|
||||
|
||||
@@ -58,6 +58,8 @@
|
||||
#define RK_DCCMAP_SIZE 0x0200
|
||||
#define RK_PDAF_RESERVED_SIZE 0x001e
|
||||
#define RK_AF_RESERVED_SIZE 0x0014
|
||||
#define RK_QSC_SIZE 0x1000
|
||||
#define RK_QSC_RESERVED_SIZE 0x0006
|
||||
#define RKOTP_MAX_MODULE 0x0008
|
||||
|
||||
#define RKOTP_REG_START 0x0008//v1 0, v2 0x0008
|
||||
@@ -66,6 +68,7 @@
|
||||
#define RKOTP_LSC_ID 2
|
||||
#define RKOTP_PDAF_ID 3
|
||||
#define RKOTP_AF_ID 4
|
||||
#define RKOTP_QSC_ID 5
|
||||
|
||||
struct id_defination {
|
||||
u32 supplier_id;
|
||||
@@ -165,6 +168,15 @@ struct af_otp_info {
|
||||
u32 size;
|
||||
};
|
||||
|
||||
struct qsc_otp_info {
|
||||
u32 flag;
|
||||
u32 version;
|
||||
u32 qsc_size;
|
||||
u8 qsc_calib[RK_QSC_SIZE];
|
||||
u32 checksum;
|
||||
u32 size;
|
||||
};
|
||||
|
||||
struct otp_info {
|
||||
u32 flag;
|
||||
u32 total_checksum;
|
||||
@@ -174,6 +186,7 @@ struct otp_info {
|
||||
struct sfr_otp_info sfr_otp_data;
|
||||
struct pdaf_otp_info pdaf_data;
|
||||
struct af_otp_info af_data;
|
||||
struct qsc_otp_info qsc_data;
|
||||
};
|
||||
|
||||
/* eeprom device structure */
|
||||
|
||||
@@ -8561,7 +8561,7 @@ int rkcif_do_start_stream(struct rkcif_stream *stream, enum rkcif_stream_mode mo
|
||||
}
|
||||
}
|
||||
if (dev->chip_id >= CHIP_RK1808_CIF) {
|
||||
if (dev->active_sensor &&
|
||||
if (dev->active_sensor &&
|
||||
(dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
|
||||
dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY ||
|
||||
dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)) {
|
||||
@@ -8997,12 +8997,18 @@ void rkcif_stream_init(struct rkcif_device *dev, u32 id)
|
||||
stream->frame_loss = 0;
|
||||
}
|
||||
|
||||
static int rkcif_sensor_set_power(struct rkcif_stream *stream, int on)
|
||||
int rkcif_sensor_set_power(struct rkcif_stream *stream, int on)
|
||||
{
|
||||
struct rkcif_device *cif_dev = stream->cifdev;
|
||||
struct sditf_priv *priv = cif_dev->sditf[0];
|
||||
int i = 0;
|
||||
|
||||
if (!on && atomic_dec_if_positive(&cif_dev->sd_power_cnt))
|
||||
return 0;
|
||||
|
||||
if (on && atomic_inc_return(&cif_dev->sd_power_cnt) > 1)
|
||||
return 0;
|
||||
|
||||
if (cif_dev->terminal_sensor.sd)
|
||||
v4l2_subdev_call(cif_dev->terminal_sensor.sd,
|
||||
core, s_power, on);
|
||||
@@ -9068,11 +9074,11 @@ static int rkcif_fh_open(struct file *filp)
|
||||
ret = v4l2_pipeline_pm_get(&vnode->vdev.entity);
|
||||
v4l2_dbg(1, rkcif_debug, vdev, "open video, entity use_count %d\n",
|
||||
vnode->vdev.entity.use_count);
|
||||
ret = rkcif_sensor_set_power(stream, on);
|
||||
mutex_unlock(&cifdev->stream_lock);
|
||||
if (ret < 0)
|
||||
vb2_fop_release(filp);
|
||||
}
|
||||
ret = rkcif_sensor_set_power(stream, on);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -9088,6 +9094,7 @@ static int rkcif_fh_release(struct file *filp)
|
||||
ret = vb2_fop_release(filp);
|
||||
if (!ret) {
|
||||
mutex_lock(&cifdev->stream_lock);
|
||||
ret = rkcif_sensor_set_power(stream, on);
|
||||
v4l2_pipeline_pm_put(&vnode->vdev.entity);
|
||||
v4l2_dbg(1, rkcif_debug, vdev, "close video, entity use_count %d\n",
|
||||
vnode->vdev.entity.use_count);
|
||||
@@ -9095,7 +9102,6 @@ static int rkcif_fh_release(struct file *filp)
|
||||
}
|
||||
|
||||
pm_runtime_put_sync(cifdev->dev);
|
||||
ret = rkcif_sensor_set_power(stream, on);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -10819,7 +10825,7 @@ void rkcif_irq_oneframe(struct rkcif_device *cif_dev)
|
||||
|
||||
/* There are two irqs enabled:
|
||||
* - PST_INF_FRAME_END: cif FIFO is ready, this is prior to FRAME_END
|
||||
* - FRAME_END: cif has saved frame to memory, a frame ready
|
||||
* - FRAME_END: cif has saved frame to memory, a frame ready
|
||||
*/
|
||||
stream = &cif_dev->stream[RKCIF_STREAM_CIF];
|
||||
|
||||
@@ -11970,6 +11976,7 @@ static void rkcif_update_stream(struct rkcif_device *cif_dev,
|
||||
mipi_id);
|
||||
if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
|
||||
return;
|
||||
stream->last_frame_idx = stream->frame_idx;
|
||||
} else {
|
||||
ret = rkcif_update_new_buffer_wake_up_mode(stream);
|
||||
if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
|
||||
@@ -13602,6 +13609,12 @@ static void rkcif_toisp_check_stop_status(struct sditf_priv *priv,
|
||||
stream->stopping = false;
|
||||
wake_up(&stream->wq_stopped);
|
||||
}
|
||||
if (!(stream->cur_stream_mode & RKCIF_STREAM_MODE_CAPTURE)) {
|
||||
cur_time = rkcif_time_get_ns(stream->cifdev);
|
||||
stream->readout.total_time = cur_time - stream->readout.fe_timestamp;
|
||||
stream->readout.readout_time = cur_time - stream->readout.fs_timestamp;
|
||||
stream->readout.fe_timestamp = cur_time;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&stream->cifdev->stream_spinlock, flags);
|
||||
if (stream->is_wait_stop_complete) {
|
||||
@@ -13747,9 +13760,6 @@ static void rkcif_toisp_check_stop_status(struct sditf_priv *priv,
|
||||
(priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id == 1) ||
|
||||
(priv->hdr_cfg.hdr_mode == HDR_X3 && stream->id == 2)))
|
||||
sditf_disable_immediately(priv);
|
||||
cur_time = rkcif_time_get_ns(stream->cifdev);
|
||||
stream->readout.total_time = cur_time - stream->readout.fs_timestamp;
|
||||
stream->readout.fs_timestamp = cur_time;
|
||||
stream->buf_wake_up_cnt++;
|
||||
if (stream->frame_idx % 2)
|
||||
stream->fps_stats.frm0_timestamp = rkcif_time_get_ns(stream->cifdev);
|
||||
|
||||
@@ -2876,6 +2876,7 @@ int rkcif_plat_init(struct rkcif_device *cif_dev, struct device_node *node, int
|
||||
atomic_set(&cif_dev->power_cnt, 0);
|
||||
atomic_set(&cif_dev->streamoff_cnt, 0);
|
||||
atomic_set(&cif_dev->sensor_off, 1);
|
||||
atomic_set(&cif_dev->sd_power_cnt, 0);
|
||||
cif_dev->is_start_hdr = false;
|
||||
cif_dev->pipe.open = rkcif_pipeline_open;
|
||||
cif_dev->pipe.close = rkcif_pipeline_close;
|
||||
|
||||
@@ -967,6 +967,7 @@ struct rkcif_device {
|
||||
atomic_t power_cnt;
|
||||
atomic_t streamoff_cnt;
|
||||
atomic_t sensor_off;
|
||||
atomic_t sd_power_cnt;
|
||||
struct mutex stream_lock; /* lock between streams */
|
||||
struct mutex scale_lock; /* lock between scale dev */
|
||||
struct mutex tools_lock; /* lock between tools dev */
|
||||
@@ -1179,4 +1180,6 @@ void rkcif_modify_line_int(struct rkcif_stream *stream, bool en);
|
||||
void rkcif_set_sof(struct rkcif_device *cif_dev, u32 seq);
|
||||
|
||||
void rkcif_set_sensor_streamon_in_sync_mode(struct rkcif_device *cif_dev);
|
||||
int rkcif_sensor_set_power(struct rkcif_stream *stream, int on);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -538,6 +538,7 @@ static void rkcif_show_format(struct rkcif_device *dev, struct seq_file *f)
|
||||
u64 fps, timestamp0, timestamp1;
|
||||
unsigned long flags;
|
||||
u32 time_val = 0;
|
||||
u32 remainder = 0;
|
||||
|
||||
if (atomic_read(&pipe->stream_cnt) < 1)
|
||||
return;
|
||||
@@ -586,7 +587,7 @@ static void rkcif_show_format(struct rkcif_device *dev, struct seq_file *f)
|
||||
else
|
||||
fps = timestamp0 > timestamp1 ?
|
||||
timestamp0 - timestamp1 : timestamp1 - timestamp0;
|
||||
fps = div_u64(fps, 1000000);
|
||||
fps = div_u64(fps, 1000);
|
||||
|
||||
seq_puts(f, "Output Info:\n");
|
||||
seq_printf(f, "\tformat:%s/%ux%u(%u,%u)\n",
|
||||
@@ -596,28 +597,27 @@ static void rkcif_show_format(struct rkcif_device *dev, struct seq_file *f)
|
||||
seq_printf(f, "\tcompact:%s\n", stream->is_compact ? "enable" : "disabled");
|
||||
seq_printf(f, "\tframe amount:%d\n", stream->frame_idx - 1);
|
||||
if (dev->inf_id == RKCIF_MIPI_LVDS) {
|
||||
time_val = div_u64(stream->readout.early_time, 1000000);
|
||||
seq_printf(f, "\tearly:%u ms\n", time_val);
|
||||
time_val = div_u64(stream->readout.early_time, 1000);
|
||||
time_val = div_u64_rem(time_val, 1000, &remainder);
|
||||
seq_printf(f, "\tearly:%u.%u ms\n", time_val, remainder);
|
||||
if (dev->hdr.hdr_mode == NO_HDR ||
|
||||
dev->hdr.hdr_mode == HDR_COMPR) {
|
||||
time_val = div_u64(stream->readout.readout_time, 1000000);
|
||||
if (dev->sditf[0] && dev->sditf[0]->mode.rdbk_mode < RKISP_VICAP_RDBK_AIQ)
|
||||
seq_puts(f, "\tsingle readout:N/A\n");
|
||||
else
|
||||
seq_printf(f, "\tsingle readout:%u ms\n", time_val);
|
||||
time_val = div_u64(stream->readout.readout_time, 1000);
|
||||
time_val = div_u64_rem(time_val, 1000, &remainder);
|
||||
seq_printf(f, "\tsingle readout:%u.%u ms\n", time_val, remainder);
|
||||
} else {
|
||||
time_val = div_u64(stream->readout.readout_time, 1000000);
|
||||
if (dev->sditf[0] && dev->sditf[0]->mode.rdbk_mode < RKISP_VICAP_RDBK_AIQ)
|
||||
seq_puts(f, "\tsingle readout:N/A\n");
|
||||
else
|
||||
seq_printf(f, "\tsingle readout:%u ms\n", time_val);
|
||||
time_val = div_u64(stream->readout.total_time, 1000000);
|
||||
seq_printf(f, "\ttotal readout:%u ms\n", time_val);
|
||||
time_val = div_u64(stream->readout.readout_time, 1000);
|
||||
time_val = div_u64_rem(time_val, 1000, &remainder);
|
||||
seq_printf(f, "\tsingle readout:%u.%u ms\n", time_val, remainder);
|
||||
time_val = div_u64(stream->readout.total_time, 1000);
|
||||
time_val = div_u64_rem(time_val, 1000, &remainder);
|
||||
seq_printf(f, "\ttotal readout:%u.%u ms\n", time_val, remainder);
|
||||
|
||||
}
|
||||
}
|
||||
seq_printf(f, "\trate:%llu ms\n", fps);
|
||||
fps = div_u64(1000, fps);
|
||||
time_val = div_u64_rem(fps, 1000, &remainder);
|
||||
seq_printf(f, "\trate:%u.%u ms\n", time_val, remainder);
|
||||
fps = div_u64(1000000, fps);
|
||||
seq_printf(f, "\tfps:%llu\n", fps);
|
||||
seq_puts(f, "\tirq statistics:\n");
|
||||
seq_printf(f, "\t\t\ttotal:%llu\n",
|
||||
|
||||
@@ -1244,6 +1244,7 @@ static int sditf_s_power(struct v4l2_subdev *sd, int on)
|
||||
pm_runtime_put_sync(cif_dev->dev);
|
||||
priv->mode.rdbk_mode = RKISP_VICAP_RDBK_AIQ;
|
||||
}
|
||||
ret |= rkcif_sensor_set_power(&cif_dev->stream[0], on);
|
||||
v4l2_dbg(1, rkcif_debug, &node->vdev, "s_power %d, entity use_count %d\n",
|
||||
on, node->vdev.entity.use_count);
|
||||
mutex_unlock(&cif_dev->stream_lock);
|
||||
|
||||
@@ -4033,12 +4033,13 @@ isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
|
||||
{
|
||||
struct rkisp_isp_params_val_v35 *priv = params_vdev->priv_val;
|
||||
struct rkisp_device *dev = params_vdev->dev;
|
||||
u32 value, ctrl;
|
||||
u32 value, ctrl, b3dldc_ctrl;
|
||||
|
||||
ctrl = isp3_param_read_cache(params_vdev, ISP33_BAY3D_CTRL0, id);
|
||||
if (en == !!(ctrl & ISP35_MODULE_EN))
|
||||
return;
|
||||
|
||||
b3dldc_ctrl = isp3_param_read_cache(params_vdev, ISP35_B3DLDC_CTRL, id);
|
||||
if (en) {
|
||||
if (!priv->buf_bay3d_iir[0].mem_priv ||
|
||||
!priv->buf_bay3d_ds[0].mem_priv ||
|
||||
@@ -4055,6 +4056,10 @@ isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
|
||||
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_RD_BASE, id);
|
||||
if (priv->bay3d_iir_rw_fmt == 3) {
|
||||
isp3_param_write(params_vdev, value, ISP35_B3DLDC_WR_ADDR, id);
|
||||
if (b3dldc_ctrl & ISP35_B3DLDC_EN) {
|
||||
b3dldc_ctrl |= ISP35_B3DLDC_FORCE_UPD;
|
||||
isp3_param_write(params_vdev, b3dldc_ctrl, ISP35_B3DLDC_CTRL, id);
|
||||
}
|
||||
value += priv->bay3d_iir_offs;
|
||||
}
|
||||
isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_BASE, id);
|
||||
@@ -4115,6 +4120,12 @@ isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
|
||||
} else {
|
||||
ctrl &= ~(ISP35_MODULE_EN | ISP35_SELF_FORCE_UPD);
|
||||
isp3_param_write(params_vdev, ctrl, ISP33_BAY3D_CTRL0, id);
|
||||
if (b3dldc_ctrl & ISP35_B3DLDC_EN) {
|
||||
b3dldc_ctrl &= ~(ISP35_B3DLDC_FORCE_UPD | ISP35_B3DLDC_EN);
|
||||
isp3_param_write(params_vdev, b3dldc_ctrl, ISP35_B3DLDC_CTRL, id);
|
||||
|
||||
isp3_param_clear_bits(params_vdev, ISP35_B3DLDC_ADR_STS, ISP35_B3DLDC_EN, id);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -4914,14 +4925,14 @@ static int rkisp_init_mesh_buf(struct rkisp_isp_params_vdev *params_vdev,
|
||||
priv->buf_b3dldc_idx[id] = 0;
|
||||
buf = priv->buf_b3dldc[id];
|
||||
/* b3d_ldch */
|
||||
mesh_w = ALIGN((ALIGN(mesh_w, 16) / 16 + 1) / 2, 2);
|
||||
mesh_w = DIV_ROUND_UP(ALIGN(mesh_w, 16) / 16 + 1, 2);
|
||||
mesh_h = ALIGN(mesh_h, 8) / 8 + 1;
|
||||
mesh_size = ALIGN(mesh_w * mesh_h, 16);
|
||||
mesh_size = ALIGN(mesh_w * 4 * mesh_h, 16);
|
||||
priv->b3dldc_hsize = mesh_w;
|
||||
priv->b3dldch_vsize = mesh_h;
|
||||
/* b3d_ldcv */
|
||||
mesh_h = ALIGN(meshsize->meas_height, 16) / 16 + 2;
|
||||
mesh_size += (mesh_w * mesh_h);
|
||||
mesh_size += (mesh_w * 4 * mesh_h);
|
||||
priv->b3dldcv_vsize = mesh_h;
|
||||
break;
|
||||
default:
|
||||
@@ -4957,7 +4968,7 @@ static int rkisp_init_mesh_buf(struct rkisp_isp_params_vdev *params_vdev,
|
||||
mesh_head->stat = MESH_BUF_INIT;
|
||||
mesh_head->data_oft = ALIGN(sizeof(struct isp2x_mesh_head), 16);
|
||||
mesh_head->data1_oft = mesh_head->data_oft +
|
||||
ALIGN(priv->b3dldc_hsize * priv->b3dldch_vsize, 16);
|
||||
ALIGN(priv->b3dldc_hsize * 4 * priv->b3dldch_vsize, 16);
|
||||
}
|
||||
buf++;
|
||||
}
|
||||
@@ -4992,6 +5003,10 @@ rkisp_params_get_meshbuf_inf_v35(struct rkisp_isp_params_vdev *params_vdev,
|
||||
priv->buf_ldch_idx[id] = 0;
|
||||
buf = priv->buf_ldch[id];
|
||||
break;
|
||||
case ISP35_MODULE_BAY3D:
|
||||
priv->buf_b3dldc_idx[id] = 0;
|
||||
buf = priv->buf_b3dldc[id];
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -263,7 +263,7 @@
|
||||
|
||||
/* VPSS2ENC_DEBUG */
|
||||
#define RKVPSS2X_RO_VPSS2ENC_LINE_CNT(x) ((x) & 0x3fff)
|
||||
#define RKVPSS2X_RO_VPSS2ENC_FRM_CNT(x) (((x) & 0xffffff) >> 16)
|
||||
#define RKVPSS2X_RO_VPSS2ENC_FRM_CNT(x) (((x) >> 16) & 0xff)
|
||||
|
||||
|
||||
/* VPSS_CTRL_SHD */
|
||||
|
||||
@@ -826,7 +826,10 @@ static void stream_frame_start(struct rkvpss_stream *stream, u32 irq)
|
||||
!stream->dev->hw_dev->is_single)
|
||||
stream->ops->update_mi(stream);
|
||||
|
||||
if (dev->stream_vdev.wrap_line) {
|
||||
if (dev->stream_vdev.wrap_line && stream->id == RKVPSS_OUTPUT_CH0) {
|
||||
/* vpss can be holded by enc if isp input offline */
|
||||
if (!irq)
|
||||
rkvpss_unite_set_bits(dev, RKVPSS_VPSS_CTRL, 0, RKVPSS_VPSS2ENC_PIPE_EN);
|
||||
rkvpss_rockit_frame_start(dev);
|
||||
rkvpss_dvbm_event(dev, ROCKIT_DVBM_START);
|
||||
}
|
||||
@@ -898,8 +901,8 @@ static void scl_update_mi(struct rkvpss_stream *stream)
|
||||
stream->ops->enable_mi(stream);
|
||||
}
|
||||
} else if (!stream->is_pause) {
|
||||
/* wrap mode don't disable mi */
|
||||
if (stream->id != RKVPSS_OUTPUT_CH0 || !dev->stream_vdev.wrap_line) {
|
||||
/* wrap mode don't disable mi for ch0 */
|
||||
if (!dev->stream_vdev.wrap_line || stream->id != RKVPSS_OUTPUT_CH0) {
|
||||
stream->is_pause = true;
|
||||
stream->ops->disable_mi(stream);
|
||||
}
|
||||
@@ -918,15 +921,11 @@ static void scl_config_mi(struct rkvpss_stream *stream)
|
||||
struct rkvpss_device *dev = stream->dev;
|
||||
struct capture_fmt *fmt = &stream->out_cap_fmt;
|
||||
struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt;
|
||||
u32 reg, val, mask;
|
||||
|
||||
v4l2_dbg(4, rkvpss_debug, &dev->v4l2_dev,
|
||||
"%s stream:%d\n", __func__, stream->id);
|
||||
u32 reg, val, mask, height = out_fmt->height;
|
||||
|
||||
val = out_fmt->plane_fmt[0].bytesperline;
|
||||
reg = stream->config->mi.stride;
|
||||
rkvpss_unite_write(dev, reg, val);
|
||||
rkvpss_unite_write(dev, reg, val);
|
||||
|
||||
switch (fmt->fourcc) {
|
||||
case V4L2_PIX_FMT_RGB565:
|
||||
@@ -942,18 +941,27 @@ static void scl_config_mi(struct rkvpss_stream *stream)
|
||||
break;
|
||||
}
|
||||
|
||||
val = val * out_fmt->height;
|
||||
val = val * height;
|
||||
reg = stream->config->mi.y_pic_size;
|
||||
rkvpss_unite_write(dev, reg, val);
|
||||
|
||||
if (dev->stream_vdev.wrap_line && stream->id == RKVPSS_OUTPUT_CH0)
|
||||
val = out_fmt->plane_fmt[0].bytesperline * dev->stream_vdev.wrap_line;
|
||||
else
|
||||
val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
|
||||
if (dev->stream_vdev.wrap_line && stream->id == RKVPSS_OUTPUT_CH0) {
|
||||
mask = RKVPSS_VPSS2ENC_SEL | RKVPSS2X_SENSOR_ID(7) |
|
||||
RKVPSS_VPSS2ENC_CNT_SEL;
|
||||
val = RKVPSS_VPSS2ENC_SEL | RKVPSS2X_VPSS2ENC_PATH_EN |
|
||||
RKVPSS2X_SENSOR_ID(dev->dev_id);
|
||||
rkvpss_unite_set_bits(dev, RKVPSS_VPSS_CTRL, mask, val);
|
||||
|
||||
height = dev->stream_vdev.wrap_line;
|
||||
}
|
||||
val = out_fmt->plane_fmt[0].bytesperline * height;
|
||||
reg = stream->config->mi.y_size;
|
||||
rkvpss_unite_write(dev, reg, val);
|
||||
|
||||
val = out_fmt->plane_fmt[1].sizeimage;
|
||||
if (dev->stream_vdev.wrap_line && stream->id == RKVPSS_OUTPUT_CH0)
|
||||
val = out_fmt->plane_fmt[0].bytesperline * height / 2;
|
||||
else
|
||||
val = out_fmt->plane_fmt[1].sizeimage;
|
||||
reg = stream->config->mi.uv_size;
|
||||
rkvpss_unite_write(dev, reg, val);
|
||||
|
||||
@@ -1154,14 +1162,14 @@ static void rkvpss_frame_end(struct rkvpss_stream *stream)
|
||||
struct rkvpss_buffer *buf = NULL;
|
||||
unsigned long lock_flags = 0;
|
||||
|
||||
v4l2_dbg(3, rkvpss_debug, &dev->v4l2_dev,
|
||||
"%s stream:%d\n", __func__, stream->id);
|
||||
spin_lock_irqsave(&stream->vbq_lock, lock_flags);
|
||||
if (stream->curr_buf) {
|
||||
buf = stream->curr_buf;
|
||||
/* wrap mode use one buffer */
|
||||
if (stream->curr_buf->vb.vb2_buf.memory || !dev->stream_vdev.wrap_line)
|
||||
/* rockit wrap mode use one buffer for ch0 */
|
||||
if (stream->curr_buf->vb.vb2_buf.memory ||
|
||||
!dev->stream_vdev.wrap_line || stream->id != RKVPSS_OUTPUT_CH0) {
|
||||
buf = stream->curr_buf;
|
||||
stream->curr_buf = NULL;
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
|
||||
|
||||
@@ -1270,6 +1278,8 @@ static void rkvpss_buf_queue(struct vb2_buffer *vb)
|
||||
if (cap_fmt->mplanes == 1) {
|
||||
for (i = 0; i < cap_fmt->cplanes - 1; i++) {
|
||||
height = pixm->height;
|
||||
if (dev->stream_vdev.wrap_line && stream->id == RKVPSS_OUTPUT_CH0)
|
||||
height = dev->stream_vdev.wrap_line;
|
||||
size = (i == 0) ?
|
||||
pixm->plane_fmt[i].bytesperline * height :
|
||||
pixm->plane_fmt[i].sizeimage;
|
||||
@@ -1910,6 +1920,8 @@ static void rkvpss_stop_streaming(struct vb2_queue *queue)
|
||||
rkvpss_stream_stop(stream);
|
||||
rkvpss_pipeline_stream(dev, false);
|
||||
}
|
||||
if (dev->stream_vdev.wrap_line && stream->id == RKVPSS_OUTPUT_CH0)
|
||||
rkvpss_dvbm_deinit(dev);
|
||||
destroy_buf_queue(stream, VB2_BUF_STATE_ERROR);
|
||||
rkvpss_pipeline_close(dev);
|
||||
tasklet_disable(&stream->buf_done_tasklet);
|
||||
@@ -2022,7 +2034,8 @@ static int rkvpss_start_streaming(struct vb2_queue *queue, unsigned int count)
|
||||
v4l2_err(&dev->v4l2_dev, "start %s failed\n", node->vdev.name);
|
||||
goto pipe_close;
|
||||
}
|
||||
|
||||
if (dev->stream_vdev.wrap_line && stream->id == RKVPSS_OUTPUT_CH0)
|
||||
rkvpss_dvbm_init(stream);
|
||||
ret = rkvpss_pipeline_stream(dev, true);
|
||||
if (ret < 0)
|
||||
goto stop_stream;
|
||||
@@ -2037,6 +2050,8 @@ static int rkvpss_start_streaming(struct vb2_queue *queue, unsigned int count)
|
||||
mutex_unlock(&hw->dev_lock);
|
||||
return 0;
|
||||
stop_stream:
|
||||
if (dev->stream_vdev.wrap_line && stream->id == RKVPSS_OUTPUT_CH0)
|
||||
rkvpss_dvbm_deinit(dev);
|
||||
stream->streaming = false;
|
||||
rkvpss_stream_stop(stream);
|
||||
pipe_close:
|
||||
@@ -2758,9 +2773,6 @@ static int rkvpss_set_wrap_line(struct rkvpss_stream *stream, int *wrap_line)
|
||||
return -EINVAL;
|
||||
|
||||
vpss_dev->stream_vdev.wrap_line = *wrap_line;
|
||||
|
||||
//set_wrap todo
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -20,7 +20,7 @@ static struct dvbm_port *g_dvbm;
|
||||
|
||||
int rkvpss_dvbm_get(struct rkvpss_device *vpss_dev)
|
||||
{
|
||||
struct device_node *np = vpss_dev->dev->of_node;
|
||||
struct device_node *np = vpss_dev->hw_dev->dev->of_node;
|
||||
struct device_node *np_dvbm = of_parse_phandle(np, "dvbm", 0);
|
||||
int ret = 0;
|
||||
|
||||
@@ -35,7 +35,10 @@ int rkvpss_dvbm_get(struct rkvpss_device *vpss_dev)
|
||||
}
|
||||
|
||||
of_node_put(np_dvbm);
|
||||
|
||||
if (IS_ERR_OR_NULL(g_dvbm)) {
|
||||
g_dvbm = NULL;
|
||||
ret = -EINVAL;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -63,7 +66,7 @@ int rkvpss_dvbm_init(struct rkvpss_stream *stream)
|
||||
dvbm_cfg.cbuf_fstd = dvbm_cfg.ybuf_fstd / 2;
|
||||
|
||||
rk_dvbm_ctrl(g_dvbm, DVBM_VPSS_SET_CFG, &dvbm_cfg);
|
||||
rk_dvbm_link(g_dvbm, 0);
|
||||
rk_dvbm_link(g_dvbm, vpss_dev->dev_id);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -73,7 +76,7 @@ void rkvpss_dvbm_deinit(struct rkvpss_device *vpss_dev)
|
||||
pr_err("g_dvbm %p or vpss_dev %p is NULL\n", g_dvbm, vpss_dev);
|
||||
return;
|
||||
}
|
||||
rk_dvbm_unlink(g_dvbm, 0);
|
||||
rk_dvbm_unlink(g_dvbm, vpss_dev->dev_id);
|
||||
}
|
||||
|
||||
int rkvpss_dvbm_event(struct rkvpss_device *vpss_dev, u32 event)
|
||||
|
||||
@@ -292,12 +292,17 @@ int rkvpss_rockit_buf_done(struct rkvpss_stream *stream, int cmd, struct rkvpss_
|
||||
curr_buf->vb.sequence,
|
||||
curr_buf->dma[0]);
|
||||
} else {
|
||||
//tosee
|
||||
if (!(stream->dev->stream_vdev.wrap_line && stream->id == RKVPSS_OUTPUT_CH0))
|
||||
return 0;
|
||||
|
||||
rockit_vpss_cfg->frame.u64PTS = vpss_dev->vpss_sdev.frame_timestamp;
|
||||
rockit_vpss_cfg->frame.u32TimeRef = vpss_dev->vpss_sdev.frame_seq;
|
||||
rockit_vpss_cfg->frame.ispEncCnt =
|
||||
RKVPSS2X_RO_VPSS2ENC_FRM_CNT(rkvpss_hw_read(vpss_dev->hw_dev, RKVPSS2X_VPSS2ENC_DEBUG));
|
||||
v4l2_dbg(2, rkvpss_debug, &vpss_dev->v4l2_dev,
|
||||
"stream:%d seq:%d enc_frm_cnt:%d rockit buf done:0x%x\n",
|
||||
stream->id, curr_buf->vb.sequence,
|
||||
rockit_vpss_cfg->frame.ispEncCnt, curr_buf->dma[0]);
|
||||
}
|
||||
|
||||
rockit_vpss_cfg->frame.u32Height = stream->out_fmt.height;
|
||||
@@ -571,7 +576,8 @@ void rkvpss_rockit_frame_start(struct rkvpss_device *dev)
|
||||
stream = &dev->stream_vdev.stream[i];
|
||||
if (!stream->streaming)
|
||||
continue;
|
||||
rkvpss_rockit_buf_done(stream, ROCKIT_DVBM_START, stream->curr_buf);
|
||||
if (stream->curr_buf && !stream->curr_buf->vb.vb2_buf.memory)
|
||||
rkvpss_rockit_buf_done(stream, ROCKIT_DVBM_START, stream->curr_buf);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -79,6 +79,8 @@
|
||||
#define PMPCSR_LO 0x200
|
||||
#define PMPCSR_HI 0x204
|
||||
|
||||
#define EDOSLAR 0x300
|
||||
|
||||
#define NUM_CPU_SAMPLES 100
|
||||
#define NUM_SAMPLES_TO_PRINT 32
|
||||
|
||||
@@ -139,6 +141,9 @@ static int rockchip_debug_dump_edpcsr(struct fiq_debugger_output *output)
|
||||
/* Unlock EDLSR.SLK so that EDPCSRhi gets populated */
|
||||
writel(EDLAR_UNLOCK, base + EDLAR);
|
||||
|
||||
/* Disabled os lock */
|
||||
writel(0, base + EDOSLAR);
|
||||
|
||||
/* Try to read a bunch of times if CPU is actually running */
|
||||
for (j = 0; j < NUM_CPU_SAMPLES &&
|
||||
printed < NUM_SAMPLES_TO_PRINT; j++) {
|
||||
@@ -299,6 +304,9 @@ static int rockchip_panic_notify_edpcsr(struct notifier_block *nb,
|
||||
/* Unlock EDLSR.SLK so that EDPCSRhi gets populated */
|
||||
writel(EDLAR_UNLOCK, base + EDLAR);
|
||||
|
||||
/* Disabled os lock */
|
||||
writel(0, base + EDOSLAR);
|
||||
|
||||
pr_err("CPU%d online:%d\n", i, cpu_online(i));
|
||||
|
||||
/* Try to read a bunch of times if CPU is actually running */
|
||||
@@ -533,6 +541,8 @@ static int rockchip_hardlock_notify(struct notifier_block *nb,
|
||||
base = rockchip_cpu_debug[cpu];
|
||||
/* Unlock EDLSR.SLK so that EDPCSRhi gets populated */
|
||||
writel(EDLAR_UNLOCK, base + EDLAR);
|
||||
/* Disabled os lock */
|
||||
writel(0, base + EDOSLAR);
|
||||
if (sizeof(edpcsr) == 8)
|
||||
edpcsr = ((u64)readl(base + EDPCSR_LO)) |
|
||||
((u64)readl(base + EDPCSR_HI) << 32);
|
||||
|
||||
@@ -141,7 +141,8 @@
|
||||
|
||||
#define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002
|
||||
#define ROCKCHIP_SPI_VER2_TYPE2 0x00110002
|
||||
#define ROCKCHIP_SPI_VER3 0x03110003
|
||||
#define ROCKCHIP_SPI_VER3_TYPE1 0x03110003
|
||||
#define ROCKCHIP_SPI_VER3_TYPE2 0x03120003
|
||||
|
||||
/*
|
||||
* The callback function may not be timely, and even cs has been released, so
|
||||
@@ -889,7 +890,8 @@ static int rockchip_spi_slave_probe(struct platform_device *pdev)
|
||||
|
||||
init_completion(&rs->xfer_done);
|
||||
switch (rs->version) {
|
||||
case ROCKCHIP_SPI_VER3:
|
||||
case ROCKCHIP_SPI_VER3_TYPE2:
|
||||
case ROCKCHIP_SPI_VER3_TYPE1:
|
||||
rs->ext_spi_clk = true;
|
||||
rs->dma_timeout = 16;
|
||||
rs->fixed_burst_size = 16;
|
||||
|
||||
@@ -143,7 +143,7 @@ static int spidev_mst_read(struct spidev_rkmst_data *spidev, void *rxbuf, size_t
|
||||
spi_message_init(&m);
|
||||
spi_message_add_tail(&t, &m);
|
||||
|
||||
ret = spidev_mst_wait_for_slave_ready(spidev, SPI_OBJ_MAX_XFER_SIZE);
|
||||
ret = spidev_mst_wait_for_slave_ready(spidev, SPI_OBJ_DEFAULT_TIMEOUT_US);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
@@ -169,7 +169,7 @@ static int spidev_slv_write_and_read(struct spidev_rkmst_data *spidev,
|
||||
spi_message_init(&m);
|
||||
spi_message_add_tail(&t, &m);
|
||||
|
||||
ret = spidev_mst_wait_for_slave_ready(spidev, SPI_OBJ_MAX_XFER_SIZE);
|
||||
ret = spidev_mst_wait_for_slave_ready(spidev, SPI_OBJ_DEFAULT_TIMEOUT_US);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
||||
@@ -94,7 +94,7 @@
|
||||
#define CLK_GMAC_125M 84
|
||||
#define CLK_TIMER_ROOT 85
|
||||
#define TCLK_WDT_NS_SRC 86
|
||||
#define TCLK_WDT_S 87
|
||||
#define TCLK_WDT_S_SRC 87
|
||||
#define TCLK_WDT_HPMCU 88
|
||||
#define CLK_CAN0 89
|
||||
#define CLK_CAN1 90
|
||||
@@ -369,8 +369,26 @@
|
||||
#define ACLK_VPSL 359
|
||||
#define CLK_CORE_VPSL 360
|
||||
#define CLK_MACPHY 361
|
||||
#define HCLK_RKRNG_NS 362
|
||||
#define HCLK_RKRNG_S_NS 362
|
||||
|
||||
#define CLK_NR_CLKS (CLK_MACPHY + 1)
|
||||
/* secure clks */
|
||||
#define CLK_USER_OTPC_S 400
|
||||
#define CLK_SBPI_OTPC_S 401
|
||||
#define PCLK_OTPC_S 402
|
||||
#define PCLK_KEY_READER_S 403
|
||||
#define HCLK_KL_RKCE_S 404
|
||||
#define HCLK_RKCE_S 405
|
||||
#define PCLK_WDT_S 406
|
||||
#define TCLK_WDT_S 407
|
||||
#define CLK_STIMER0 408
|
||||
#define CLK_STIMER1 409
|
||||
#define PLK_STIMER 410
|
||||
#define HCLK_RKRNG_S 411
|
||||
#define CLK_PKA_RKCE_S 412
|
||||
#define ACLK_RKCE_S 413
|
||||
|
||||
#define CLK_NR_CLKS (ACLK_RKCE_S + 1)
|
||||
|
||||
// ======================= TOPCRU module definition bank=0 ========================
|
||||
// TOPCRU_SOFTRST_CON15(Offset:0xA3C)
|
||||
|
||||
114
include/dt-bindings/suspend/rockchip-rv1126b.h
Normal file
114
include/dt-bindings/suspend/rockchip-rv1126b.h
Normal file
@@ -0,0 +1,114 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_RV1126B_PM_H__
|
||||
#define __DT_BINDINGS_RV1126B_PM_H__
|
||||
/******************************bits ops************************************/
|
||||
|
||||
#ifndef BIT
|
||||
#define BIT(nr) (1 << (nr))
|
||||
#endif
|
||||
|
||||
#define RKPM_SLP_ARMPD BIT(0)
|
||||
#define RKPM_SLP_ARMOFF BIT(1)
|
||||
#define RKPM_SLP_ARMOFF_DDRPD BIT(2)
|
||||
#define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
|
||||
#define RKPM_SLP_ARMOFF_PMUOFF BIT(4)
|
||||
|
||||
#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8)
|
||||
#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
|
||||
#define RKPM_SLP_PMU_DIS_OSC BIT(10)
|
||||
|
||||
#define RKPM_SLP_CLK_GT BIT(16)
|
||||
#define RKPM_SLP_PMIC_LP BIT(17)
|
||||
|
||||
#define RKPM_SLP_32K_EXT BIT(24)
|
||||
#define RKPM_SLP_TIME_OUT_WKUP BIT(25)
|
||||
#define RKPM_SLP_PMU_DBG BIT(26)
|
||||
#define RKPM_SLP_LP_PR BIT(27)
|
||||
#define RKPM_SLP_ARCH_TIMER_RESET BIT(28)
|
||||
|
||||
/* the wake up source */
|
||||
#define RKPM_CPU0_WKUP_EN BIT(0)
|
||||
#define RKPM_CPU1_WKUP_EN BIT(1)
|
||||
#define RKPM_CPU2_WKUP_EN BIT(2)
|
||||
#define RKPM_CPU3_WKUP_EN BIT(3)
|
||||
#define RKPM_GPIO0_WKUP_EN BIT(4)
|
||||
#define RKPM_SDMMC0_WKUP_EN BIT(5)
|
||||
#define RKPM_SDMMC1_WKUP_EN BIT(6)
|
||||
#define RKPM_SDIO_WKUP_EN BIT(7)
|
||||
#define RKPM_USB_WKUP_EN BIT(8)
|
||||
#define RKPM_UART0_WKUP_EN BIT(9)
|
||||
#define RKPM_I2C2_WKUP_EN BIT(10)
|
||||
#define RKPM_PWM1_WKUP_EN BIT(11)
|
||||
#define RKPM_TIMER_WKUP_EN BIT(12)
|
||||
#define RKPM_HPTIMER_WKUP_EN BIT(13)
|
||||
#define RKPM_SYSINT_WKUP_EN BIT(14)
|
||||
#define RKPM_AOV_WKUP_EN BIT(15)
|
||||
#define RKPM_AAD_WKUP_EN BIT(16)
|
||||
#define RKPM_TIMEOUT_WKUP_EN BIT(17)
|
||||
|
||||
/* sleep pin */
|
||||
#define RKPM_SLEEP_PIN0_EN BIT(0) /* GPIO0_A3 */
|
||||
#define RKPM_SLEEP_PIN1_EN BIT(1) /* GPIO0_A4 */
|
||||
#define RKPM_SLEEP_PIN2_EN BIT(2) /* GPIO0_C1 */
|
||||
|
||||
#define RKPM_SLEEP_PIN0_ACT_LOW BIT(0) /* GPIO0_A3 */
|
||||
#define RKPM_SLEEP_PIN1_ACT_LOW BIT(1) /* GPIO0_A4 */
|
||||
#define RKPM_SLEEP_PIN2_ACT_LOW BIT(2) /* GPIO0_C1 */
|
||||
|
||||
/* io config */
|
||||
#define RKPM_IO_CFG_IOMUX_SFT 0
|
||||
#define RKPM_IO_CFG_GPIO_DIR_SFT 8
|
||||
#define RKPM_IO_CFG_GPIO_LVL_SFT 9
|
||||
#define RKPM_IO_CFG_PULL_SFT 10
|
||||
#define RKPM_IO_CFG_ID_SFT 16
|
||||
|
||||
#define RKPM_IO_CFG_IOMUX_MSK 0x3f
|
||||
#define RKPM_IO_CFG_GPIO_DIR_MSK 0x1
|
||||
#define RKPM_IO_CFG_GPIO_LVL_MSK 0x1
|
||||
#define RKPM_IO_CFG_PULL_MSK 0x3
|
||||
#define RKPM_IO_CFG_ID_MSK 0xffff
|
||||
|
||||
#define RKPM_IO_CFG_IOMUX_GPIO_VAL 0
|
||||
#define RKPM_IO_CFG_GPIO_DIR_INPUT_VAL 0
|
||||
#define RKPM_IO_CFG_GPIO_DIR_OUTPUT_VAL 1
|
||||
#define RKPM_IO_CFG_GPIO_LVL_LOW_VAL 0
|
||||
#define RKPM_IO_CFG_GPIO_LVL_HIGH_VAL 1
|
||||
#define RKPM_IO_CFG_PULL_NONE_VAL 0
|
||||
#define RKPM_IO_CFG_PULL_UP_VAL 1
|
||||
#define RKPM_IO_CFG_PULL_DOWN_VAL 2
|
||||
|
||||
#define RKPM_IO_CFG_IOMUX(func) ((func) << RKPM_IO_CFG_IOMUX_SFT)
|
||||
#define RKPM_IO_CFG_GPIO_DIR_INPUT \
|
||||
(RKPM_IO_CFG_GPIO_DIR_INPUT_VAL << RKPM_IO_CFG_GPIO_DIR_SFT)
|
||||
#define RKPM_IO_CFG_GPIO_DIR_OUTPUT \
|
||||
(RKPM_IO_CFG_GPIO_DIR_OUTPUT_VAL << RKPM_IO_CFG_GPIO_DIR_SFT)
|
||||
#define RKPM_IO_CFG_GPIO_LVL_LOW \
|
||||
(RKPM_IO_CFG_GPIO_LVL_LOW_VAL << RKPM_IO_CFG_GPIO_LVL_SFT)
|
||||
#define RKPM_IO_CFG_GPIO_LVL_HIGH \
|
||||
(RKPM_IO_CFG_GPIO_LVL_HIGH_VAL << RKPM_IO_CFG_GPIO_LVL_SFT)
|
||||
#define RKPM_IO_CFG_PULL_NONE \
|
||||
(RKPM_IO_CFG_PULL_NONE_VAL << RKPM_IO_CFG_PULL_SFT)
|
||||
#define RKPM_IO_CFG_PULL_UP \
|
||||
(RKPM_IO_CFG_PULL_UP_VAL << RKPM_IO_CFG_PULL_SFT)
|
||||
#define RKPM_IO_CFG_PULL_DOWN \
|
||||
(RKPM_IO_CFG_PULL_DOWN_VAL << RKPM_IO_CFG_PULL_SFT)
|
||||
#define RKPM_IO_CFG_ID(id) ((id) << RKPM_IO_CFG_ID_SFT)
|
||||
#define RKPM_IO_CFG_IOMUX_GPIO \
|
||||
RKPM_IO_CFG_IOMUX(RKPM_IO_CFG_IOMUX_GPIO_VAL)
|
||||
|
||||
#define RKPM_IO_CFG_GET_IOMUX(cfg) \
|
||||
(((cfg) >> RKPM_IO_CFG_IOMUX_SFT) & RKPM_IO_CFG_IOMUX_MSK)
|
||||
#define RKPM_IO_CFG_GET_GPIO_DIR(cfg) \
|
||||
(((cfg) >> RKPM_IO_CFG_GPIO_DIR_SFT) & RKPM_IO_CFG_GPIO_DIR_MSK)
|
||||
#define RKPM_IO_CFG_GET_GPIO_LVL(cfg) \
|
||||
(((cfg) >> RKPM_IO_CFG_GPIO_LVL_SFT) & RKPM_IO_CFG_GPIO_LVL_MSK)
|
||||
#define RKPM_IO_CFG_GET_PULL(cfg) \
|
||||
(((cfg) >> RKPM_IO_CFG_PULL_SFT) & RKPM_IO_CFG_PULL_MSK)
|
||||
#define RKPM_IO_CFG_GET_ID(cfg) \
|
||||
(((cfg) >> RKPM_IO_CFG_ID_SFT) & RKPM_IO_CFG_ID_MSK)
|
||||
|
||||
#endif
|
||||
@@ -143,6 +143,14 @@ static const struct snd_kcontrol_new rk730_out2_switch =
|
||||
static SOC_ENUM_SINGLE_DECL(ana_ldo_volt_enum, RK730_LDO,
|
||||
4, ana_ldo_volt_text);
|
||||
|
||||
static const char * const adc_sdo_sel_tx_text[] = {
|
||||
"ADCL ADCR", "ADCL ADCR DACL DACR", "ADCL DACL", "ADCL DACR",
|
||||
"ADCR DACL", "ADCR DACR", "DACL DACR",
|
||||
};
|
||||
|
||||
static SOC_ENUM_SINGLE_DECL(adc_sdo_sel_tx_enum, RK730_DI2S_TXCR2,
|
||||
5, adc_sdo_sel_tx_text);
|
||||
|
||||
static int rk730_pll_event(struct snd_soc_dapm_widget *w,
|
||||
struct snd_kcontrol *kcontrol, int event)
|
||||
{
|
||||
@@ -477,6 +485,7 @@ static const struct snd_kcontrol_new rk730_snd_controls[] = {
|
||||
SOC_ENUM("Mic Bias Volt", micbias_volt_enum),
|
||||
SOC_ENUM("DAC HPF Center Freq", dac_hfp_center_freq_enum),
|
||||
SOC_ENUM("ADC CAPACITY TRIM", adc_capacity_trim_enum),
|
||||
SOC_ENUM("ADC SDO SEL TX", adc_sdo_sel_tx_enum),
|
||||
SOC_SINGLE("ADC Volume Bypass Switch", RK730_DTOP_VUCTL, 7, 1, 0),
|
||||
SOC_SINGLE("DAC Volume Bypass Switch", RK730_DTOP_VUCTL, 6, 1, 0),
|
||||
SOC_SINGLE("ADC Fade Switch", RK730_DTOP_VUCTL, 5, 1, 0),
|
||||
@@ -792,26 +801,46 @@ static int rk730_dai_hw_params(struct snd_pcm_substream *substream,
|
||||
dev_info(component->dev, "%s:index %d mclk=%d rate=%d\n",
|
||||
__func__, coeff, coeff_div[coeff].mclk, coeff_div[coeff].rate);
|
||||
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
snd_soc_component_update_bits(component, RK730_DI2S_RXCR2,
|
||||
RK730_DI2S_RXCR2_VDW_MASK,
|
||||
RK730_DI2S_RXCR2_VDW(16));
|
||||
snd_soc_component_update_bits(component, RK730_DI2S_TXCR2,
|
||||
RK730_DI2S_TXCR2_VDW_MASK,
|
||||
RK730_DI2S_TXCR2_VDW(16));
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S24_LE:
|
||||
case SNDRV_PCM_FORMAT_S32_LE:
|
||||
snd_soc_component_update_bits(component, RK730_DI2S_RXCR2,
|
||||
RK730_DI2S_RXCR2_VDW_MASK,
|
||||
RK730_DI2S_RXCR2_VDW(24));
|
||||
snd_soc_component_update_bits(component, RK730_DI2S_TXCR2,
|
||||
RK730_DI2S_TXCR2_VDW_MASK,
|
||||
RK730_DI2S_TXCR2_VDW(24));
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
snd_soc_component_update_bits(component, RK730_DI2S_RXCR2,
|
||||
RK730_DI2S_RXCR2_VDW_MASK,
|
||||
RK730_DI2S_RXCR2_VDW(16));
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S24_LE:
|
||||
snd_soc_component_update_bits(component, RK730_DI2S_RXCR2,
|
||||
RK730_DI2S_RXCR2_VDW_MASK,
|
||||
RK730_DI2S_RXCR2_VDW(24));
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S32_LE:
|
||||
snd_soc_component_update_bits(component, RK730_DI2S_RXCR2,
|
||||
RK730_DI2S_RXCR2_VDW_MASK,
|
||||
RK730_DI2S_RXCR2_VDW(32));
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
} else {
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
snd_soc_component_update_bits(component, RK730_DI2S_TXCR2,
|
||||
RK730_DI2S_TXCR2_VDW_MASK,
|
||||
RK730_DI2S_TXCR2_VDW(16));
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S24_LE:
|
||||
snd_soc_component_update_bits(component, RK730_DI2S_TXCR2,
|
||||
RK730_DI2S_TXCR2_VDW_MASK,
|
||||
RK730_DI2S_TXCR2_VDW(24));
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S32_LE:
|
||||
snd_soc_component_update_bits(component, RK730_DI2S_TXCR2,
|
||||
RK730_DI2S_TXCR2_VDW_MASK,
|
||||
RK730_DI2S_TXCR2_VDW(32));
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
rate = samplerate_to_bit(params_rate(params));
|
||||
|
||||
@@ -520,6 +520,19 @@ static int rk_dsm_pcm_trigger(struct snd_pcm_substream *substream,
|
||||
snd_soc_component_get_drvdata(dai->component);
|
||||
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
case SNDRV_PCM_TRIGGER_RESUME:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
/**
|
||||
* NOTE: Recover DAC volumes and switch RKDSM_ON_FUNC after hw_param()
|
||||
* again, avoid to incorrect silence during recover from XRUN.
|
||||
*/
|
||||
regmap_write(rd->regmap, DACVOLL0, rd->vols.vol_l);
|
||||
regmap_write(rd->regmap, DACVOLR0, rd->vols.vol_r);
|
||||
regmap_write(rd->regmap, DACVOGP, rd->vols.polarity);
|
||||
if (rd->data && rd->data->iomux_switch)
|
||||
rd->data->iomux_switch(rd->dev, RKDSM_ON_FUNC);
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
|
||||
@@ -22,6 +22,8 @@
|
||||
|
||||
#include "rockchip_asrc.h"
|
||||
|
||||
#define RV1126B_ASRC 0x04000000
|
||||
|
||||
/*
|
||||
* structure:
|
||||
* tx: memory->asrc->sai->codec
|
||||
@@ -42,6 +44,7 @@
|
||||
#define MAXBURST_PER_FIFO 8
|
||||
#define DEFAULT_SAMPLE_RATE 48000
|
||||
#define ASRC_DEFAULT_CLK 200000000
|
||||
#define ASRC_LRCK_SOURCE_FREQ_DEFAULT 98304000
|
||||
|
||||
/* Platform Definition */
|
||||
/* rk3576 */
|
||||
@@ -182,7 +185,6 @@ struct rk_asrc_soc_data {
|
||||
int (*lrck_clk_set)(struct device *dev);
|
||||
int (*lrck_clk_en)(struct device *dev);
|
||||
int (*lrck_clk_dis)(struct device *dev);
|
||||
int lrck_source_freq;
|
||||
};
|
||||
|
||||
struct rockchip_asrc_pair {
|
||||
@@ -223,6 +225,9 @@ struct rockchip_asrc {
|
||||
int resample_rate;
|
||||
int dst_link_dai_id; /* This must be set firstly by amixer/tinymixer */
|
||||
int src_link_dai_id; /* This must be set firstly by amixer/tinymixer */
|
||||
int lrck_src_freq;
|
||||
int lrck_dst_freq;
|
||||
int version;
|
||||
};
|
||||
|
||||
static int rockchip_asrc_calculate_ratio(struct rockchip_asrc *asrc,
|
||||
@@ -405,9 +410,15 @@ static int rockchip_asrc_hw_params(struct snd_pcm_substream *substream,
|
||||
asrc->sample_bits = 16;
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S24_LE:
|
||||
val = ASRC_IWL_24BIT | ASRC_OWL_24BIT |
|
||||
ASRC_OFMT_32 | ASRC_IFMT_32 |
|
||||
ASRC_ISJM(0) | ASRC_OSJM(0);
|
||||
asrc->sample_bits = 32;
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S32_LE:
|
||||
val = ASRC_IWL_24BIT | ASRC_OWL_24BIT |
|
||||
ASRC_OFMT_32 | ASRC_IFMT_32;
|
||||
ASRC_OFMT_32 | ASRC_IFMT_32 |
|
||||
ASRC_ISJM(8) | ASRC_OSJM(8);
|
||||
asrc->sample_bits = 32;
|
||||
break;
|
||||
default:
|
||||
@@ -528,6 +539,7 @@ static bool rockchip_asrc_readable_reg(struct device *dev, unsigned int reg)
|
||||
case ASRC_LRCK_MARGIN:
|
||||
case ASRC_FETCH_LEN:
|
||||
case ASRC_DMA_THRESH:
|
||||
case ASRC_LRCK_FILT:
|
||||
case ASRC_INT_CON:
|
||||
case ASRC_INT_ST:
|
||||
case ASRC_ST:
|
||||
@@ -564,6 +576,7 @@ static bool rockchip_asrc_writeable_reg(struct device *dev, unsigned int reg)
|
||||
case ASRC_LRCK_MARGIN:
|
||||
case ASRC_FETCH_LEN:
|
||||
case ASRC_DMA_THRESH:
|
||||
case ASRC_LRCK_FILT:
|
||||
case ASRC_INT_CON:
|
||||
case ASRC_INT_ST:
|
||||
case ASRC_FIFO_IN_WRCNT:
|
||||
@@ -1141,6 +1154,11 @@ static int rockchip_asrc_init(struct rockchip_asrc *asrc)
|
||||
ASRC_RATIO_TRACK_DIV_MSK | ASRC_RATIO_TRACK_PERIOD_MSK,
|
||||
ASRC_RATIO_TRACK_DIV(3) | ASRC_RATIO_TRACK_PERIOD(1023));
|
||||
|
||||
if (asrc->version == RV1126B_ASRC) {
|
||||
regmap_update_bits(asrc->regmap, ASRC_LRCK_FILT,
|
||||
ASRC_LRCK_FILT_MSK, ASRC_LRCK_FILT_DIS);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1290,7 +1308,7 @@ static void rockchip_asrc_lrck_div_set(struct rockchip_asrc *asrc)
|
||||
|
||||
switch (asrc->src_link_dai_id) {
|
||||
case DAI_ID_ASRC0 ... DAI_ID_ASRC15:
|
||||
src_lrck_div = asrc->soc_data->lrck_source_freq / asrc->sample_rate;
|
||||
src_lrck_div = asrc->lrck_src_freq / asrc->sample_rate;
|
||||
break;
|
||||
case DAI_ID_SPDIF_TX0 ... DAI_ID_SPDIF_RX7:
|
||||
src_lrck_div = 128;
|
||||
@@ -1301,7 +1319,7 @@ static void rockchip_asrc_lrck_div_set(struct rockchip_asrc *asrc)
|
||||
|
||||
switch (asrc->dst_link_dai_id) {
|
||||
case DAI_ID_ASRC0 ... DAI_ID_ASRC15:
|
||||
dst_lrck_div = asrc->soc_data->lrck_source_freq / asrc->resample_rate;
|
||||
dst_lrck_div = asrc->lrck_dst_freq / asrc->resample_rate;
|
||||
break;
|
||||
case DAI_ID_SPDIF_TX0 ... DAI_ID_SPDIF_RX7:
|
||||
dst_lrck_div = 128;
|
||||
@@ -1381,19 +1399,24 @@ static int rk3506_asrc_lrck_clk_set(struct device *dev)
|
||||
clk_set_parent(asrc->src_lrck, asrc->src_lrck_parent);
|
||||
clk_set_parent(asrc->dst_lrck, asrc->dst_lrck_parent);
|
||||
if (rockchip_asrc_is_link_mem(asrc->src_link_dai_id)) {
|
||||
if (clk_set_rate(asrc->src_lrck_parent, asrc->soc_data->lrck_source_freq)) {
|
||||
if (clk_set_rate(asrc->src_lrck_parent, asrc->lrck_src_freq)) {
|
||||
dev_err(asrc->dev, "Failed to set src_lrck_parent, freq is %d\n",
|
||||
asrc->soc_data->lrck_source_freq);
|
||||
asrc->lrck_src_freq);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
asrc->lrck_src_freq = clk_get_rate(asrc->src_lrck_parent);
|
||||
}
|
||||
|
||||
if (rockchip_asrc_is_link_mem(asrc->dst_link_dai_id)) {
|
||||
if (clk_set_rate(asrc->dst_lrck_parent, asrc->soc_data->lrck_source_freq)) {
|
||||
if (clk_set_rate(asrc->dst_lrck_parent, asrc->lrck_dst_freq)) {
|
||||
dev_err(asrc->dev, "Failed to set dst_lrck_parent, freq is %d\n",
|
||||
asrc->soc_data->lrck_source_freq);
|
||||
asrc->lrck_dst_freq);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* get the real freq */
|
||||
asrc->lrck_dst_freq = clk_get_rate(asrc->dst_lrck_parent);
|
||||
}
|
||||
|
||||
rockchip_asrc_lrck_div_set(asrc);
|
||||
@@ -1612,19 +1635,23 @@ static int rk3576_asrc_lrck_clk_set(struct device *dev)
|
||||
}
|
||||
|
||||
if (rockchip_asrc_is_link_mem(asrc->src_link_dai_id)) {
|
||||
if (clk_set_rate(asrc->cru_src0, asrc->soc_data->lrck_source_freq)) {
|
||||
if (clk_set_rate(asrc->cru_src0, asrc->lrck_src_freq)) {
|
||||
dev_err(asrc->dev, "Failed to set cru_src0, freq is %d\n",
|
||||
asrc->soc_data->lrck_source_freq);
|
||||
asrc->lrck_src_freq);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
asrc->lrck_src_freq = clk_get_rate(asrc->cru_src0);
|
||||
}
|
||||
|
||||
if (rockchip_asrc_is_link_mem(asrc->dst_link_dai_id)) {
|
||||
if (clk_set_rate(asrc->cru_src1, asrc->soc_data->lrck_source_freq)) {
|
||||
if (clk_set_rate(asrc->cru_src1, asrc->lrck_dst_freq)) {
|
||||
dev_err(asrc->dev, "Failed to set cru_src1, freq is %d\n",
|
||||
asrc->soc_data->lrck_source_freq);
|
||||
asrc->lrck_dst_freq);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
asrc->lrck_dst_freq = clk_get_rate(asrc->cru_src1);
|
||||
}
|
||||
|
||||
rockchip_asrc_lrck_div_set(asrc);
|
||||
@@ -1664,7 +1691,6 @@ static const struct rk_asrc_soc_data rk3506_data = {
|
||||
.lrck_clk_set = rk3506_asrc_lrck_clk_set,
|
||||
.lrck_clk_en = rk3506_asrc_lrck_clk_en,
|
||||
.lrck_clk_dis = rk3506_asrc_lrck_clk_dis,
|
||||
.lrck_source_freq = 98304000,
|
||||
};
|
||||
|
||||
static const struct rk_asrc_soc_data rk3576_data = {
|
||||
@@ -1672,7 +1698,6 @@ static const struct rk_asrc_soc_data rk3576_data = {
|
||||
.lrck_clk_set = rk3576_asrc_lrck_clk_set,
|
||||
.lrck_clk_en = rk3576_asrc_lrck_clk_en,
|
||||
.lrck_clk_dis = rk3576_asrc_lrck_clk_dis,
|
||||
.lrck_source_freq = 49152000,
|
||||
};
|
||||
|
||||
static const struct of_device_id rockchip_asrc_match[] = {
|
||||
@@ -1694,6 +1719,8 @@ static int rockchip_asrc_probe(struct platform_device *pdev)
|
||||
if (!asrc)
|
||||
return -ENOMEM;
|
||||
|
||||
asrc->lrck_src_freq = ASRC_LRCK_SOURCE_FREQ_DEFAULT;
|
||||
asrc->lrck_dst_freq = ASRC_LRCK_SOURCE_FREQ_DEFAULT;
|
||||
asrc->dev = &pdev->dev;
|
||||
asrc->pdev = pdev;
|
||||
dev_set_drvdata(&pdev->dev, asrc);
|
||||
@@ -1770,6 +1797,7 @@ static int rockchip_asrc_probe(struct platform_device *pdev)
|
||||
if (ret < 0)
|
||||
goto err_runtime_suspend;
|
||||
|
||||
regmap_read(asrc->regmap, ASRC_VERSION, &asrc->version);
|
||||
ret = rockchip_asrc_init(asrc);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Asrc init error.\n");
|
||||
|
||||
@@ -23,6 +23,7 @@
|
||||
#define ASRC_LRCK_MARGIN 0x0034
|
||||
#define ASRC_FETCH_LEN 0x0040
|
||||
#define ASRC_DMA_THRESH 0x0050
|
||||
#define ASRC_LRCK_FILT 0x0058
|
||||
#define ASRC_INT_CON 0x0060
|
||||
#define ASRC_INT_ST 0x0064
|
||||
#define ASRC_ST 0x0070
|
||||
@@ -124,6 +125,15 @@
|
||||
#define ASRC_DMA_TX_THRESH_MSK (0xf << 0)
|
||||
#define ASRC_DMA_TX_THRESH(x) (x << 0)
|
||||
|
||||
/**********************ASRC_LRCK_FILT************************/
|
||||
#define ASRC_LRCK_DRIFT_MARGIN_MSK (0x7ff << 0)
|
||||
#define ASRC_LRCK_DRIFT_MARGIN(x) (x << 0)
|
||||
#define ASRC_LRCK_SUPER_MARGIN_MSK (0x7ff << 16)
|
||||
#define ASRC_LRCK_SUPER_MARGIN(x) (x << 16)
|
||||
#define ASRC_LRCK_FILT_MSK (0x1 << 31)
|
||||
#define ASRC_LRCK_FILT_EN (0x1 << 31)
|
||||
#define ASRC_LRCK_FILT_DIS (0x0 << 31)
|
||||
|
||||
/**********************ASRC_INT_CON************************/
|
||||
#define ASRC_DST_LRCK_UNLOCK_MSK (0x1 << 12)
|
||||
#define ASRC_DST_LRCK_UNLOCK_EN (0x1 << 12)
|
||||
|
||||
Reference in New Issue
Block a user