shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 03:15:31 +09:00
Code Issues Packages Projects Releases Wiki Activity

phy: rockchip: naneng-combphy: Fix PCIe system PM

Browse Source 
combophy relies on rockchip,pcie1ln-sel-bits to specify
lane mux for each devices. During system PM, genpd will
be turned off, so lane mux information will lost. So we'd
better move it to rockchip_combphy_pcie_init() as it will
be called both for probing and resuming.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I69a0754d7f67a95d97bde71ef629135a59a2c64b
This commit is contained in:
Shawn Lin
2021-12-03 15:27:41 +08:00
committed by Tao Huang
parent a5f5019da0
commit 33d95b67b3
1 changed files with 11 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
View File

@@ -19,6 +19,7 @@
#include <dt-bindings/phy/phy.h>
#define BIT_WRITEABLE_SHIFT 16
#define PCIE_NO_MUX_SEL 0xffff
struct rockchip_combphy_priv;
@@ -74,6 +75,7 @@ struct rockchip_combphy_cfg {
struct rockchip_combphy_priv {
u8 mode;
u32 mux_sel_bits[4];
void __iomem *mmio;
int num_clks;
struct clk_bulk_data *clks;
@@ -132,6 +134,11 @@ static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv)
{
int ret = 0;
if (priv->mux_sel_bits[0] != PCIE_NO_MUX_SEL)
regmap_write(priv->pipe_grf, priv->mux_sel_bits[0],
(GENMASK(priv->mux_sel_bits[2], priv->mux_sel_bits[1]) << 16) |
priv->mux_sel_bits[3]);
if (priv->cfg->combphy_cfg) {
ret = priv->cfg->combphy_cfg(priv);
if (ret) {
@@ -289,7 +296,6 @@ static int rockchip_combphy_parse_dt(struct device *dev,
{
const struct rockchip_combphy_cfg *phy_cfg = priv->cfg;
int ret, mac_id;
u32 vals[4];
ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
if (ret == -EPROBE_DEFER)
@@ -323,10 +329,10 @@ static int rockchip_combphy_parse_dt(struct device *dev,
param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel,
true);
if (!device_property_read_u32_array(dev, "rockchip,pcie1ln-sel-bits",
vals, ARRAY_SIZE(vals)))
regmap_write(priv->pipe_grf, vals[0],
(GENMASK(vals[2], vals[1]) << 16) | vals[3]);
priv->mux_sel_bits[0] = PCIE_NO_MUX_SEL;
device_property_read_u32_array(dev, "rockchip,pcie1ln-sel-bits",
priv->mux_sel_bits,
ARRAY_SIZE(priv->mux_sel_bits));
priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb");
if (IS_ERR(priv->apb_rst)) {