mirror of
https://github.com/hardkernel/linux.git
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ARM64: dts: rk3399: sort nodes and fix spi reg
Change-Id: Icb71adf3ebfcee57be46886672a0fe1afe77473f Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
This commit is contained in:
Huang, Tao
committed by
Gerrit Code Review
Gerrit Code Review
parent
e63146d4cf
commit
33edbc6b60
@@ -156,27 +156,6 @@
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clock-output-names = "xin24m";
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};
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gic: interrupt-controller@fee00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
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<0x0 0xfef00000 0 0xc0000>, /* GICR */
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<0x0 0xfff00000 0 0x10000>, /* GICC */
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<0x0 0xfff10000 0 0x10000>, /* GICH */
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<0x0 0xfff20000 0 0x10000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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its: interrupt-controller@fee20000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0xfee20000 0x0 0x20000>;
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};
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};
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <2>;
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@@ -204,6 +183,106 @@
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};
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};
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emmc_phy: phy {
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compatible = "rockchip,rk3399-emmc-phy";
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reg-offset = <0xf780>;
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#phy-cells = <0>;
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rockchip,grf = <&grf>;
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status = "disabled";
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};
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sdio0: dwmmc@fe310000 {
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compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xfe310000 0x0 0x4000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
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<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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status = "disabled";
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};
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sdmmc: dwmmc@fe320000 {
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compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xfe320000 0x0 0x4000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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status = "disabled";
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};
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sdhci: sdhci@fe330000 {
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compatible = "arasan,sdhci-5.1";
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reg = <0x0 0xfe330000 0x0 0x10000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
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clock-names = "clk_xin", "clk_ahb";
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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status = "disabled";
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};
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usb_host0_echi: usb@fe380000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfe380000 0x0 0x20000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST0>;
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clock-names = "hclk_host0";
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status = "disabled";
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};
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usb_host0_ohci: usb@fe3a0000 {
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compatible = "generic-ohci";
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reg = <0x0 0xfe3a0000 0x0 0x20000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST0>;
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clock-names = "hclk_host0";
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status = "disabled";
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};
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usb_host1_echi: usb@fe3c0000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfe3c0000 0x0 0x20000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST1>;
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clock-names = "hclk_host1";
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status = "disabled";
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};
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usb_host1_ohci: usb@fe3e0000 {
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compatible = "generic-ohci";
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reg = <0x0 0xfe3e0000 0x0 0x20000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST1>;
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clock-names = "hclk_host1";
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status = "disabled";
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};
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gic: interrupt-controller@fee00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
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<0x0 0xfef00000 0 0xc0000>, /* GICR */
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<0x0 0xfff00000 0 0x10000>, /* GICC */
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<0x0 0xfff10000 0 0x10000>, /* GICH */
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<0x0 0xfff20000 0 0x10000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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its: interrupt-controller@fee20000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0xfee20000 0x0 0x20000>;
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};
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};
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saradc: saradc@ff100000 {
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compatible = "rockchip,rk3399-saradc";
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reg = <0x0 0xff100000 0x0 0x100>;
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@@ -305,49 +384,6 @@
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status = "disabled";
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};
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emmc_phy: phy {
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compatible = "rockchip,rk3399-emmc-phy";
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reg-offset = <0xf780>;
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#phy-cells = <0>;
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rockchip,grf = <&grf>;
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status = "disabled";
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};
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sdio0: dwmmc@fe310000 {
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compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xfe310000 0x0 0x4000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
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<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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status = "disabled";
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};
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sdmmc: dwmmc@fe320000 {
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compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xfe320000 0x0 0x4000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clock-freq-min-max = <400000 150000000>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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fifo-depth = <0x100>;
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status = "disabled";
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};
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sdhci: sdhci@fe330000 {
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compatible = "arasan,sdhci-5.1";
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reg = <0x0 0xfe330000 0x0 0x10000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
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clock-names = "clk_xin", "clk_ahb";
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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status = "disabled";
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};
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uart0: serial@ff180000 {
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compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
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reg = <0x0 0xff180000 0x0 0x100>;
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@@ -394,7 +430,7 @@
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spi0: spi@ff1c0000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff110000 0x0 0x1000>;
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reg = <0x0 0xff1c0000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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@@ -407,7 +443,7 @@
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spi1: spi@ff1d0000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff120000 0x0 0x1000>;
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reg = <0x0 0xff1d0000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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@@ -420,7 +456,7 @@
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spi2: spi@ff1e0000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff130000 0x0 0x1000>;
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reg = <0x0 0xff1e0000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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@@ -433,7 +469,7 @@
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spi4: spi@ff1f0000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff120000 0x0 0x1000>;
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reg = <0x0 0xff1f0000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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@@ -446,7 +482,7 @@
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spi5: spi@ff200000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff130000 0x0 0x1000>;
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reg = <0x0 0xff200000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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@@ -478,6 +514,68 @@
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status = "disabled";
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};
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pmu: power-management@ff31000 {
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compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
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reg = <0x0 0xff310000 0x0 0x1000>;
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power: power-controller {
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status = "disabled";
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compatible = "rockchip,rk3399-power-controller";
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#power-domain-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_center {
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reg = <RK3399_PD_CENTER>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_vdu {
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reg = <RK3399_PD_VDU>;
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};
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pd_vcodec {
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reg = <RK3399_PD_VCODEC>;
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};
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pd_iep {
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reg = <RK3399_PD_IEP>;
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};
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pd_rga {
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reg = <RK3399_PD_RGA>;
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};
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};
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pd_vio {
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reg = <RK3399_PD_VIO>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_isp0 {
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reg = <RK3399_PD_ISP0>;
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};
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pd_isp1 {
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reg = <RK3399_PD_ISP1>;
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};
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pd_hdcp {
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reg = <RK3399_PD_HDCP>;
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};
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pd_vo {
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reg = <RK3399_PD_VO>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_vopb {
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reg = <RK3399_PD_VOPB>;
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};
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pd_vopl {
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reg = <RK3399_PD_VOPL>;
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};
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};
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};
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pd_gpu {
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reg = <RK3399_PD_GPU>;
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};
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};
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};
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pmugrf: syscon@ff320000 {
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compatible = "rockchip,rk3399-pmugrf", "syscon";
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reg = <0x0 0xff320000 0x0 0x1000>;
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@@ -485,7 +583,7 @@
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spi3: spi@ff350000 {
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compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
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reg = <0x0 0xff110000 0x0 0x1000>;
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reg = <0x0 0xff350000 0x0 0x1000>;
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clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
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clock-names = "spiclk", "apb_pclk";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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@@ -507,42 +605,6 @@
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status = "disabled";
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};
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usb_host0_echi: usb@fe380000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfe380000 0x0 0x20000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST0>;
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clock-names = "hclk_host0";
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status = "disabled";
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};
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usb_host0_ohci: usb@fe3a0000 {
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compatible = "generic-ohci";
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reg = <0x0 0xfe3a0000 0x0 0x20000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST0>;
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clock-names = "hclk_host0";
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status = "disabled";
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};
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usb_host1_echi: usb@fe3c0000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfe3c0000 0x0 0x20000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST1>;
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clock-names = "hclk_host1";
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status = "disabled";
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};
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usb_host1_ohci: usb@fe3e0000 {
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compatible = "generic-ohci";
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reg = <0x0 0xfe3e0000 0x0 0x20000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST1>;
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clock-names = "hclk_host1";
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status = "disabled";
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};
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i2c4: i2c@ff3d0000 {
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compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
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reg = <0x0 0xff3d0000 0x0 0x1000>;
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@@ -613,68 +675,6 @@
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status = "disabled";
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};
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pmu: power-management@ff731000 {
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compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
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reg = <0x0 0xff310000 0x0 0x1000>;
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power: power-controller {
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status = "disabled";
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compatible = "rockchip,rk3399-power-controller";
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#power-domain-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_center {
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reg = <RK3399_PD_CENTER>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_vdu {
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reg = <RK3399_PD_VDU>;
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};
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pd_vcodec {
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reg = <RK3399_PD_VCODEC>;
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};
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pd_iep {
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reg = <RK3399_PD_IEP>;
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};
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pd_rga {
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reg = <RK3399_PD_RGA>;
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};
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};
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pd_vio {
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reg = <RK3399_PD_VIO>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_isp0 {
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reg = <RK3399_PD_ISP0>;
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};
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pd_isp1 {
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reg = <RK3399_PD_ISP1>;
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};
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pd_hdcp {
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reg = <RK3399_PD_HDCP>;
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};
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pd_vo {
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reg = <RK3399_PD_VO>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_vopb {
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reg = <RK3399_PD_VOPB>;
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};
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pd_vopl {
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reg = <RK3399_PD_VOPL>;
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};
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};
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};
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pd_gpu {
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reg = <RK3399_PD_GPU>;
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};
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};
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};
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pmucru: pmu-clock-controller@ff750000 {
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compatible = "rockchip,rk3399-pmucru";
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reg = <0x0 0xff750000 0x0 0x1000>;
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