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phy: rockchip: csi2-dphy: fixed logic error about clk1_en

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Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I03dc62115346a5908d27ecf83b1705a96dc4bd53
This commit is contained in:
Zefa Chen
2022-07-14 10:43:33 +08:00
committed by Tao Huang
parent e96b693e05
commit 3417af9ec0
1 changed files with 3 additions and 1 deletions
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4
drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c
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@@ -414,6 +414,7 @@ static const struct csi2dphy_reg rv1106_csi2dphy_regs[] = {
[CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
[CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
[CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
[CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
[CSI2PHY_PATH0_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH0_MODE_SEL),
[CSI2PHY_PATH0_LVDS_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH0_LVDS_MODE_SEL),
[CSI2PHY_PATH1_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH1_MODE_SEL),
@@ -637,7 +638,8 @@ static int csi2_dphy_hw_stream_on(struct csi2_dphy *dphy,
if (dphy->phy_index % 3 == DPHY2) {
val |= (GENMASK(sensor->lanes - 1, 0) <<
CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT);
write_csi2_dphy_reg(hw, CSI2PHY_CLK1_LANE_ENABLE, BIT(6));
if (hw->drv_data->chip_id >= CHIP_ID_RK3588)
write_csi2_dphy_reg(hw, CSI2PHY_CLK1_LANE_ENABLE, BIT(6));
}
}
val |= pre_val;