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spicc: add dma and enhance features of axg/txhd/g12a/g12b.

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PD#164751: spicc: add dma and enhance features of axg/txhd/g12a/g12b.

1. fix TESTREG bits defination error;
2. fix cs-gpio error in slave setup;
3. reset fifo to avoid successive fifo error before tansfer;
4. add enhance feature of cs-preload delay control;
5. add auto io delay control;
6. add enhance feature of tt/ti delay control;
7. fix clk error which occurred certainly when sencond spicc added;
8. surpport both auto core clk and  fixed core clk rate setting:
   set dts "fixed_core_rate = <200000000(example)>" to use fixed
   core rate. otherwise, to use auto core clk.
9. support loop-back mode;
10. support DMA transfer;
11. must delete 1000M from parent clk.
12. It will be wrong when enhance divider=2. we have to add a flag
   CLK_DIVIDER_PROHIBIT_ZERO to shield against it.

Change-Id: I820a52e6d31d3fe2e3615a0f4c5a07c17d11914d
Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
This commit is contained in:
Sunny Luo
2018-04-28 10:15:15 +08:00
parent 7ef26fb586
commit 34616dd660
2 changed files with 623 additions and 291 deletions
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53
Documentation/devicetree/bindings/spi/spi-meson.txt
View File

@@ -31,6 +31,9 @@ Required properties:
"amlogic,meson-gx-spicc" on Amlogic GX and compatible SoCs.
"amlogic,meson-txlx-spicc" on Amlogic TXLX and compatible SoCs
"amlogic,meson-axg-spicc" on Amlogic AXG and compatible SoCs
"amlogic,meson-g12a-spicc" on Amlogic G12A and compatible SoCs
"amlogic,meson-g12b-spicc", "amlogic,meson-g12a-spicc"
on Amlogic G12B and compatible SoCs
- reg: physical base address and length of the controller registers
- interrupts: The interrupt specifier
- clock-names: Must contain "core"
@@ -55,7 +58,7 @@ Example :
#size-cells = <0>;
};
spicc_a: spi@13000 {
spicc0: spi@13000 {
compatible = "amlogic,meson-txlx-spicc";
reg = <0x0 0x13000 0x0 0x3c>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -63,16 +66,56 @@ Example :
clock-names = "core";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spicc_b: spi@15000 {
spicc1: spi@15000 {
compatible = "amlogic,meson-txlx-spicc";
reg = <0x0 0x15000 0x0 0x3c>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC1>;
clock-names = "core";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spicc0: spi@13000 {
compatible = "amlogic,meson-axg-spicc";
reg = <0x0 0x13000 0x0 0x40>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC0>,
<&clkc CLKID_SPICC_COMP>;
clock-names = "core", "delay";
#address-cells = <1>;
#size-cells = <0>;
};
spicc1: spi@15000 {
compatible = "amlogic,meson-axg-spicc";
reg = <0x0 0x15000 0x0 0x40>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC1>,
<&clkc CLKID_SPICC_COMP>;
clock-names = "core", "delay";
#address-cells = <1>;
#size-cells = <0>;
};
spicc0: spi@13000 {
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0x13000 0x0 0x40>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC0_COMP>;
clock-names = "core";
#address-cells = <1>;
#size-cells = <0>;
};
spicc1: spi@15000 {
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0x15000 0x0 0x40>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC1_COMP>;
clock-names = "core";
#address-cells = <1>;
#size-cells = <0>;
};

861
drivers/spi/spi-meson-spicc.c
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