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https://github.com/hardkernel/linux.git
synced 2026-06-08 11:50:43 +09:00
add dma pl330 memcpy test
This commit is contained in:
hhb
@@ -166,5 +166,9 @@ config RK_PL330_DMA
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select PL330
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help
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DMA API Driver for PL330 DMAC
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config RK_PL330_DMA_TEST
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bool "pl330 DMA memcpy test"
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depends on RK_PL330_DMA
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endif
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@@ -2,6 +2,7 @@ obj-$(CONFIG_RK29_LAST_LOG) += last_log.o
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obj-$(CONFIG_USB_GADGET) += usb_detect.o
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obj-$(CONFIG_RK29_VPU) += vpu_service.o
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obj-$(CONFIG_RK_PL330_DMA) += dma-pl330.o
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obj-$(CONFIG_RK_PL330_DMA_TEST) += dma_memcpy_test.o
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obj-$(CONFIG_FIQ) += fiq.o
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obj-$(CONFIG_FIQ_DEBUGGER) += rk_fiq_debugger.o
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obj-$(CONFIG_RK_EARLY_PRINTK) += early_printk.o ../kernel/debug.o
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235
arch/arm/plat-rk/dma_memcpy_test.c
Normal file
235
arch/arm/plat-rk/dma_memcpy_test.c
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@@ -0,0 +1,235 @@
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/*
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*
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* arch/arm/plat-rk/dma_memcpy_test.c
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*
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* Copyright (C) 2012 Rochchip.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* Author: hhb@rock-chips.com
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* Date: 2012.03.26
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*
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* HOW TO USE IT?
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* enter the follow command at command line
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* echo 1 > sys/module/dma_memcpy_test/parameters/debug enable log output,default is enable
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* echo 1 > sys/module/dma_memcpy_test/parameters/dmac1 set dmac1 memcpy
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* echo 1 > sys/module/dma_memcpy_test/parameters/dmac2 set dmac2 memcpy
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* echo 1000 > sys/module/dma_memcpy_test/parameters/interval set dma transfer interval, default is 1000ms
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* echo 1 > /sys/devices/platform/dma_memcpy.0/dmamemcpy to start the dma test
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*
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*/
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/wait.h>
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#include <linux/sched.h>
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#include <linux/delay.h>
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#include <mach/io.h>
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#include <plat/dma-pl330.h>
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#include <asm/uaccess.h>
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#include <asm/current.h>
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#define DMA_TEST_BUFFER_SIZE 4096
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static DECLARE_WAIT_QUEUE_HEAD(wq);
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static int wq_condition = 0;
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struct Dma_MemToMem {
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dma_addr_t SrcAddr; //phy address
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dma_addr_t DstAddr;
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unsigned char* src; //virtual address
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unsigned char* dst;
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int MenSize;
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};
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//wait_queue_head_t dma_memcpy_wait;
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//enable log output
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static int debug = 1;
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module_param(debug,int,S_IRUGO|S_IWUSR);
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//set dma transfer interval time (unit ms)
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static int interval = 1000;
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module_param(interval,int,S_IRUGO|S_IWUSR);
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static int dmac1 = 1;
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module_param(dmac1,int,S_IRUGO|S_IWUSR);
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static int dmac2 = -1;
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module_param(dmac2,int,S_IRUGO|S_IWUSR);
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static struct Dma_MemToMem DmaMemInfo1;
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static struct Dma_MemToMem DmaMemInfo2;
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#define MEMCPY_DMA_DBG(fmt...) {if(debug > 0) printk(fmt);}
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static struct rk29_dma_client rk29_dma_memcpy_client = {
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.name = "rk29-dma-memcpy",
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};
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static void rk29_dma_memcpy_callback1(void *buf_id, int size, enum rk29_dma_buffresult result)
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{
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if(result != RK29_RES_OK){
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return;
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}
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MEMCPY_DMA_DBG("rk29_dma_memcpy_callback1 ok\n");
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if(wq_condition == 0){
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wq_condition = 1;
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wake_up_interruptible(&wq);
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}
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//wake_up_interruptible(&dma_memcpy_wait);
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}
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static void rk29_dma_memcpy_callback2(void *buf_id, int size, enum rk29_dma_buffresult result)
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{
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if(result != RK29_RES_OK){
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return;
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}
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MEMCPY_DMA_DBG("rk29_dma_memcpy_callback2 ok\n");
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if(wq_condition == 0){
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wq_condition = 1;
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wake_up_interruptible(&wq);
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}
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//wake_up_interruptible(&dma_memcpy_wait);
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}
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//int slecount = 0;
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static ssize_t memcpy_dma_read(struct device *device,struct device_attribute *attr, char *argv)
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{
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return 0;
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}
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static ssize_t memcpy_dma_write(struct device *device, struct device_attribute *attr, const char *argv, size_t count)
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{
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int rt, i;
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// struct Dma_MemToMem *DmaMemInfo1 = (struct Dma_MemToMem *)argv;
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MEMCPY_DMA_DBG("memcpy_dma_write\n");
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//dmac1
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if(dmac1 > 0) {
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memset(DmaMemInfo1.src, 0x55, DMA_TEST_BUFFER_SIZE);
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memset(DmaMemInfo1.dst, 0x0, DMA_TEST_BUFFER_SIZE);
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rt = rk29_dma_devconfig(DMACH_DMAC1_MEMTOMEM, RK29_DMASRC_MEMTOMEM, DmaMemInfo1.SrcAddr);
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rt = rk29_dma_enqueue(DMACH_DMAC1_MEMTOMEM, NULL, DmaMemInfo1.DstAddr, DmaMemInfo1.MenSize);
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rt = rk29_dma_ctrl(DMACH_DMAC1_MEMTOMEM, RK29_DMAOP_START);
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}
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//dmac2
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if(dmac2 > 0) {
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memset(DmaMemInfo2.src, 0xaa, DMA_TEST_BUFFER_SIZE);
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memset(DmaMemInfo2.dst, 0x0, DMA_TEST_BUFFER_SIZE);
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rt = rk29_dma_devconfig(DMACH_DMAC2_MEMTOMEM, RK29_DMASRC_MEMTOMEM, DmaMemInfo2.SrcAddr);
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rt = rk29_dma_enqueue(DMACH_DMAC2_MEMTOMEM, NULL, DmaMemInfo2.DstAddr, DmaMemInfo2.MenSize);
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rt = rk29_dma_ctrl(DMACH_DMAC2_MEMTOMEM, RK29_DMAOP_START);
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}
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if(dmac2 > 0 || dmac1 > 0)
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wait_event_interruptible_timeout(wq, wq_condition, 500);
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if(dmac1 > 0) {
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for(i = 0; i < 16; i++) {
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MEMCPY_DMA_DBG("dmac1 src1:%x", *(DmaMemInfo1.src + i*(DMA_TEST_BUFFER_SIZE/16)));
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MEMCPY_DMA_DBG(" -> dst1:%x\n", *(DmaMemInfo1.dst + i*(DMA_TEST_BUFFER_SIZE/16)));
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}
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}
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if(dmac2 > 0) {
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for(i = 0; i < 16; i++) {
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MEMCPY_DMA_DBG("dmac2 src2:%x", *(DmaMemInfo2.src + i*(DMA_TEST_BUFFER_SIZE/16)));
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MEMCPY_DMA_DBG(" -> dst2:%x\n", *(DmaMemInfo2.dst + i*(DMA_TEST_BUFFER_SIZE/16)));
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}
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}
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msleep(interval);
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wq_condition = 0;
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//init_waitqueue_head(&dma_memcpy_wait);
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//interruptible_sleep_on(&dma_memcpy_wait);
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return 0;
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}
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static DEVICE_ATTR(dmamemcpy, S_IRUGO|S_IALLUGO, memcpy_dma_read, memcpy_dma_write);
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static int __devinit dma_memcpy_probe(struct platform_device *pdev)
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{
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int ret;
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ret = device_create_file(&pdev->dev, &dev_attr_dmamemcpy);
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printk(">>>>>>>>>>>>>>>>>>>>> dam_test_probe <<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
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//dmac1
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if (rk29_dma_request(DMACH_DMAC1_MEMTOMEM, &rk29_dma_memcpy_client, NULL) == -EBUSY) {
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printk("DMACH_DMAC1_MEMTOMEM request fail\n");
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} else {
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rk29_dma_config(DMACH_DMAC1_MEMTOMEM, 8, 16);
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rk29_dma_set_buffdone_fn(DMACH_DMAC1_MEMTOMEM, rk29_dma_memcpy_callback1);
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DmaMemInfo1.src = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo1.SrcAddr, GFP_KERNEL);
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DmaMemInfo1.dst = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo1.DstAddr, GFP_KERNEL);
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DmaMemInfo1.MenSize = DMA_TEST_BUFFER_SIZE;
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printk("DMACH_DMAC1_MEMTOMEM request sucess\n");
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}
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//dmac2
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if (rk29_dma_request(DMACH_DMAC2_MEMTOMEM, &rk29_dma_memcpy_client, NULL) == -EBUSY) {
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printk("DMACH_DMAC2_MEMTOMEM request fail\n");
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} else {
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rk29_dma_config(DMACH_DMAC2_MEMTOMEM, 8, 16);
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rk29_dma_set_buffdone_fn(DMACH_DMAC2_MEMTOMEM, rk29_dma_memcpy_callback2);
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DmaMemInfo2.src = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo2.SrcAddr, GFP_KERNEL);
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DmaMemInfo2.dst = dma_alloc_coherent(NULL, DMA_TEST_BUFFER_SIZE, &DmaMemInfo2.DstAddr, GFP_KERNEL);
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DmaMemInfo2.MenSize = DMA_TEST_BUFFER_SIZE;
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printk("DMACH_DMAC2_MEMTOMEM request sucess\n");
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}
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return 0;
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}
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static int __devexit dma_memcpy_remove(struct platform_device *pdev)
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{
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device_remove_file(&pdev->dev, &dev_attr_dmamemcpy);
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return 0;
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}
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static struct platform_driver dma_mempcy_driver = {
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.driver = {
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.name = "dma_memcpy",
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.owner = THIS_MODULE,
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},
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.probe = dma_memcpy_probe,
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.remove = __devexit_p(dma_memcpy_remove),
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};
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struct platform_device rk29_device_dma_cpy = {
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.name = "dma_memcpy",
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.id = 0,
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};
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static int __init dma_test_init(void)
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{
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platform_device_register(&rk29_device_dma_cpy);
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return platform_driver_register(&dma_mempcy_driver);
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}
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static void __exit dma_test_exit(void)
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{
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platform_driver_unregister(&dma_mempcy_driver);
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}
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late_initcall(dma_test_init);
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module_exit(dma_test_exit);
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MODULE_DESCRIPTION("RK29 PL330 Dma Test Deiver");
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MODULE_LICENSE("GPL V2");
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MODULE_AUTHOR("ZhenFu Fang <fzf@rock-chips.com>");
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