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Merge tag 'v6.6.76' of git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable into odroid-6.6.y

Browse Source 
This is the 6.6.76 stable release

Change-Id: I6256e80e6e212a19ef3a83c9fc567e2b018a9ae8
This commit is contained in:
Mauro Ribeiro
2025-02-11 12:05:28 -03:00
parent 533ede1348 ef3ce4bf49
commit 34f71e82dc
454 changed files with 4493 additions and 3372 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml
View File

@@ -27,7 +27,7 @@ properties:
description: |
For multicolor LED support this property should be defined as either
LED_COLOR_ID_RGB or LED_COLOR_ID_MULTI which can be found in
include/linux/leds/common.h.
include/dt-bindings/leds/common.h.
enum: [ 8, 9 ]
required:

20
Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml
View File

@@ -50,15 +50,15 @@ properties:
minimum: 0
maximum: 1
rohm,charger-sense-resistor-ohms:
minimum: 10000000
maximum: 50000000
rohm,charger-sense-resistor-micro-ohms:
minimum: 10000
maximum: 50000
description: |
BD71827 and BD71828 have SAR ADC for measuring charging currents.
External sense resistor (RSENSE in data sheet) should be used. If
something other but 30MOhm resistor is used the resistance value
should be given here in Ohms.
default: 30000000
BD71815 has SAR ADC for measuring charging currents. External sense
resistor (RSENSE in data sheet) should be used. If something other
but a 30 mOhm resistor is used the resistance value should be given
here in micro Ohms.
default: 30000
regulators:
$ref: ../regulator/rohm,bd71815-regulator.yaml
@@ -67,7 +67,7 @@ properties:
gpio-reserved-ranges:
description: |
Usage of BD71828 GPIO pins can be changed via OTP. This property can be
Usage of BD71815 GPIO pins can be changed via OTP. This property can be
used to mark the pins which should not be configured for GPIO. Please see
the ../gpio/gpio.txt for more information.
@@ -113,7 +113,7 @@ examples:
gpio-controller;
#gpio-cells = <2>;
rohm,charger-sense-resistor-ohms = <10000000>;
rohm,charger-sense-resistor-micro-ohms = <10000>;
regulators {
buck1: buck1 {

2
Documentation/devicetree/bindings/mmc/mmc-controller.yaml
View File

@@ -25,7 +25,7 @@ properties:
"#address-cells":
const: 1
description: |
The cell is the slot ID if a function subnode is used.
The cell is the SDIO function number if a function subnode is used.
"#size-cells":
const: 0

6
Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml
View File

@@ -31,10 +31,6 @@ properties:
$ref: regulator.yaml#
unevaluatedProperties: false
properties:
regulator-compatible:
pattern: "^vbuck[1-4]$"
additionalProperties: false
required:
@@ -52,7 +48,6 @@ examples:
regulators {
vbuck1 {
regulator-compatible = "vbuck1";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
@@ -60,7 +55,6 @@ examples:
};
vbuck3 {
regulator-compatible = "vbuck3";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;

4
Makefile
View File

@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 6
PATCHLEVEL = 6
SUBLEVEL = 75
SUBLEVEL = 76
EXTRAVERSION =
NAME = Pinguïn Aangedreven
@@ -518,7 +518,7 @@ KGZIP = gzip
KBZIP2 = bzip2
KLZOP = lzop
LZMA = lzma
LZ4 = lz4c
LZ4 = lz4
XZ = xz
ZSTD = zstd

24
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
View File

@@ -284,12 +284,12 @@
&i2c11 {
status = "okay";
power-sensor@10 {
compatible = "adi, adm1272";
compatible = "adi,adm1272";
reg = <0x10>;
};
power-sensor@12 {
compatible = "adi, adm1272";
compatible = "adi,adm1272";
reg = <0x12>;
};
@@ -454,22 +454,20 @@
};
pwm@20{
compatible = "max31790";
compatible = "maxim,max31790";
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
};
gpio@22{
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
pwm@23{
compatible = "max31790";
compatible = "maxim,max31790";
reg = <0x23>;
#address-cells = <1>;
#size-cells = <0>;
};
adc@33 {
@@ -504,22 +502,20 @@
};
pwm@20{
compatible = "max31790";
compatible = "maxim,max31790";
reg = <0x20>;
#address-cells = <1>;
#size-cells = <0>;
};
gpio@22{
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
pwm@23{
compatible = "max31790";
compatible = "maxim,max31790";
reg = <0x23>;
#address-cells = <1>;
#size-cells = <0>;
};
adc@33 {

6
arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
View File

@@ -440,7 +440,7 @@
clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
reset-names = "stmmaceth", "ahb";
reset-names = "stmmaceth", "stmmaceth-ocp";
snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
@@ -460,7 +460,7 @@
clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
reset-names = "stmmaceth", "ahb";
reset-names = "stmmaceth", "stmmaceth-ocp";
snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
@@ -480,7 +480,7 @@
clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
reset-names = "stmmaceth", "ahb";
reset-names = "stmmaceth", "stmmaceth-ocp";
snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};

2
arch/arm/boot/dts/mediatek/mt7623.dtsi
View File

@@ -308,7 +308,7 @@
clock-names = "spi", "wrap";
};
cir: cir@10013000 {
cir: ir-receiver@10013000 {
compatible = "mediatek,mt7623-cir";
reg = <0 0x10013000 0 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;

2
arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts
View File

@@ -197,7 +197,7 @@
&sdmmc0 {
bus-width = <4>;
mmc-ddr-3_3v;
no-1-8-v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";

2
arch/arm/boot/dts/st/stm32mp151.dtsi
View File

@@ -1165,7 +1165,7 @@
reg = <0x4c001000 0x400>;
st,proc-id = <0>;
interrupts-extended =
<&exti 61 1>,
<&exti 61 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rx", "tx";
clocks = <&rcc IPCC>;

12
arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi
View File

@@ -6,18 +6,6 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
/ {
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&adc {
status = "disabled";
};

10
arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi
View File

@@ -7,16 +7,6 @@
#include <dt-bindings/pwm/pwm.h>
/ {
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
clk_ext_audio_codec: clock-codec {
compatible = "fixed-clock";
#clock-cells = <0>;

10
arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi
View File

@@ -7,16 +7,6 @@
#include <dt-bindings/pwm/pwm.h>
/ {
aliases {
serial0 = &uart4;
serial1 = &usart3;
serial2 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
led {
compatible = "gpio-leds";

7
arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi
View File

@@ -14,6 +14,13 @@
ethernet1 = &ksz8851;
rtc0 = &hwrtc;
rtc1 = &rtc;
serial0 = &uart4;
serial1 = &uart8;
serial2 = &usart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@c0000000 {

31
arch/arm/mach-at91/pm.c
View File

@@ -591,7 +591,21 @@ static int at91_suspend_finish(unsigned long val)
return 0;
}
static void at91_pm_switch_ba_to_vbat(void)
/**
* at91_pm_switch_ba_to_auto() - Configure Backup Unit Power Switch
* to automatic/hardware mode.
*
* The Backup Unit Power Switch can be managed either by software or hardware.
* Enabling hardware mode allows the automatic transition of power between
* VDDANA (or VDDIN33) and VDDBU (or VBAT, respectively), based on the
* availability of these power sources.
*
* If the Backup Unit Power Switch is already in automatic mode, no action is
* required. If it is in software-controlled mode, it is switched to automatic
* mode to enhance safety and eliminate the need for toggling between power
* sources.
*/
static void at91_pm_switch_ba_to_auto(void)
{
unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu);
unsigned int val;
@@ -602,24 +616,19 @@ static void at91_pm_switch_ba_to_vbat(void)
val = readl(soc_pm.data.sfrbu + offset);
/* Already on VBAT. */
if (!(val & soc_pm.sfrbu_regs.pswbu.state))
/* Already on auto/hardware. */
if (!(val & soc_pm.sfrbu_regs.pswbu.ctrl))
return;
val &= ~soc_pm.sfrbu_regs.pswbu.softsw;
val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl;
val &= ~soc_pm.sfrbu_regs.pswbu.ctrl;
val |= soc_pm.sfrbu_regs.pswbu.key;
writel(val, soc_pm.data.sfrbu + offset);
/* Wait for update. */
val = readl(soc_pm.data.sfrbu + offset);
while (val & soc_pm.sfrbu_regs.pswbu.state)
val = readl(soc_pm.data.sfrbu + offset);
}
static void at91_pm_suspend(suspend_state_t state)
{
if (soc_pm.data.mode == AT91_PM_BACKUP) {
at91_pm_switch_ba_to_vbat();
at91_pm_switch_ba_to_auto();
cpu_suspend(0, at91_suspend_finish);

2
arch/arm/mach-omap1/board-nokia770.c
View File

@@ -289,7 +289,7 @@ static struct gpiod_lookup_table nokia770_irq_gpio_table = {
GPIO_LOOKUP("gpio-0-15", 15, "ads7846_irq",
GPIO_ACTIVE_HIGH),
/* GPIO used for retu IRQ */
GPIO_LOOKUP("gpio-48-63", 15, "retu_irq",
GPIO_LOOKUP("gpio-48-63", 14, "retu_irq",
GPIO_ACTIVE_HIGH),
/* GPIO used for tahvo IRQ */
GPIO_LOOKUP("gpio-32-47", 8, "tahvo_irq",

2
arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
View File

@@ -390,6 +390,8 @@
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_rgb666_pins>;
assigned-clocks = <&ccu CLK_TCON0>;
assigned-clock-parents = <&ccu CLK_PLL_VIDEO0_2X>;
status = "okay";
};

2
arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
View File

@@ -369,6 +369,8 @@
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_rgb666_pins>;
assigned-clocks = <&ccu CLK_TCON0>;
assigned-clock-parents = <&ccu CLK_PLL_VIDEO0_2X>;
status = "okay";
};

2
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@@ -410,6 +410,8 @@
clock-names = "ahb", "tcon-ch0";
clock-output-names = "tcon-data-clock";
#clock-cells = <0>;
assigned-clocks = <&ccu CLK_TCON0>;
assigned-clock-parents = <&ccu CLK_PLL_MIPI>;
resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
reset-names = "lcd", "lvds";

29
arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
View File

@@ -938,7 +938,7 @@
interrupt-controller;
#interrupt-cells = <2>;
clock: mt6397clock {
clock: clocks {
compatible = "mediatek,mt6397-clk";
#clock-cells = <1>;
};
@@ -949,11 +949,10 @@
#gpio-cells = <2>;
};
regulator: mt6397regulator {
regulators {
compatible = "mediatek,mt6397-regulator";
mt6397_vpca15_reg: buck_vpca15 {
regulator-compatible = "buck_vpca15";
regulator-name = "vpca15";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -963,7 +962,6 @@
};
mt6397_vpca7_reg: buck_vpca7 {
regulator-compatible = "buck_vpca7";
regulator-name = "vpca7";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -973,7 +971,6 @@
};
mt6397_vsramca15_reg: buck_vsramca15 {
regulator-compatible = "buck_vsramca15";
regulator-name = "vsramca15";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -982,7 +979,6 @@
};
mt6397_vsramca7_reg: buck_vsramca7 {
regulator-compatible = "buck_vsramca7";
regulator-name = "vsramca7";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -991,7 +987,6 @@
};
mt6397_vcore_reg: buck_vcore {
regulator-compatible = "buck_vcore";
regulator-name = "vcore";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -1000,7 +995,6 @@
};
mt6397_vgpu_reg: buck_vgpu {
regulator-compatible = "buck_vgpu";
regulator-name = "vgpu";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -1009,7 +1003,6 @@
};
mt6397_vdrm_reg: buck_vdrm {
regulator-compatible = "buck_vdrm";
regulator-name = "vdrm";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1400000>;
@@ -1018,7 +1011,6 @@
};
mt6397_vio18_reg: buck_vio18 {
regulator-compatible = "buck_vio18";
regulator-name = "vio18";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
@@ -1027,18 +1019,15 @@
};
mt6397_vtcxo_reg: ldo_vtcxo {
regulator-compatible = "ldo_vtcxo";
regulator-name = "vtcxo";
regulator-always-on;
};
mt6397_va28_reg: ldo_va28 {
regulator-compatible = "ldo_va28";
regulator-name = "va28";
};
mt6397_vcama_reg: ldo_vcama {
regulator-compatible = "ldo_vcama";
regulator-name = "vcama";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -1046,18 +1035,15 @@
};
mt6397_vio28_reg: ldo_vio28 {
regulator-compatible = "ldo_vio28";
regulator-name = "vio28";
regulator-always-on;
};
mt6397_vusb_reg: ldo_vusb {
regulator-compatible = "ldo_vusb";
regulator-name = "vusb";
};
mt6397_vmc_reg: ldo_vmc {
regulator-compatible = "ldo_vmc";
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
@@ -1065,7 +1051,6 @@
};
mt6397_vmch_reg: ldo_vmch {
regulator-compatible = "ldo_vmch";
regulator-name = "vmch";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@@ -1073,7 +1058,6 @@
};
mt6397_vemc_3v3_reg: ldo_vemc3v3 {
regulator-compatible = "ldo_vemc3v3";
regulator-name = "vemc_3v3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@@ -1081,7 +1065,6 @@
};
mt6397_vgp1_reg: ldo_vgp1 {
regulator-compatible = "ldo_vgp1";
regulator-name = "vcamd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -1089,7 +1072,6 @@
};
mt6397_vgp2_reg: ldo_vgp2 {
regulator-compatible = "ldo_vgp2";
regulator-name = "vcamio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -1097,7 +1079,6 @@
};
mt6397_vgp3_reg: ldo_vgp3 {
regulator-compatible = "ldo_vgp3";
regulator-name = "vcamaf";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -1105,7 +1086,6 @@
};
mt6397_vgp4_reg: ldo_vgp4 {
regulator-compatible = "ldo_vgp4";
regulator-name = "vgp4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@@ -1113,7 +1093,6 @@
};
mt6397_vgp5_reg: ldo_vgp5 {
regulator-compatible = "ldo_vgp5";
regulator-name = "vgp5";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
@@ -1121,7 +1100,6 @@
};
mt6397_vgp6_reg: ldo_vgp6 {
regulator-compatible = "ldo_vgp6";
regulator-name = "vgp6";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -1130,7 +1108,6 @@
};
mt6397_vibr_reg: ldo_vibr {
regulator-compatible = "ldo_vibr";
regulator-name = "vibr";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <3300000>;
@@ -1138,7 +1115,7 @@
};
};
rtc: mt6397rtc {
rtc: rtc {
compatible = "mediatek,mt6397-rtc";
};

25
arch/arm64/boot/dts/mediatek/mt8173-evb.dts
View File

@@ -308,11 +308,10 @@
interrupt-controller;
#interrupt-cells = <2>;
mt6397regulator: mt6397regulator {
regulators {
compatible = "mediatek,mt6397-regulator";
mt6397_vpca15_reg: buck_vpca15 {
regulator-compatible = "buck_vpca15";
regulator-name = "vpca15";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -321,7 +320,6 @@
};
mt6397_vpca7_reg: buck_vpca7 {
regulator-compatible = "buck_vpca7";
regulator-name = "vpca7";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -330,7 +328,6 @@
};
mt6397_vsramca15_reg: buck_vsramca15 {
regulator-compatible = "buck_vsramca15";
regulator-name = "vsramca15";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -339,7 +336,6 @@
};
mt6397_vsramca7_reg: buck_vsramca7 {
regulator-compatible = "buck_vsramca7";
regulator-name = "vsramca7";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -348,7 +344,6 @@
};
mt6397_vcore_reg: buck_vcore {
regulator-compatible = "buck_vcore";
regulator-name = "vcore";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -357,7 +352,6 @@
};
mt6397_vgpu_reg: buck_vgpu {
regulator-compatible = "buck_vgpu";
regulator-name = "vgpu";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@@ -366,7 +360,6 @@
};
mt6397_vdrm_reg: buck_vdrm {
regulator-compatible = "buck_vdrm";
regulator-name = "vdrm";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1400000>;
@@ -375,7 +368,6 @@
};
mt6397_vio18_reg: buck_vio18 {
regulator-compatible = "buck_vio18";
regulator-name = "vio18";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
@@ -384,19 +376,16 @@
};
mt6397_vtcxo_reg: ldo_vtcxo {
regulator-compatible = "ldo_vtcxo";
regulator-name = "vtcxo";
regulator-always-on;
};
mt6397_va28_reg: ldo_va28 {
regulator-compatible = "ldo_va28";
regulator-name = "va28";
regulator-always-on;
};
mt6397_vcama_reg: ldo_vcama {
regulator-compatible = "ldo_vcama";
regulator-name = "vcama";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2800000>;
@@ -404,18 +393,15 @@
};
mt6397_vio28_reg: ldo_vio28 {
regulator-compatible = "ldo_vio28";
regulator-name = "vio28";
regulator-always-on;
};
mt6397_vusb_reg: ldo_vusb {
regulator-compatible = "ldo_vusb";
regulator-name = "vusb";
};
mt6397_vmc_reg: ldo_vmc {
regulator-compatible = "ldo_vmc";
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
@@ -423,7 +409,6 @@
};
mt6397_vmch_reg: ldo_vmch {
regulator-compatible = "ldo_vmch";
regulator-name = "vmch";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@@ -431,7 +416,6 @@
};
mt6397_vemc_3v3_reg: ldo_vemc3v3 {
regulator-compatible = "ldo_vemc3v3";
regulator-name = "vemc_3v3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@@ -439,7 +423,6 @@
};
mt6397_vgp1_reg: ldo_vgp1 {
regulator-compatible = "ldo_vgp1";
regulator-name = "vcamd";
regulator-min-microvolt = <1220000>;
regulator-max-microvolt = <3300000>;
@@ -447,7 +430,6 @@
};
mt6397_vgp2_reg: ldo_vgp2 {
regulator-compatible = "ldo_vgp2";
regulator-name = "vcamio";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3300000>;
@@ -455,7 +437,6 @@
};
mt6397_vgp3_reg: ldo_vgp3 {
regulator-compatible = "ldo_vgp3";
regulator-name = "vcamaf";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@@ -463,7 +444,6 @@
};
mt6397_vgp4_reg: ldo_vgp4 {
regulator-compatible = "ldo_vgp4";
regulator-name = "vgp4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@@ -471,7 +451,6 @@
};
mt6397_vgp5_reg: ldo_vgp5 {
regulator-compatible = "ldo_vgp5";
regulator-name = "vgp5";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
@@ -479,7 +458,6 @@
};
mt6397_vgp6_reg: ldo_vgp6 {
regulator-compatible = "ldo_vgp6";
regulator-name = "vgp6";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@@ -487,7 +465,6 @@
};
mt6397_vibr_reg: ldo_vibr {
regulator-compatible = "ldo_vibr";
regulator-name = "vibr";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <3300000>;

4
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
View File

@@ -27,6 +27,10 @@
hid-descr-addr = <0x0001>;
};
&mt6358codec {
mediatek,dmic-mode = <1>; /* one-wire */
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_DAMU";
};

15
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
View File

@@ -11,3 +11,18 @@
model = "Google kenzo sku17 board";
compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183";
};
&i2c0 {
touchscreen@40 {
compatible = "hid-over-i2c";
reg = <0x40>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <70>;
hid-descr-addr = <0x0001>;
};
};

15
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
View File

@@ -6,6 +6,21 @@
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
&i2c0 {
touchscreen@40 {
compatible = "hid-over-i2c";
reg = <0x40>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <70>;
hid-descr-addr = <0x0001>;
};
};
&i2c2 {
trackpad@2c {
compatible = "hid-over-i2c";

2
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
View File

@@ -39,8 +39,6 @@
pp3300_panel: pp3300-panel {
compatible = "regulator-fixed";
regulator-name = "pp3300_panel";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pp3300_panel_pins>;

3
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@@ -1026,7 +1026,8 @@
};
keyboard: keyboard@10010000 {
compatible = "mediatek,mt6779-keypad";
compatible = "mediatek,mt8183-keypad",
"mediatek,mt6779-keypad";
reg = <0 0x10010000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_FALLING>;
clocks = <&clk26m>;

8
arch/arm64/boot/dts/mediatek/mt8186.dtsi
View File

@@ -1545,6 +1545,8 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
wakeup-source;
mediatek,syscon-wakeup = <&pericfg 0x420 2>;
status = "disabled";
usb_host0: usb@11200000 {
@@ -1558,8 +1560,6 @@
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,syscon-wakeup = <&pericfg 0x420 2>;
wakeup-source;
status = "disabled";
};
};
@@ -1611,6 +1611,8 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
wakeup-source;
mediatek,syscon-wakeup = <&pericfg 0x424 2>;
status = "disabled";
usb_host1: usb@11280000 {
@@ -1624,8 +1626,6 @@
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,syscon-wakeup = <&pericfg 0x424 2>;
wakeup-source;
status = "disabled";
};
};

3
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
View File

@@ -1391,7 +1391,6 @@
regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
@@ -1401,7 +1400,6 @@
};
mt6315_6_vbuck3: vbuck3 {
regulator-compatible = "vbuck3";
regulator-name = "Vlcpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
@@ -1418,7 +1416,6 @@
regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <800000>;

2
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
View File

@@ -1203,7 +1203,6 @@
regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
@@ -1221,7 +1220,6 @@
regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;

9
arch/arm64/boot/dts/mediatek/mt8195-demo.dts
View File

@@ -137,7 +137,6 @@
richtek,vinovp-microvolt = <14500000>;
otg_vbus_regulator: usb-otg-vbus-regulator {
regulator-compatible = "usb-otg-vbus";
regulator-name = "usb-otg-vbus";
regulator-min-microvolt = <4425000>;
regulator-max-microvolt = <5825000>;
@@ -149,7 +148,6 @@
LDO_VIN3-supply = <&mt6360_buck2>;
mt6360_buck1: buck1 {
regulator-compatible = "BUCK1";
regulator-name = "mt6360,buck1";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1300000>;
@@ -160,7 +158,6 @@
};
mt6360_buck2: buck2 {
regulator-compatible = "BUCK2";
regulator-name = "mt6360,buck2";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1300000>;
@@ -171,7 +168,6 @@
};
mt6360_ldo1: ldo1 {
regulator-compatible = "LDO1";
regulator-name = "mt6360,ldo1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
@@ -180,7 +176,6 @@
};
mt6360_ldo2: ldo2 {
regulator-compatible = "LDO2";
regulator-name = "mt6360,ldo2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
@@ -189,7 +184,6 @@
};
mt6360_ldo3: ldo3 {
regulator-compatible = "LDO3";
regulator-name = "mt6360,ldo3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
@@ -198,7 +192,6 @@
};
mt6360_ldo5: ldo5 {
regulator-compatible = "LDO5";
regulator-name = "mt6360,ldo5";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3600000>;
@@ -207,7 +200,6 @@
};
mt6360_ldo6: ldo6 {
regulator-compatible = "LDO6";
regulator-name = "mt6360,ldo6";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2100000>;
@@ -216,7 +208,6 @@
};
mt6360_ldo7: ldo7 {
regulator-compatible = "LDO7";
regulator-name = "mt6360,ldo7";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2100000>;

5
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@@ -1572,9 +1572,6 @@
phy-names = "pcie-phy";
power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
reset-names = "mac";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
@@ -2680,7 +2677,7 @@
};
ovl0: ovl@1c000000 {
compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
compatible = "mediatek,mt8195-disp-ovl";
reg = <0 0x1c000000 0 0x1000>;
interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;

3
arch/arm64/boot/dts/mediatek/mt8365.dtsi
View File

@@ -334,7 +334,8 @@
};
keypad: keypad@10010000 {
compatible = "mediatek,mt6779-keypad";
compatible = "mediatek,mt8365-keypad",
"mediatek,mt6779-keypad";
reg = <0 0x10010000 0 0x1000>;
wakeup-source;
interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;

11
arch/arm64/boot/dts/mediatek/mt8516.dtsi
View File

@@ -144,10 +144,10 @@
#size-cells = <2>;
ranges;
/* 128 KiB reserved for ARM Trusted Firmware (BL31) */
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
bl31_secmon_reserved: secmon@43000000 {
no-map;
reg = <0 0x43000000 0 0x20000>;
reg = <0 0x43000000 0 0x30000>;
};
};
@@ -206,7 +206,7 @@
compatible = "mediatek,mt8516-wdt",
"mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x1000>;
interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
#reset-cells = <1>;
};
@@ -268,7 +268,7 @@
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x10310000 0 0x1000>,
<0 0x10320000 0 0x1000>,
<0 0x1032f000 0 0x2000>,
<0 0x10340000 0 0x2000>,
<0 0x10360000 0 0x2000>;
interrupts = <GIC_PPI 9
@@ -344,6 +344,7 @@
reg = <0 0x11009000 0 0x90>,
<0 0x11000180 0 0x80>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
clock-div = <2>;
clocks = <&topckgen CLK_TOP_I2C0>,
<&topckgen CLK_TOP_APDMA>;
clock-names = "main", "dma";
@@ -358,6 +359,7 @@
reg = <0 0x1100a000 0 0x90>,
<0 0x11000200 0 0x80>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
clock-div = <2>;
clocks = <&topckgen CLK_TOP_I2C1>,
<&topckgen CLK_TOP_APDMA>;
clock-names = "main", "dma";
@@ -372,6 +374,7 @@
reg = <0 0x1100b000 0 0x90>,
<0 0x11000280 0 0x80>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
clock-div = <2>;
clocks = <&topckgen CLK_TOP_I2C2>,
<&topckgen CLK_TOP_APDMA>;
clock-names = "main", "dma";

2
arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
View File

@@ -47,7 +47,6 @@
};
&i2c0 {
clock-div = <2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
@@ -156,7 +155,6 @@
};
&i2c2 {
clock-div = <2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";

2
arch/arm64/boot/dts/nvidia/tegra234.dtsi
View File

@@ -1794,7 +1794,7 @@
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
resets = <&bpmp TEGRA234_RESET_SPI2>;
reset-names = "spi";
dmas = <&gpcdma 19>, <&gpcdma 19>;
dmas = <&gpcdma 16>, <&gpcdma 16>;
dma-names = "rx", "tx";
dma-coherent;
status = "disabled";

3
arch/arm64/boot/dts/qcom/Makefile
View File

@@ -171,6 +171,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo
dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb

2
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@@ -104,7 +104,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-frequency = <32764>;
};
};

2
arch/arm64/boot/dts/qcom/msm8939.dtsi
View File

@@ -33,7 +33,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-frequency = <32764>;
};
};

11
arch/arm64/boot/dts/qcom/msm8994.dtsi
View File

@@ -34,7 +34,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
};
};
@@ -437,6 +437,15 @@
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"qusb2_phy",
"hs_phy_irq",
"ss_phy_irq";
clocks = <&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>,

2
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
View File

@@ -64,7 +64,7 @@
};
led@1 {
reg = <0>;
reg = <1>;
chan-name = "button-backlight1";
led-cur = /bits/ 8 <0x32>;
max-cur = /bits/ 8 <0xc8>;

9
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@@ -3046,9 +3046,14 @@
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq";
interrupt-names = "pwr_event",
"qusb2_phy",
"hs_phy_irq",
"ss_phy_irq";
clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,

2
arch/arm64/boot/dts/qcom/pm6150.dtsi
View File

@@ -13,7 +13,7 @@
thermal-zones {
pm6150_thermal: pm6150-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm6150_temp>;
trips {

3
arch/arm64/boot/dts/qcom/pm6150l.dtsi
View File

@@ -10,9 +10,6 @@
/ {
thermal-zones {
pm6150l-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm6150l_temp>;
trips {

2
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@@ -28,7 +28,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-frequency = <32764>;
};
};

2
arch/arm64/boot/dts/qcom/qdu1000-idp.dts
View File

@@ -31,7 +31,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};

2
arch/arm64/boot/dts/qcom/qrb4210-rb2.dts
View File

@@ -492,7 +492,7 @@
};
&sleep_clk {
clock-frequency = <32000>;
clock-frequency = <32764>;
};
&tlmm {

2
arch/arm64/boot/dts/qcom/qru1000-idp.dts
View File

@@ -31,7 +31,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};

829
arch/arm64/boot/dts/qcom/sa8775p-ride.dts
View File

@@ -5,828 +5,43 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sa8775p.dtsi"
#include "sa8775p-pmics.dtsi"
#include "sa8775p-ride.dtsi"
/ {
model = "Qualcomm SA8775P Ride";
compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
aliases {
ethernet0 = &ethernet0;
ethernet1 = &ethernet1;
i2c11 = &i2c11;
i2c18 = &i2c18;
serial0 = &uart10;
serial1 = &uart12;
serial2 = &uart17;
spi16 = &spi16;
ufshc1 = &ufs_mem_hc;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "a";
vreg_s4a: smps4 {
regulator-name = "vreg_s4a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1816000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s5a: smps5 {
regulator-name = "vreg_s5a";
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <1996000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s9a: smps9 {
regulator-name = "vreg_s9a";
regulator-min-microvolt = <535000>;
regulator-max-microvolt = <1120000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4a: ldo4 {
regulator-name = "vreg_l4a";
regulator-min-microvolt = <788000>;
regulator-max-microvolt = <1050000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a: ldo5 {
regulator-name = "vreg_l5a";
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6a: ldo6 {
regulator-name = "vreg_l6a";
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a: ldo7 {
regulator-name = "vreg_l7a";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a: ldo8 {
regulator-name = "vreg_l8a";
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9a: ldo9 {
regulator-name = "vreg_l9a";
regulator-min-microvolt = <2970000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-1 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "c";
vreg_l1c: ldo1 {
regulator-name = "vreg_l1c";
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c: ldo2 {
regulator-name = "vreg_l2c";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1100000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3c: ldo3 {
regulator-name = "vreg_l3c";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c: ldo4 {
regulator-name = "vreg_l4c";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
/*
* FIXME: This should have regulator-allow-set-load but
* we're getting an over-current fault from the PMIC
* when switching to LPM.
*/
};
vreg_l5c: ldo5 {
regulator-name = "vreg_l5c";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6c: ldo6 {
regulator-name = "vreg_l6c";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c: ldo7 {
regulator-name = "vreg_l7c";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c: ldo8 {
regulator-name = "vreg_l8c";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c: ldo9 {
regulator-name = "vreg_l9c";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <2700000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-2 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "e";
vreg_s4e: smps4 {
regulator-name = "vreg_s4e";
regulator-min-microvolt = <970000>;
regulator-max-microvolt = <1520000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s7e: smps7 {
regulator-name = "vreg_s7e";
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s9e: smps9 {
regulator-name = "vreg_s9e";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <570000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6e: ldo6 {
regulator-name = "vreg_l6e";
regulator-min-microvolt = <1280000>;
regulator-max-microvolt = <1450000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8e: ldo8 {
regulator-name = "vreg_l8e";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
};
&ethernet0 {
phy-mode = "sgmii";
phy-handle = <&sgmii_phy0>;
pinctrl-0 = <&ethernet0_default>;
pinctrl-names = "default";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,ps-speed = <1000>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
sgmii_phy0: phy@8 {
compatible = "ethernet-phy-id0141.0dd4";
reg = <0x8>;
device_type = "ethernet-phy";
reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
sgmii_phy1: phy@a {
compatible = "ethernet-phy-id0141.0dd4";
reg = <0xa>;
device_type = "ethernet-phy";
reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <4>;
snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};
&ethernet1 {
phy-mode = "sgmii";
phy-handle = <&sgmii_phy1>;
};
snps,mtl-rx-config = <&mtl_rx_setup1>;
snps,mtl-tx-config = <&mtl_tx_setup1>;
snps,ps-speed = <1000>;
&mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
mtl_rx_setup1: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
sgmii_phy0: phy@8 {
compatible = "ethernet-phy-id0141.0dd4";
reg = <0x8>;
device_type = "ethernet-phy";
interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
mtl_tx_setup1: tx-queues-config {
snps,tx-queues-to-use = <4>;
snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
sgmii_phy1: phy@a {
compatible = "ethernet-phy-id0141.0dd4";
reg = <0xa>;
device_type = "ethernet-phy";
interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <70000>;
};
};
&i2c11 {
clock-frequency = <400000>;
pinctrl-0 = <&qup_i2c11_default>;
pinctrl-names = "default";
status = "okay";
};
&i2c18 {
clock-frequency = <400000>;
pinctrl-0 = <&qup_i2c18_default>;
pinctrl-names = "default";
status = "okay";
};
&pmm8654au_0_gpios {
gpio-line-names = "DS_EN",
"POFF_COMPLETE",
"UFS0_VER_ID",
"FAST_POFF",
"DBU1_PON_DONE",
"AOSS_SLEEP",
"CAM_DES0_EN",
"CAM_DES1_EN",
"CAM_DES2_EN",
"CAM_DES3_EN",
"UEFI",
"ANALOG_PON_OPT";
};
&pmm8654au_1_gpios {
gpio-line-names = "PMIC_C_ID0",
"PMIC_C_ID1",
"UFS1_VER_ID",
"IPA_PWR",
"",
"WLAN_DBU4_EN",
"WLAN_EN",
"BT_EN",
"USB2_PWR_EN",
"USB2_FAULT";
usb2_en_state: usb2-en-state {
pins = "gpio9";
function = "normal";
output-high;
power-source = <0>;
};
};
&pmm8654au_2_gpios {
gpio-line-names = "PMIC_E_ID0",
"PMIC_E_ID1",
"USB0_PWR_EN",
"USB0_FAULT",
"SENSOR_IRQ_1",
"SENSOR_IRQ_2",
"SENSOR_RST",
"SGMIIO0_RST",
"SGMIIO1_RST",
"USB1_PWR_ENABLE",
"USB1_FAULT",
"VMON_SPX8";
usb0_en_state: usb0-en-state {
pins = "gpio3";
function = "normal";
output-high;
power-source = <0>;
};
usb1_en_state: usb1-en-state {
pins = "gpio10";
function = "normal";
output-high;
power-source = <0>;
};
};
&pmm8654au_3_gpios {
gpio-line-names = "PMIC_G_ID0",
"PMIC_G_ID1",
"GNSS_RST",
"GNSS_EN",
"GNSS_BOOT_MODE";
};
&qupv3_id_1 {
status = "okay";
};
&qupv3_id_2 {
status = "okay";
};
&serdes0 {
phy-supply = <&vreg_l5a>;
status = "okay";
};
&serdes1 {
phy-supply = <&vreg_l5a>;
status = "okay";
};
&sleep_clk {
clock-frequency = <32764>;
};
&spi16 {
pinctrl-0 = <&qup_spi16_default>;
pinctrl-names = "default";
status = "okay";
};
&tlmm {
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio8";
function = "emac0_mdc";
drive-strength = <16>;
bias-pull-up;
};
ethernet0_mdio: ethernet0-mdio-pins {
pins = "gpio9";
function = "emac0_mdio";
drive-strength = <16>;
bias-pull-up;
};
};
qup_uart10_default: qup-uart10-state {
pins = "gpio46", "gpio47";
function = "qup1_se3";
};
qup_spi16_default: qup-spi16-state {
pins = "gpio86", "gpio87", "gpio88", "gpio89";
function = "qup2_se2";
drive-strength = <6>;
bias-disable;
};
qup_i2c11_default: qup-i2c11-state {
pins = "gpio48", "gpio49";
function = "qup1_se4";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c18_default: qup-i2c18-state {
pins = "gpio95", "gpio96";
function = "qup2_se4";
drive-strength = <2>;
bias-pull-up;
};
qup_uart12_default: qup-uart12-state {
qup_uart12_cts: qup-uart12-cts-pins {
pins = "gpio52";
function = "qup1_se5";
bias-disable;
};
qup_uart12_rts: qup-uart12-rts-pins {
pins = "gpio53";
function = "qup1_se5";
bias-pull-down;
};
qup_uart12_tx: qup-uart12-tx-pins {
pins = "gpio54";
function = "qup1_se5";
bias-pull-up;
};
qup_uart12_rx: qup-uart12-rx-pins {
pins = "gpio55";
function = "qup1_se5";
bias-pull-down;
};
};
qup_uart17_default: qup-uart17-state {
qup_uart17_cts: qup-uart17-cts-pins {
pins = "gpio91";
function = "qup2_se3";
bias-disable;
};
qup_uart17_rts: qup0-uart17-rts-pins {
pins = "gpio92";
function = "qup2_se3";
bias-pull-down;
};
qup_uart17_tx: qup0-uart17-tx-pins {
pins = "gpio93";
function = "qup2_se3";
bias-pull-up;
};
qup_uart17_rx: qup0-uart17-rx-pins {
pins = "gpio94";
function = "qup2_se3";
bias-pull-down;
};
};
pcie0_default_state: pcie0-default-state {
perst-pins {
pins = "gpio2";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio1";
function = "pcie0_clkreq";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio0";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie1_default_state: pcie1-default-state {
perst-pins {
pins = "gpio4";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio3";
function = "pcie1_clkreq";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio5";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&pcie0 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
status = "okay";
};
&pcie1 {
perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
status = "okay";
};
&pcie0_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l1c>;
status = "okay";
};
&pcie1_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l1c>;
status = "okay";
};
&uart10 {
compatible = "qcom,geni-debug-uart";
pinctrl-0 = <&qup_uart10_default>;
pinctrl-names = "default";
status = "okay";
};
&uart12 {
pinctrl-0 = <&qup_uart12_default>;
pinctrl-names = "default";
status = "okay";
};
&uart17 {
pinctrl-0 = <&qup_uart17_default>;
pinctrl-names = "default";
status = "okay";
};
&ufs_mem_hc {
reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l8a>;
vcc-max-microamp = <1100000>;
vccq-supply = <&vreg_l4c>;
vccq-max-microamp = <1200000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l4a>;
vdda-pll-supply = <&vreg_l1c>;
status = "okay";
};
&usb_0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_en_state>;
status = "okay";
};
&usb_0_dwc3 {
dr_mode = "peripheral";
};
&usb_0_hsphy {
vdda-pll-supply = <&vreg_l7a>;
vdda18-supply = <&vreg_l6c>;
vdda33-supply = <&vreg_l9a>;
status = "okay";
};
&usb_0_qmpphy {
vdda-phy-supply = <&vreg_l1c>;
vdda-pll-supply = <&vreg_l7a>;
status = "okay";
};
&usb_1 {
pinctrl-names = "default";
pinctrl-0 = <&usb1_en_state>;
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "host";
};
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l7a>;
vdda18-supply = <&vreg_l6c>;
vdda33-supply = <&vreg_l9a>;
status = "okay";
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l1c>;
vdda-pll-supply = <&vreg_l7a>;
status = "okay";
};
&usb_2 {
pinctrl-names = "default";
pinctrl-0 = <&usb2_en_state>;
status = "okay";
};
&usb_2_dwc3 {
dr_mode = "host";
};
&usb_2_hsphy {
vdda-pll-supply = <&vreg_l7a>;
vdda18-supply = <&vreg_l6c>;
vdda33-supply = <&vreg_l9a>;
status = "okay";
};
&xo_board_clk {
clock-frequency = <38400000>;
};

814
arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi Normal file
View File

@@ -0,0 +1,814 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sa8775p.dtsi"
#include "sa8775p-pmics.dtsi"
/ {
aliases {
ethernet0 = &ethernet0;
ethernet1 = &ethernet1;
i2c11 = &i2c11;
i2c18 = &i2c18;
serial0 = &uart10;
serial1 = &uart12;
serial2 = &uart17;
spi16 = &spi16;
ufshc1 = &ufs_mem_hc;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "a";
vreg_s4a: smps4 {
regulator-name = "vreg_s4a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1816000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s5a: smps5 {
regulator-name = "vreg_s5a";
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <1996000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s9a: smps9 {
regulator-name = "vreg_s9a";
regulator-min-microvolt = <535000>;
regulator-max-microvolt = <1120000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4a: ldo4 {
regulator-name = "vreg_l4a";
regulator-min-microvolt = <788000>;
regulator-max-microvolt = <1050000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a: ldo5 {
regulator-name = "vreg_l5a";
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6a: ldo6 {
regulator-name = "vreg_l6a";
regulator-min-microvolt = <870000>;
regulator-max-microvolt = <970000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a: ldo7 {
regulator-name = "vreg_l7a";
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a: ldo8 {
regulator-name = "vreg_l8a";
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9a: ldo9 {
regulator-name = "vreg_l9a";
regulator-min-microvolt = <2970000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-1 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "c";
vreg_l1c: ldo1 {
regulator-name = "vreg_l1c";
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c: ldo2 {
regulator-name = "vreg_l2c";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1100000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3c: ldo3 {
regulator-name = "vreg_l3c";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c: ldo4 {
regulator-name = "vreg_l4c";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
/*
* FIXME: This should have regulator-allow-set-load but
* we're getting an over-current fault from the PMIC
* when switching to LPM.
*/
};
vreg_l5c: ldo5 {
regulator-name = "vreg_l5c";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6c: ldo6 {
regulator-name = "vreg_l6c";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c: ldo7 {
regulator-name = "vreg_l7c";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c: ldo8 {
regulator-name = "vreg_l8c";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c: ldo9 {
regulator-name = "vreg_l9c";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <2700000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-2 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "e";
vreg_s4e: smps4 {
regulator-name = "vreg_s4e";
regulator-min-microvolt = <970000>;
regulator-max-microvolt = <1520000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s7e: smps7 {
regulator-name = "vreg_s7e";
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s9e: smps9 {
regulator-name = "vreg_s9e";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <570000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6e: ldo6 {
regulator-name = "vreg_l6e";
regulator-min-microvolt = <1280000>;
regulator-max-microvolt = <1450000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8e: ldo8 {
regulator-name = "vreg_l8e";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
};
&ethernet0 {
phy-handle = <&sgmii_phy0>;
pinctrl-0 = <&ethernet0_default>;
pinctrl-names = "default";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,ps-speed = <1000>;
status = "okay";
mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <4>;
snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};
&ethernet1 {
phy-handle = <&sgmii_phy1>;
snps,mtl-rx-config = <&mtl_rx_setup1>;
snps,mtl-tx-config = <&mtl_tx_setup1>;
snps,ps-speed = <1000>;
status = "okay";
mtl_rx_setup1: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
snps,route-ptp;
};
queue2 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x2>;
snps,route-avcp;
};
queue3 {
snps,avb-algorithm;
snps,map-to-dma-channel = <0x3>;
snps,priority = <0xc>;
};
};
mtl_tx_setup1: tx-queues-config {
snps,tx-queues-to-use = <4>;
snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
};
queue1 {
snps,dcb-algorithm;
};
queue2 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
queue3 {
snps,avb-algorithm;
snps,send_slope = <0x1000>;
snps,idle_slope = <0x1000>;
snps,high_credit = <0x3e800>;
snps,low_credit = <0xffc18000>;
};
};
};
&i2c11 {
clock-frequency = <400000>;
pinctrl-0 = <&qup_i2c11_default>;
pinctrl-names = "default";
status = "okay";
};
&i2c18 {
clock-frequency = <400000>;
pinctrl-0 = <&qup_i2c18_default>;
pinctrl-names = "default";
status = "okay";
};
&pmm8654au_0_gpios {
gpio-line-names = "DS_EN",
"POFF_COMPLETE",
"UFS0_VER_ID",
"FAST_POFF",
"DBU1_PON_DONE",
"AOSS_SLEEP",
"CAM_DES0_EN",
"CAM_DES1_EN",
"CAM_DES2_EN",
"CAM_DES3_EN",
"UEFI",
"ANALOG_PON_OPT";
};
&pmm8654au_0_pon_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&pmm8654au_1_gpios {
gpio-line-names = "PMIC_C_ID0",
"PMIC_C_ID1",
"UFS1_VER_ID",
"IPA_PWR",
"",
"WLAN_DBU4_EN",
"WLAN_EN",
"BT_EN",
"USB2_PWR_EN",
"USB2_FAULT";
usb2_en_state: usb2-en-state {
pins = "gpio9";
function = "normal";
output-high;
power-source = <0>;
};
};
&pmm8654au_2_gpios {
gpio-line-names = "PMIC_E_ID0",
"PMIC_E_ID1",
"USB0_PWR_EN",
"USB0_FAULT",
"SENSOR_IRQ_1",
"SENSOR_IRQ_2",
"SENSOR_RST",
"SGMIIO0_RST",
"SGMIIO1_RST",
"USB1_PWR_ENABLE",
"USB1_FAULT",
"VMON_SPX8";
usb0_en_state: usb0-en-state {
pins = "gpio3";
function = "normal";
output-high;
power-source = <0>;
};
usb1_en_state: usb1-en-state {
pins = "gpio10";
function = "normal";
output-high;
power-source = <0>;
};
};
&pmm8654au_3_gpios {
gpio-line-names = "PMIC_G_ID0",
"PMIC_G_ID1",
"GNSS_RST",
"GNSS_EN",
"GNSS_BOOT_MODE";
};
&qupv3_id_1 {
status = "okay";
};
&qupv3_id_2 {
status = "okay";
};
&serdes0 {
phy-supply = <&vreg_l5a>;
status = "okay";
};
&serdes1 {
phy-supply = <&vreg_l5a>;
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&spi16 {
pinctrl-0 = <&qup_spi16_default>;
pinctrl-names = "default";
status = "okay";
};
&tlmm {
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio8";
function = "emac0_mdc";
drive-strength = <16>;
bias-pull-up;
};
ethernet0_mdio: ethernet0-mdio-pins {
pins = "gpio9";
function = "emac0_mdio";
drive-strength = <16>;
bias-pull-up;
};
};
qup_uart10_default: qup-uart10-state {
pins = "gpio46", "gpio47";
function = "qup1_se3";
};
qup_spi16_default: qup-spi16-state {
pins = "gpio86", "gpio87", "gpio88", "gpio89";
function = "qup2_se2";
drive-strength = <6>;
bias-disable;
};
qup_i2c11_default: qup-i2c11-state {
pins = "gpio48", "gpio49";
function = "qup1_se4";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c18_default: qup-i2c18-state {
pins = "gpio95", "gpio96";
function = "qup2_se4";
drive-strength = <2>;
bias-pull-up;
};
qup_uart12_default: qup-uart12-state {
qup_uart12_cts: qup-uart12-cts-pins {
pins = "gpio52";
function = "qup1_se5";
bias-disable;
};
qup_uart12_rts: qup-uart12-rts-pins {
pins = "gpio53";
function = "qup1_se5";
bias-pull-down;
};
qup_uart12_tx: qup-uart12-tx-pins {
pins = "gpio54";
function = "qup1_se5";
bias-pull-up;
};
qup_uart12_rx: qup-uart12-rx-pins {
pins = "gpio55";
function = "qup1_se5";
bias-pull-down;
};
};
qup_uart17_default: qup-uart17-state {
qup_uart17_cts: qup-uart17-cts-pins {
pins = "gpio91";
function = "qup2_se3";
bias-disable;
};
qup_uart17_rts: qup0-uart17-rts-pins {
pins = "gpio92";
function = "qup2_se3";
bias-pull-down;
};
qup_uart17_tx: qup0-uart17-tx-pins {
pins = "gpio93";
function = "qup2_se3";
bias-pull-up;
};
qup_uart17_rx: qup0-uart17-rx-pins {
pins = "gpio94";
function = "qup2_se3";
bias-pull-down;
};
};
pcie0_default_state: pcie0-default-state {
perst-pins {
pins = "gpio2";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio1";
function = "pcie0_clkreq";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio0";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie1_default_state: pcie1-default-state {
perst-pins {
pins = "gpio4";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio3";
function = "pcie1_clkreq";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio5";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&pcie0 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
status = "okay";
};
&pcie1 {
perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
status = "okay";
};
&pcie0_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l1c>;
status = "okay";
};
&pcie1_phy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l1c>;
status = "okay";
};
&uart10 {
compatible = "qcom,geni-debug-uart";
pinctrl-0 = <&qup_uart10_default>;
pinctrl-names = "default";
status = "okay";
};
&uart12 {
pinctrl-0 = <&qup_uart12_default>;
pinctrl-names = "default";
status = "okay";
};
&uart17 {
pinctrl-0 = <&qup_uart17_default>;
pinctrl-names = "default";
status = "okay";
};
&ufs_mem_hc {
reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l8a>;
vcc-max-microamp = <1100000>;
vccq-supply = <&vreg_l4c>;
vccq-max-microamp = <1200000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l4a>;
vdda-pll-supply = <&vreg_l1c>;
status = "okay";
};
&usb_0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_en_state>;
status = "okay";
};
&usb_0_dwc3 {
dr_mode = "peripheral";
};
&usb_0_hsphy {
vdda-pll-supply = <&vreg_l7a>;
vdda18-supply = <&vreg_l6c>;
vdda33-supply = <&vreg_l9a>;
status = "okay";
};
&usb_0_qmpphy {
vdda-phy-supply = <&vreg_l1c>;
vdda-pll-supply = <&vreg_l7a>;
status = "okay";
};
&usb_1 {
pinctrl-names = "default";
pinctrl-0 = <&usb1_en_state>;
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "host";
};
&usb_1_hsphy {
vdda-pll-supply = <&vreg_l7a>;
vdda18-supply = <&vreg_l6c>;
vdda33-supply = <&vreg_l9a>;
status = "okay";
};
&usb_1_qmpphy {
vdda-phy-supply = <&vreg_l1c>;
vdda-pll-supply = <&vreg_l7a>;
status = "okay";
};
&usb_2 {
pinctrl-names = "default";
pinctrl-0 = <&usb2_en_state>;
status = "okay";
};
&usb_2_dwc3 {
dr_mode = "host";
};
&usb_2_hsphy {
vdda-pll-supply = <&vreg_l7a>;
vdda18-supply = <&vreg_l6c>;
vdda33-supply = <&vreg_l9a>;
status = "okay";
};
&xo_board_clk {
clock-frequency = <38400000>;
};

84
arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi
View File

@@ -6,82 +6,82 @@
* by Qualcomm firmware.
*/
&CPU0 {
&cpu0 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU1 {
&cpu1 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU2 {
&cpu2 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU3 {
&cpu3 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU4 {
&cpu4 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU5 {
&cpu5 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&little_cpu_sleep_0
&little_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU6 {
&cpu6 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&big_cpu_sleep_0
&big_cpu_sleep_1
&cluster_sleep_0>;
};
&CPU7 {
&cpu7 {
/delete-property/ power-domains;
/delete-property/ power-domain-names;
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
cpu-idle-states = <&big_cpu_sleep_0
&big_cpu_sleep_1
&cluster_sleep_0>;
};
/delete-node/ &domain_idle_states;
&idle_states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
cluster_sleep_0: cluster-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "cluster-power-down";
arm,psci-suspend-param = <0x40003444>;
@@ -92,15 +92,15 @@
};
};
/delete-node/ &CPU_PD0;
/delete-node/ &CPU_PD1;
/delete-node/ &CPU_PD2;
/delete-node/ &CPU_PD3;
/delete-node/ &CPU_PD4;
/delete-node/ &CPU_PD5;
/delete-node/ &CPU_PD6;
/delete-node/ &CPU_PD7;
/delete-node/ &CLUSTER_PD;
/delete-node/ &cpu_pd0;
/delete-node/ &cpu_pd1;
/delete-node/ &cpu_pd2;
/delete-node/ &cpu_pd3;
/delete-node/ &cpu_pd4;
/delete-node/ &cpu_pd5;
/delete-node/ &cpu_pd6;
/delete-node/ &cpu_pd7;
/delete-node/ &cluster_pd;
&apps_rsc {
/delete-property/ power-domains;

9
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
View File

@@ -26,7 +26,6 @@
thermal-zones {
skin_temp_thermal: skin-temp-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 1>;
sustainable-power = <965>;
@@ -54,14 +53,14 @@
cooling-maps {
map0 {
trip = <&skin_temp_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&skin_temp_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

9
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
View File

@@ -43,7 +43,6 @@
thermal-zones {
skin_temp_thermal: skin-temp-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 1>;
sustainable-power = <965>;
@@ -71,14 +70,14 @@
cooling-maps {
map0 {
trip = <&skin_temp_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&skin_temp_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

7
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
View File

@@ -12,14 +12,11 @@
/ {
thermal-zones {
5v-choke-thermal {
polling-delay-passive = <0>;
polling-delay = <250>;
choke-5v-thermal {
thermal-sensors = <&pm6150_adc_tm 1>;
trips {
5v-choke-crit {
choke-5v-crit {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";

1
arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi
View File

@@ -84,6 +84,7 @@
pinctrl-names = "default";
pinctrl-0 = <&lcd_rst>;
avdd-supply = <&ppvar_lcd>;
avee-supply = <&ppvar_lcd>;
pp1800-supply = <&v1p8_disp>;
pp3300-supply = <&pp3300_dx_edp>;
backlight = <&backlight>;

9
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
View File

@@ -50,7 +50,6 @@
thermal-zones {
skin_temp_thermal: skin-temp-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 1>;
sustainable-power = <574>;
@@ -78,14 +77,14 @@
cooling-maps {
map0 {
trip = <&skin_temp_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&skin_temp_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

3
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View File

@@ -21,9 +21,6 @@
/ {
thermal-zones {
charger_thermal: charger-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 0>;
trips {

387
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@@ -74,28 +74,28 @@
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
next-level-cache = <&L2_0>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
@@ -103,206 +103,206 @@
};
};
CPU1: cpu@100 {
cpu1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD1>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_100>;
next-level-cache = <&l2_100>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU2: cpu@200 {
cpu2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD2>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_200>;
next-level-cache = <&l2_200>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU3: cpu@300 {
cpu3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x300>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD3>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_300>;
next-level-cache = <&l2_300>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU4: cpu@400 {
cpu4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x400>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD4>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_400>;
next-level-cache = <&l2_400>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_400: l2-cache {
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU5: cpu@500 {
cpu5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x500>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD5>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
capacity-dmips-mhz = <415>;
dynamic-power-coefficient = <137>;
next-level-cache = <&L2_500>;
next-level-cache = <&l2_500>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_500: l2-cache {
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU6: cpu@600 {
cpu6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x600>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
power-domains = <&CPU_PD6>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <480>;
next-level-cache = <&L2_600>;
next-level-cache = <&l2_600>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
CPU7: cpu@700 {
cpu7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x700>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
power-domains = <&CPU_PD7>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <480>;
next-level-cache = <&L2_700>;
next-level-cache = <&l2_700>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_700: l2-cache {
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
cpu = <&cpu0>;
};
core1 {
cpu = <&CPU1>;
cpu = <&cpu1>;
};
core2 {
cpu = <&CPU2>;
cpu = <&cpu2>;
};
core3 {
cpu = <&CPU3>;
cpu = <&cpu3>;
};
core4 {
cpu = <&CPU4>;
cpu = <&cpu4>;
};
core5 {
cpu = <&CPU5>;
cpu = <&cpu5>;
};
core6 {
cpu = <&CPU6>;
cpu = <&cpu6>;
};
core7 {
cpu = <&CPU7>;
cpu = <&cpu7>;
};
};
};
@@ -310,7 +310,7 @@
idle_states: idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-power-down";
arm,psci-suspend-param = <0x40000003>;
@@ -320,7 +320,7 @@
local-timer-stop;
};
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
little_cpu_sleep_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "little-rail-power-down";
arm,psci-suspend-param = <0x40000004>;
@@ -330,7 +330,7 @@
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-power-down";
arm,psci-suspend-param = <0x40000003>;
@@ -340,7 +340,7 @@
local-timer-stop;
};
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
big_cpu_sleep_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "big-rail-power-down";
arm,psci-suspend-param = <0x40000004>;
@@ -352,7 +352,7 @@
};
domain_idle_states: domain-idle-states {
CLUSTER_SLEEP_PC: cluster-sleep-0 {
cluster_sleep_pc: cluster-sleep-0 {
compatible = "domain-idle-state";
idle-state-name = "cluster-l3-power-collapse";
arm,psci-suspend-param = <0x41000044>;
@@ -361,7 +361,7 @@
min-residency-us = <6118>;
};
CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
cluster_sleep_cx_ret: cluster-sleep-1 {
compatible = "domain-idle-state";
idle-state-name = "cluster-cx-retention";
arm,psci-suspend-param = <0x41001244>;
@@ -370,7 +370,7 @@
min-residency-us = <8467>;
};
CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
cluster_aoss_sleep: cluster-sleep-2 {
compatible = "domain-idle-state";
idle-state-name = "cluster-power-down";
arm,psci-suspend-param = <0x4100b244>;
@@ -580,59 +580,59 @@
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: cpu0 {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD1: cpu1 {
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD2: cpu2 {
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD3: cpu3 {
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD4: cpu4 {
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD5: cpu5 {
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
CPU_PD6: cpu6 {
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
CPU_PD7: cpu7 {
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
CLUSTER_PD: cpu-cluster0 {
cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_PC
&CLUSTER_SLEEP_CX_RET
&CLUSTER_AOSS_SLEEP>;
domain-idle-states = <&cluster_sleep_pc
&cluster_sleep_cx_ret
&cluster_aoss_sleep>;
};
};
@@ -2465,7 +2465,7 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07040000 0 0x1000>;
cpu = <&CPU0>;
cpu = <&cpu0>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2485,7 +2485,7 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07140000 0 0x1000>;
cpu = <&CPU1>;
cpu = <&cpu1>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2505,7 +2505,7 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07240000 0 0x1000>;
cpu = <&CPU2>;
cpu = <&cpu2>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2525,7 +2525,7 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07340000 0 0x1000>;
cpu = <&CPU3>;
cpu = <&cpu3>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2545,7 +2545,7 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07440000 0 0x1000>;
cpu = <&CPU4>;
cpu = <&cpu4>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2565,7 +2565,7 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07540000 0 0x1000>;
cpu = <&CPU5>;
cpu = <&cpu5>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2585,7 +2585,7 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07640000 0 0x1000>;
cpu = <&CPU6>;
cpu = <&cpu6>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -2605,7 +2605,7 @@
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0 0x07740000 0 0x1000>;
cpu = <&CPU7>;
cpu = <&cpu7>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
@@ -3645,7 +3645,7 @@
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
power-domains = <&CLUSTER_PD>;
power-domains = <&cluster_pd>;
rpmhcc: clock-controller {
compatible = "qcom,sc7180-rpmh-clk";
@@ -3827,7 +3827,6 @@
thermal-zones {
cpu0_thermal: cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 1>;
sustainable-power = <1052>;
@@ -3855,28 +3854,27 @@
cooling-maps {
map0 {
trip = <&cpu0_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu0_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu1_thermal: cpu1-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 2>;
sustainable-power = <1052>;
@@ -3904,28 +3902,27 @@
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu1_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu2_thermal: cpu2-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 3>;
sustainable-power = <1052>;
@@ -3953,28 +3950,27 @@
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu2_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu3_thermal: cpu3-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 4>;
sustainable-power = <1052>;
@@ -4002,28 +3998,27 @@
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu3_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu4_thermal: cpu4-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 5>;
sustainable-power = <1052>;
@@ -4051,28 +4046,27 @@
cooling-maps {
map0 {
trip = <&cpu4_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu4_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu5_thermal: cpu5-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 6>;
sustainable-power = <1052>;
@@ -4100,28 +4094,27 @@
cooling-maps {
map0 {
trip = <&cpu5_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu5_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu6_thermal: cpu6-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 9>;
sustainable-power = <1425>;
@@ -4149,20 +4142,19 @@
cooling-maps {
map0 {
trip = <&cpu6_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu6_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu7_thermal: cpu7-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 10>;
sustainable-power = <1425>;
@@ -4190,20 +4182,19 @@
cooling-maps {
map0 {
trip = <&cpu7_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu7_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu8_thermal: cpu8-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 11>;
sustainable-power = <1425>;
@@ -4231,20 +4222,19 @@
cooling-maps {
map0 {
trip = <&cpu8_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu8_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu9_thermal: cpu9-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 12>;
sustainable-power = <1425>;
@@ -4272,20 +4262,19 @@
cooling-maps {
map0 {
trip = <&cpu9_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu9_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
aoss0-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 0>;
@@ -4306,7 +4295,6 @@
cpuss0-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 7>;
@@ -4326,7 +4314,6 @@
cpuss1-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 8>;
@@ -4346,7 +4333,6 @@
gpuss0-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 13>;
@@ -4374,7 +4360,6 @@
gpuss1-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens0 14>;
@@ -4402,7 +4387,6 @@
aoss1-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 0>;
@@ -4423,7 +4407,6 @@
cwlan-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
@@ -4444,7 +4427,6 @@
audio-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
@@ -4465,7 +4447,6 @@
ddr-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 3>;
@@ -4486,7 +4467,6 @@
q6-hvx-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 4>;
@@ -4507,7 +4487,6 @@
camera-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 5>;
@@ -4528,7 +4507,6 @@
mdm-core-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 6>;
@@ -4549,7 +4527,6 @@
mdm-dsp-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 7>;
@@ -4570,7 +4547,6 @@
npu-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 8>;
@@ -4591,7 +4567,6 @@
video-thermal {
polling-delay-passive = <250>;
polling-delay = <0>;
thermal-sensors = <&tsens1 9>;

2
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@@ -80,7 +80,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};

6
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@@ -2642,7 +2642,7 @@
remoteproc_adsp: remoteproc@3000000 {
compatible = "qcom,sc8280xp-adsp-pas";
reg = <0 0x03000000 0 0x100>;
reg = <0 0x03000000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -4399,7 +4399,7 @@
remoteproc_nsp0: remoteproc@1b300000 {
compatible = "qcom,sc8280xp-nsp0-pas";
reg = <0 0x1b300000 0 0x100>;
reg = <0 0x1b300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
@@ -4530,7 +4530,7 @@
remoteproc_nsp1: remoteproc@21300000 {
compatible = "qcom,sc8280xp-nsp1-pas";
reg = <0 0x21300000 0 0x100>;
reg = <0 0x21300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,

46
arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dts → arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso
View File

@@ -4,8 +4,10 @@
*/
/dts-v1/;
/plugin/;
#include "sdm845-db845c.dts"
#include <dt-bindings/clock/qcom,camcc-sdm845.h>
#include <dt-bindings/gpio/gpio.h>
&camss {
vdda-phy-supply = <&vreg_l1a_0p875>;
@@ -28,6 +30,9 @@
};
&cci_i2c0 {
#address-cells = <1>;
#size-cells = <0>;
camera@10 {
compatible = "ovti,ov8856";
reg = <0x10>;
@@ -63,42 +68,3 @@
};
};
};
&cci_i2c1 {
camera@60 {
compatible = "ovti,ov7251";
/* I2C address as per ov7251.txt linux documentation */
reg = <0x60>;
/* CAM3_RST_N */
enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam3_default>;
clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
clock-names = "xclk";
clock-frequency = <24000000>;
/*
* The &vreg_s4a_1p8 trace always powered on.
*
* The 2.8V vdda-supply regulator is enabled when the
* vreg_s4a_1p8 trace is pulled high.
* It too is represented by a fixed regulator.
*
* No 1.2V vddd-supply regulator is used.
*/
vdddo-supply = <&vreg_lvs1a_1p8>;
vdda-supply = <&cam3_avdd_2v8>;
status = "disabled";
port {
ov7251_ep: endpoint {
data-lanes = <0 1>;
/* remote-endpoint = <&csiphy3_ep>; */
};
};
};
};

20
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@@ -4244,16 +4244,16 @@
"vfe1",
"vfe_lite";
interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csid0",
"csid1",
"csid2",

2
arch/arm64/boot/dts/qcom/sdx75.dtsi
View File

@@ -29,7 +29,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};

2
arch/arm64/boot/dts/qcom/sm4450.dtsi
View File

@@ -23,7 +23,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};

2
arch/arm64/boot/dts/qcom/sm6125.dtsi
View File

@@ -28,7 +28,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
};
};

2
arch/arm64/boot/dts/qcom/sm6375.dtsi
View File

@@ -29,7 +29,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};

16
arch/arm64/boot/dts/qcom/sm7125.dtsi Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#include "sc7180.dtsi"
/* SM7125 uses Kryo 465 instead of Kryo 468 */
&cpu0 { compatible = "qcom,kryo465"; };
&cpu1 { compatible = "qcom,kryo465"; };
&cpu2 { compatible = "qcom,kryo465"; };
&cpu3 { compatible = "qcom,kryo465"; };
&cpu4 { compatible = "qcom,kryo465"; };
&cpu5 { compatible = "qcom,kryo465"; };
&cpu6 { compatible = "qcom,kryo465"; };
&cpu7 { compatible = "qcom,kryo465"; };

2
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
View File

@@ -26,7 +26,7 @@
chassis-type = "handset";
/* required for bootloader to select correct board */
qcom,msm-id = <434 0x10000>, <459 0x10000>;
qcom,msm-id = <459 0x10000>;
qcom,board-id = <8 32>;
aliases {

4
arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
View File

@@ -376,8 +376,8 @@
pinctrl-0 = <&da7280_intr_default>;
dlg,actuator-type = "LRA";
dlg,dlg,const-op-mode = <1>;
dlg,dlg,periodic-op-mode = <1>;
dlg,const-op-mode = <1>;
dlg,periodic-op-mode = <1>;
dlg,nom-microvolt = <2000000>;
dlg,abs-max-microvolt = <2000000>;
dlg,imax-microamp = <129000>;

30
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@@ -85,7 +85,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};
@@ -4121,20 +4121,20 @@
"vfe_lite0",
"vfe_lite1";
interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy0",
"csiphy1",
"csiphy2",

2
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@@ -40,7 +40,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32764>;
#clock-cells = <0>;
};
};

2
arch/arm64/boot/dts/qcom/sm8450.dtsi
View File

@@ -40,7 +40,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-frequency = <32764>;
};
};

1
arch/arm64/boot/dts/ti/k3-am62-main.dtsi
View File

@@ -23,7 +23,6 @@
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x01 0x00000000 0x00 0x2000>, /* GICC */
<0x01 0x00010000 0x00 0x1000>, /* GICH */
<0x01 0x00020000 0x00 0x2000>; /* GICV */

1
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
View File

@@ -18,7 +18,6 @@
compatible = "arm,gic-v3";
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x00 0x01880000 0x00 0xc0000>, /* GICR */
<0x01 0x00000000 0x00 0x2000>, /* GICC */
<0x01 0x00010000 0x00 0x1000>, /* GICH */
<0x01 0x00020000 0x00 0x2000>; /* GICV */

2
arch/hexagon/include/asm/cmpxchg.h
View File

@@ -56,7 +56,7 @@ __arch_xchg(unsigned long x, volatile void *ptr, int size)
__typeof__(ptr) __ptr = (ptr); \
__typeof__(*(ptr)) __old = (old); \
__typeof__(*(ptr)) __new = (new); \
__typeof__(*(ptr)) __oldval = 0; \
__typeof__(*(ptr)) __oldval = (__typeof__(*(ptr))) 0; \
\
asm volatile( \
"1: %0 = memw_locked(%1);\n" \

4
arch/hexagon/kernel/traps.c
View File

@@ -195,8 +195,10 @@ int die(const char *str, struct pt_regs *regs, long err)
printk(KERN_EMERG "Oops: %s[#%d]:\n", str, ++die.counter);
if (notify_die(DIE_OOPS, str, regs, err, pt_cause(regs), SIGSEGV) ==
NOTIFY_STOP)
NOTIFY_STOP) {
spin_unlock_irq(&die.lock);
return 1;
}
print_modules();
show_regs(regs);

4
arch/loongarch/include/asm/hw_breakpoint.h
View File

@@ -38,8 +38,8 @@ struct arch_hw_breakpoint {
* Limits.
* Changing these will require modifications to the register accessors.
*/
#define LOONGARCH_MAX_BRP 8
#define LOONGARCH_MAX_WRP 8
#define LOONGARCH_MAX_BRP 14
#define LOONGARCH_MAX_WRP 14
/* Virtual debug register bases. */
#define CSR_CFG_ADDR 0

60
arch/loongarch/include/asm/loongarch.h
View File

@@ -928,6 +928,36 @@
#define LOONGARCH_CSR_DB7CTRL 0x34a /* data breakpoint 7 control */
#define LOONGARCH_CSR_DB7ASID 0x34b /* data breakpoint 7 asid */
#define LOONGARCH_CSR_DB8ADDR 0x350 /* data breakpoint 8 address */
#define LOONGARCH_CSR_DB8MASK 0x351 /* data breakpoint 8 mask */
#define LOONGARCH_CSR_DB8CTRL 0x352 /* data breakpoint 8 control */
#define LOONGARCH_CSR_DB8ASID 0x353 /* data breakpoint 8 asid */
#define LOONGARCH_CSR_DB9ADDR 0x358 /* data breakpoint 9 address */
#define LOONGARCH_CSR_DB9MASK 0x359 /* data breakpoint 9 mask */
#define LOONGARCH_CSR_DB9CTRL 0x35a /* data breakpoint 9 control */
#define LOONGARCH_CSR_DB9ASID 0x35b /* data breakpoint 9 asid */
#define LOONGARCH_CSR_DB10ADDR 0x360 /* data breakpoint 10 address */
#define LOONGARCH_CSR_DB10MASK 0x361 /* data breakpoint 10 mask */
#define LOONGARCH_CSR_DB10CTRL 0x362 /* data breakpoint 10 control */
#define LOONGARCH_CSR_DB10ASID 0x363 /* data breakpoint 10 asid */
#define LOONGARCH_CSR_DB11ADDR 0x368 /* data breakpoint 11 address */
#define LOONGARCH_CSR_DB11MASK 0x369 /* data breakpoint 11 mask */
#define LOONGARCH_CSR_DB11CTRL 0x36a /* data breakpoint 11 control */
#define LOONGARCH_CSR_DB11ASID 0x36b /* data breakpoint 11 asid */
#define LOONGARCH_CSR_DB12ADDR 0x370 /* data breakpoint 12 address */
#define LOONGARCH_CSR_DB12MASK 0x371 /* data breakpoint 12 mask */
#define LOONGARCH_CSR_DB12CTRL 0x372 /* data breakpoint 12 control */
#define LOONGARCH_CSR_DB12ASID 0x373 /* data breakpoint 12 asid */
#define LOONGARCH_CSR_DB13ADDR 0x378 /* data breakpoint 13 address */
#define LOONGARCH_CSR_DB13MASK 0x379 /* data breakpoint 13 mask */
#define LOONGARCH_CSR_DB13CTRL 0x37a /* data breakpoint 13 control */
#define LOONGARCH_CSR_DB13ASID 0x37b /* data breakpoint 13 asid */
#define LOONGARCH_CSR_FWPC 0x380 /* instruction breakpoint config */
#define LOONGARCH_CSR_FWPS 0x381 /* instruction breakpoint status */
@@ -971,6 +1001,36 @@
#define LOONGARCH_CSR_IB7CTRL 0x3ca /* inst breakpoint 7 control */
#define LOONGARCH_CSR_IB7ASID 0x3cb /* inst breakpoint 7 asid */
#define LOONGARCH_CSR_IB8ADDR 0x3d0 /* inst breakpoint 8 address */
#define LOONGARCH_CSR_IB8MASK 0x3d1 /* inst breakpoint 8 mask */
#define LOONGARCH_CSR_IB8CTRL 0x3d2 /* inst breakpoint 8 control */
#define LOONGARCH_CSR_IB8ASID 0x3d3 /* inst breakpoint 8 asid */
#define LOONGARCH_CSR_IB9ADDR 0x3d8 /* inst breakpoint 9 address */
#define LOONGARCH_CSR_IB9MASK 0x3d9 /* inst breakpoint 9 mask */
#define LOONGARCH_CSR_IB9CTRL 0x3da /* inst breakpoint 9 control */
#define LOONGARCH_CSR_IB9ASID 0x3db /* inst breakpoint 9 asid */
#define LOONGARCH_CSR_IB10ADDR 0x3e0 /* inst breakpoint 10 address */
#define LOONGARCH_CSR_IB10MASK 0x3e1 /* inst breakpoint 10 mask */
#define LOONGARCH_CSR_IB10CTRL 0x3e2 /* inst breakpoint 10 control */
#define LOONGARCH_CSR_IB10ASID 0x3e3 /* inst breakpoint 10 asid */
#define LOONGARCH_CSR_IB11ADDR 0x3e8 /* inst breakpoint 11 address */
#define LOONGARCH_CSR_IB11MASK 0x3e9 /* inst breakpoint 11 mask */
#define LOONGARCH_CSR_IB11CTRL 0x3ea /* inst breakpoint 11 control */
#define LOONGARCH_CSR_IB11ASID 0x3eb /* inst breakpoint 11 asid */
#define LOONGARCH_CSR_IB12ADDR 0x3f0 /* inst breakpoint 12 address */
#define LOONGARCH_CSR_IB12MASK 0x3f1 /* inst breakpoint 12 mask */
#define LOONGARCH_CSR_IB12CTRL 0x3f2 /* inst breakpoint 12 control */
#define LOONGARCH_CSR_IB12ASID 0x3f3 /* inst breakpoint 12 asid */
#define LOONGARCH_CSR_IB13ADDR 0x3f8 /* inst breakpoint 13 address */
#define LOONGARCH_CSR_IB13MASK 0x3f9 /* inst breakpoint 13 mask */
#define LOONGARCH_CSR_IB13CTRL 0x3fa /* inst breakpoint 13 control */
#define LOONGARCH_CSR_IB13ASID 0x3fb /* inst breakpoint 13 asid */
#define LOONGARCH_CSR_DEBUG 0x500 /* debug config */
#define LOONGARCH_CSR_DERA 0x501 /* debug era */
#define LOONGARCH_CSR_DESAVE 0x502 /* debug save */

16
arch/loongarch/kernel/hw_breakpoint.c
View File

@@ -51,7 +51,13 @@ int hw_breakpoint_slots(int type)
READ_WB_REG_CASE(OFF, 4, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 5, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 6, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 7, REG, T, VAL);
READ_WB_REG_CASE(OFF, 7, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 8, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 9, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 10, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 11, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 12, REG, T, VAL); \
READ_WB_REG_CASE(OFF, 13, REG, T, VAL);
#define GEN_WRITE_WB_REG_CASES(OFF, REG, T, VAL) \
WRITE_WB_REG_CASE(OFF, 0, REG, T, VAL); \
@@ -61,7 +67,13 @@ int hw_breakpoint_slots(int type)
WRITE_WB_REG_CASE(OFF, 4, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 5, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 6, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL);
WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 8, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 9, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 10, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 11, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 12, REG, T, VAL); \
WRITE_WB_REG_CASE(OFF, 13, REG, T, VAL);
static u64 read_wb_reg(int reg, int n, int t)
{

2
arch/loongarch/power/platform.c
View File

@@ -17,7 +17,7 @@ void enable_gpe_wakeup(void)
if (acpi_gbl_reduced_hardware)
return;
acpi_enable_all_wakeup_gpes();
acpi_hw_enable_all_wakeup_gpes();
}
void enable_pci_wakeup(void)

9
arch/powerpc/include/asm/hugetlb.h
View File

@@ -15,6 +15,15 @@
extern bool hugetlb_disabled;
static inline bool hugepages_supported(void)
{
if (hugetlb_disabled)
return false;
return HPAGE_SHIFT != 0;
}
#define hugepages_supported hugepages_supported
void __init hugetlbpage_init_defaultsize(void);
int slice_is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,

4
arch/powerpc/kernel/smp.c
View File

@@ -1051,7 +1051,7 @@ static struct sched_domain_topology_level powerpc_topology[] = {
#endif
{ shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) },
{ cpu_mc_mask, SD_INIT_NAME(MC) },
{ cpu_cpu_mask, SD_INIT_NAME(DIE) },
{ cpu_cpu_mask, SD_INIT_NAME(PKG) },
{ NULL, },
};
@@ -1595,7 +1595,7 @@ static void add_cpu_to_masks(int cpu)
/* Skip all CPUs already part of current CPU core mask */
cpumask_andnot(mask, cpu_online_mask, cpu_core_mask(cpu));
/* If chip_id is -1; limit the cpu_core_mask to within DIE*/
/* If chip_id is -1; limit the cpu_core_mask to within PKG */
if (chip_id == -1)
cpumask_and(mask, mask, cpu_cpu_mask(cpu));

4
arch/powerpc/sysdev/xive/native.c
View File

@@ -559,9 +559,7 @@ bool __init xive_native_init(void)
struct device_node *np;
struct resource r;
void __iomem *tima;
struct property *prop;
u8 max_prio = 7;
const __be32 *p;
u32 val, cpu;
s64 rc;
@@ -592,7 +590,7 @@ bool __init xive_native_init(void)
max_prio = val - 1;
/* Iterate the EQ sizes and pick one */
of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) {
of_property_for_each_u32(np, "ibm,xive-eq-sizes", val) {
xive_queue_shift = val;
if (val == PAGE_SHIFT)
break;

3
arch/powerpc/sysdev/xive/spapr.c
View File

@@ -814,7 +814,6 @@ bool __init xive_spapr_init(void)
struct device_node *np;
struct resource r;
void __iomem *tima;
struct property *prop;
u8 max_prio;
u32 val;
u32 len;
@@ -866,7 +865,7 @@ bool __init xive_spapr_init(void)
}
/* Iterate the EQ sizes and pick one */
of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) {
of_property_for_each_u32(np, "ibm,xive-eq-sizes", val) {
xive_queue_shift = val;
if (val == PAGE_SHIFT)
break;

2
arch/riscv/kernel/vector.c
View File

@@ -270,7 +270,7 @@ static int __init riscv_v_sysctl_init(void)
static int __init riscv_v_sysctl_init(void) { return 0; }
#endif /* ! CONFIG_SYSCTL */
static int riscv_v_init(void)
static int __init riscv_v_init(void)
{
return riscv_v_sysctl_init();
}

2
arch/s390/Makefile
View File

@@ -21,7 +21,7 @@ KBUILD_AFLAGS_DECOMPRESSOR := $(CLANG_FLAGS) -m64 -D__ASSEMBLY__
ifndef CONFIG_AS_IS_LLVM
KBUILD_AFLAGS_DECOMPRESSOR += $(if $(CONFIG_DEBUG_INFO),$(aflags_dwarf))
endif
KBUILD_CFLAGS_DECOMPRESSOR := $(CLANG_FLAGS) -m64 -O2 -mpacked-stack
KBUILD_CFLAGS_DECOMPRESSOR := $(CLANG_FLAGS) -m64 -O2 -mpacked-stack -std=gnu11
KBUILD_CFLAGS_DECOMPRESSOR += -DDISABLE_BRANCH_PROFILING -D__NO_FORTIFY
KBUILD_CFLAGS_DECOMPRESSOR += -fno-delete-null-pointer-checks -msoft-float -mbackchain
KBUILD_CFLAGS_DECOMPRESSOR += -fno-asynchronous-unwind-tables

2
arch/s390/kernel/perf_cpum_cf.c
View File

@@ -977,7 +977,7 @@ static int cfdiag_push_sample(struct perf_event *event,
if (event->attr.sample_type & PERF_SAMPLE_RAW) {
raw.frag.size = cpuhw->usedss;
raw.frag.data = cpuhw->stop;
perf_sample_save_raw_data(&data, &raw);
perf_sample_save_raw_data(&data, event, &raw);
}
overflow = perf_event_overflow(event, &data, &regs);

2
arch/s390/kernel/perf_pai_crypto.c
View File

@@ -365,7 +365,7 @@ static int paicrypt_push_sample(void)
if (event->attr.sample_type & PERF_SAMPLE_RAW) {
raw.frag.size = rawsize;
raw.frag.data = cpump->save;
perf_sample_save_raw_data(&data, &raw);
perf_sample_save_raw_data(&data, event, &raw);
}
overflow = perf_event_overflow(event, &data, &regs);

2
arch/s390/kernel/perf_pai_ext.c
View File

@@ -454,7 +454,7 @@ static int paiext_push_sample(void)
if (event->attr.sample_type & PERF_SAMPLE_RAW) {
raw.frag.size = rawsize;
raw.frag.data = cpump->save;
perf_sample_save_raw_data(&data, &raw);
perf_sample_save_raw_data(&data, event, &raw);
}
overflow = perf_event_overflow(event, &data, &regs);

2
arch/s390/kernel/topology.c
View File

@@ -522,7 +522,7 @@ static struct sched_domain_topology_level s390_topology[] = {
{ cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
{ cpu_book_mask, SD_INIT_NAME(BOOK) },
{ cpu_drawer_mask, SD_INIT_NAME(DRAWER) },
{ cpu_cpu_mask, SD_INIT_NAME(DIE) },
{ cpu_cpu_mask, SD_INIT_NAME(PKG) },
{ NULL, },
};

2
arch/s390/purgatory/Makefile
View File

@@ -21,7 +21,7 @@ UBSAN_SANITIZE := n
KASAN_SANITIZE := n
KCSAN_SANITIZE := n
KBUILD_CFLAGS := -fno-strict-aliasing -Wall -Wstrict-prototypes
KBUILD_CFLAGS := -std=gnu11 -fno-strict-aliasing -Wall -Wstrict-prototypes
KBUILD_CFLAGS += -Wno-pointer-sign -Wno-sign-compare
KBUILD_CFLAGS += -fno-zero-initialized-in-bss -fno-builtin -ffreestanding
KBUILD_CFLAGS += -Os -m64 -msoft-float -fno-common

2
arch/x86/events/amd/ibs.c
View File

@@ -1115,7 +1115,7 @@ fail:
.data = ibs_data.data,
},
};
perf_sample_save_raw_data(&data, &raw);
perf_sample_save_raw_data(&data, event, &raw);
}
if (perf_ibs == &perf_ibs_op)

12
arch/x86/kernel/smpboot.c
View File

@@ -604,14 +604,6 @@ static int x86_cluster_flags(void)
}
#endif
static int x86_die_flags(void)
{
if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
return x86_sched_itmt_flags();
return 0;
}
/*
* Set if a package/die has multiple NUMA nodes inside.
* AMD Magny-Cours, Intel Cluster-on-Die, and Intel
@@ -641,13 +633,13 @@ static void __init build_sched_topology(void)
};
#endif
/*
* When there is NUMA topology inside the package skip the DIE domain
* When there is NUMA topology inside the package skip the PKG domain
* since the NUMA domains will auto-magically create the right spanning
* domains based on the SLIT.
*/
if (!x86_has_numa_in_package) {
x86_topology[i++] = (struct sched_domain_topology_level){
cpu_cpu_mask, x86_die_flags, SD_INIT_NAME(DIE)
cpu_cpu_mask, x86_sched_itmt_flags, SD_INIT_NAME(PKG)
};
}

22
block/genhd.c
View File

@@ -763,7 +763,7 @@ static ssize_t disk_badblocks_store(struct device *dev,
}
#ifdef CONFIG_BLOCK_LEGACY_AUTOLOAD
void blk_request_module(dev_t devt)
static bool blk_probe_dev(dev_t devt)
{
unsigned int major = MAJOR(devt);
struct blk_major_name **n;
@@ -773,14 +773,26 @@ void blk_request_module(dev_t devt)
if ((*n)->major == major && (*n)->probe) {
(*n)->probe(devt);
mutex_unlock(&major_names_lock);
return;
return true;
}
}
mutex_unlock(&major_names_lock);
return false;
}
if (request_module("block-major-%d-%d", MAJOR(devt), MINOR(devt)) > 0)
/* Make old-style 2.4 aliases work */
request_module("block-major-%d", MAJOR(devt));
void blk_request_module(dev_t devt)
{
int error;
if (blk_probe_dev(devt))
return;
error = request_module("block-major-%d-%d", MAJOR(devt), MINOR(devt));
/* Make old-style 2.4 aliases work */
if (error > 0)
error = request_module("block-major-%d", MAJOR(devt));
if (!error)
blk_probe_dev(devt);
}
#endif /* CONFIG_BLOCK_LEGACY_AUTOLOAD */

2
block/partitions/ldm.h
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/**
/*
* ldm - Part of the Linux-NTFS project.
*
* Copyright (C) 2001,2002 Richard Russon <ldm@flatcap.org>

2
drivers/acpi/acpica/achware.h
View File

@@ -103,8 +103,6 @@ acpi_hw_get_gpe_status(struct acpi_gpe_event_info *gpe_event_info,
acpi_status acpi_hw_enable_all_runtime_gpes(void);
acpi_status acpi_hw_enable_all_wakeup_gpes(void);
u8 acpi_hw_check_all_gpes(acpi_handle gpe_skip_device, u32 gpe_skip_number);
acpi_status

10
drivers/acpi/fan_core.c
View File

@@ -367,19 +367,25 @@ static int acpi_fan_probe(struct platform_device *pdev)
result = sysfs_create_link(&pdev->dev.kobj,
&cdev->device.kobj,
"thermal_cooling");
if (result)
if (result) {
dev_err(&pdev->dev, "Failed to create sysfs link 'thermal_cooling'\n");
goto err_unregister;
}
result = sysfs_create_link(&cdev->device.kobj,
&pdev->dev.kobj,
"device");
if (result) {
dev_err(&pdev->dev, "Failed to create sysfs link 'device'\n");
goto err_end;
goto err_remove_link;
}
return 0;
err_remove_link:
sysfs_remove_link(&pdev->dev.kobj, "thermal_cooling");
err_unregister:
thermal_cooling_device_unregister(cdev);
err_end:
if (fan->acpi4)
acpi_fan_delete_attributes(device);

9
drivers/base/class.c
View File

@@ -314,8 +314,12 @@ void class_dev_iter_init(struct class_dev_iter *iter, const struct class *class,
struct subsys_private *sp = class_to_subsys(class);
struct klist_node *start_knode = NULL;
if (!sp)
memset(iter, 0, sizeof(*iter));
if (!sp) {
pr_crit("%s: class %p was not registered yet\n",
__func__, class);
return;
}
if (start)
start_knode = &start->p->knode_class;
@@ -342,6 +346,9 @@ struct device *class_dev_iter_next(struct class_dev_iter *iter)
struct klist_node *knode;
struct device *dev;
if (!iter->sp)
return NULL;
while (1) {
knode = klist_next(&iter->ki);
if (!knode)

1
drivers/block/nbd.c
View File

@@ -2164,6 +2164,7 @@ static void nbd_disconnect_and_put(struct nbd_device *nbd)
flush_workqueue(nbd->recv_workq);
nbd_clear_que(nbd);
nbd->task_setup = NULL;
clear_bit(NBD_RT_BOUND, &nbd->config->runtime_flags);
mutex_unlock(&nbd->config_lock);
if (test_and_clear_bit(NBD_RT_HAS_CONFIG_REF,

3
drivers/bluetooth/btnxpuart.c
View File

@@ -1280,13 +1280,12 @@ static void btnxpuart_tx_work(struct work_struct *work)
while ((skb = nxp_dequeue(nxpdev))) {
len = serdev_device_write_buf(serdev, skb->data, skb->len);
serdev_device_wait_until_sent(serdev, 0);
hdev->stat.byte_tx += len;
skb_pull(skb, len);
if (skb->len > 0) {
skb_queue_head(&nxpdev->txq, skb);
break;
continue;
}
switch (hci_skb_pkt_type(skb)) {

4
drivers/bus/ti-sysc.c
View File

@@ -2283,11 +2283,9 @@ static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
const char *name)
{
struct device_node *np = ddata->dev->of_node;
struct property *prop;
const __be32 *p;
u32 val;
of_property_for_each_u32(np, name, prop, p, val) {
of_property_for_each_u32(np, name, val) {
if (val >= SYSC_NR_IDLEMODES) {
dev_err(ddata->dev, "invalid idlemode: %i\n", val);
return -EINVAL;

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