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arm64: dts: rockchip: add u2phy1_otg node for rk3399

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RK3399 SoC USB2 PHY1 comprises with one host-port and
one otg-port, now we support PHY1 otg-port.

Change-Id: I8e7fd53ce6f1552172044ad2adc3f19e923d1bcd
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
This commit is contained in:
Wu Liang feng
2016-07-27 21:57:58 +08:00
committed by Gerrit Code Review
parent fd4c48722a
commit 35e7cfb4c0
1 changed files with 10 additions and 0 deletions
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10
arch/arm64/boot/dts/rockchip/rk3399.dtsi
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@@ -1222,6 +1222,16 @@
clock-output-names = "clk_usbphy1_480m";
status = "disabled";
u2phy1_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
status = "disabled";
};
u2phy1_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;