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drm/rockchip: vop2: config vtoal and vsync independently

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Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I9d5cfaf9105d502e3fad1c88de33e2edf0f25514
This commit is contained in:
Zhang Yubing
2022-07-19 14:14:09 +08:00
committed by Tao Huang
parent 7dec57e6ec
commit 35fd6d07c6
3 changed files with 33 additions and 15 deletions
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7
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -639,7 +639,9 @@ struct vop2_video_port_regs {
struct vop_reg pre_scan_htiming;
struct vop_reg htotal_pw;
struct vop_reg hact_st_end;
struct vop_reg vtotal_pw;
struct vop_reg dsp_vtotal;
struct vop_reg sw_dsp_vtotal_imd;
struct vop_reg dsp_vs_end;
struct vop_reg vact_st_end;
struct vop_reg vact_st_end_f1;
struct vop_reg vs_st_end_f1;
@@ -753,7 +755,8 @@ struct vop2_dsc_regs {
struct vop_reg scan_timing_para_imd_en;
struct vop_reg dsc_htotal_pw;
struct vop_reg dsc_hact_st_end;
struct vop_reg dsc_vtotal_pw;
struct vop_reg dsc_vtotal;
struct vop_reg dsc_vs_end;
struct vop_reg dsc_vact_st_end;
struct vop_reg dsc_error_status;

10
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -5905,13 +5905,13 @@ static bool vop2_crtc_mode_update(struct drm_crtc *crtc)
u16 vact_end = vact_st + vdisplay;
u32 htotal_sync = htotal << 16 | hsync_len;
u32 hactive_st_end = hact_st << 16 | hact_end;
u32 vtotal_sync = vtotal << 16 | vsync_len;
u32 vactive_st_end = vact_st << 16 | vact_end;
u32 crtc_clock = adjusted_mode->crtc_clock * 100;
if (htotal_sync != VOP_MODULE_GET(vop2, vp, htotal_pw) ||
hactive_st_end != VOP_MODULE_GET(vop2, vp, hact_st_end) ||
vtotal_sync != VOP_MODULE_GET(vop2, vp, vtotal_pw) ||
vtotal != VOP_MODULE_GET(vop2, vp, dsp_vtotal) ||
vsync_len != VOP_MODULE_GET(vop2, vp, dsp_vs_end) ||
vactive_st_end != VOP_MODULE_GET(vop2, vp, vact_st_end) ||
crtc_clock != clk_get_rate(vp->dclk))
return true;
@@ -6369,7 +6369,8 @@ static void vop2_crtc_enable_dsc(struct drm_crtc *crtc, struct drm_crtc_state *o
val = dsc_hact_end << 16 | dsc_hact_st;
VOP_MODULE_SET(vop2, dsc, dsc_hact_st_end, val);
VOP_MODULE_SET(vop2, dsc, dsc_vtotal_pw, vtotal << 16 | vsync_len);
VOP_MODULE_SET(vop2, dsc, dsc_vtotal, vtotal);
VOP_MODULE_SET(vop2, dsc, dsc_vs_end, vsync_len);
VOP_MODULE_SET(vop2, dsc, dsc_vact_st_end, vact_end << 16 | vact_st);
}
@@ -6834,7 +6835,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state
VOP_INTR_SET(vop2, intr, line_flag_num[0], act_end);
VOP_INTR_SET(vop2, intr, line_flag_num[1], act_end);
VOP_MODULE_SET(vop2, vp, vtotal_pw, vtotal << 16 | vsync_len);
VOP_MODULE_SET(vop2, vp, dsp_vtotal, vtotal);
VOP_MODULE_SET(vop2, vp, dsp_vs_end, vsync_len);
if (vop2->version == VOP_VERSION_RK3568) {
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK ||

31
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -524,7 +524,8 @@ static const struct vop2_dsc_regs rk3588_vop_dsc_8k_regs = {
.scan_timing_para_imd_en = VOP_REG(RK3588_DSC_8K_INIT_DLY, 0x1, 16),
.dsc_htotal_pw = VOP_REG(RK3588_DSC_8K_HTOTAL_HS_END, 0xffffffff, 0),
.dsc_hact_st_end = VOP_REG(RK3588_DSC_8K_HACT_ST_END, 0xffffffff, 0),
.dsc_vtotal_pw = VOP_REG(RK3588_DSC_8K_VTOTAL_VS_END, 0xffffffff, 0),
.dsc_vtotal = VOP_REG(RK3588_DSC_8K_VTOTAL_VS_END, 0xffff, 16),
.dsc_vs_end = VOP_REG(RK3588_DSC_8K_VTOTAL_VS_END, 0xffff, 0),
.dsc_vact_st_end = VOP_REG(RK3588_DSC_8K_VACT_ST_END, 0xffffffff, 0),
.dsc_error_status = VOP_REG(RK3588_DSC_8K_STATUS, 0x1, 0),
@@ -564,7 +565,8 @@ static const struct vop2_dsc_regs rk3588_vop_dsc_4k_regs = {
.scan_timing_para_imd_en = VOP_REG(RK3588_DSC_4K_INIT_DLY, 0x1, 16),
.dsc_htotal_pw = VOP_REG(RK3588_DSC_4K_HTOTAL_HS_END, 0xffffffff, 0),
.dsc_hact_st_end = VOP_REG(RK3588_DSC_4K_HACT_ST_END, 0xffffffff, 0),
.dsc_vtotal_pw = VOP_REG(RK3588_DSC_4K_VTOTAL_VS_END, 0xffffffff, 0),
.dsc_vtotal = VOP_REG(RK3588_DSC_4K_VTOTAL_VS_END, 0xffff, 16),
.dsc_vs_end = VOP_REG(RK3588_DSC_4K_VTOTAL_VS_END, 0xffff, 0),
.dsc_vact_st_end = VOP_REG(RK3588_DSC_4K_VACT_ST_END, 0xffffffff, 0),
.dsc_error_status = VOP_REG(RK3588_DSC_4K_STATUS, 0x1, 0),
@@ -709,7 +711,8 @@ static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
.post_scl_factor = VOP_REG(RK3568_VP0_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
.post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
.hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.dsp_vtotal = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 16),
.dsp_vs_end = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 0),
.vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
.vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
@@ -791,7 +794,8 @@ static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
.post_scl_factor = VOP_REG(RK3568_VP1_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
.post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0),
.hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.dsp_vtotal = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 16),
.dsp_vs_end = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 0),
.vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0),
.vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
@@ -840,7 +844,8 @@ static const struct vop2_video_port_regs rk3568_vop_vp2_regs = {
.post_scl_ctrl = VOP_REG(RK3568_VP2_POST_SCL_CTRL, 0x3, 0),
.htotal_pw = VOP_REG(RK3568_VP2_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3568_VP2_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.dsp_vtotal = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff, 16),
.dsp_vs_end = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff, 0),
.vact_st_end = VOP_REG(RK3568_VP2_DSP_VACT_ST_END, 0x1fff1fff, 0),
.vact_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.vs_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
@@ -932,7 +937,9 @@ static const struct vop2_video_port_regs rk3588_vop_vp0_regs = {
.post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
.htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0xffffffff, 0),
.hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0xffffffff, 0),
.vtotal_pw = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.dsp_vtotal = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 16),
.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1, 15),
.dsp_vs_end = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 0),
.vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
.vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
@@ -1023,7 +1030,9 @@ static const struct vop2_video_port_regs rk3588_vop_vp1_regs = {
.post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0),
.htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.dsp_vtotal = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 16),
.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1, 15),
.dsp_vs_end = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 0),
.vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0),
.vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
@@ -1110,7 +1119,9 @@ static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
.post_scl_ctrl = VOP_REG(RK3568_VP2_POST_SCL_CTRL, 0x3, 0),
.htotal_pw = VOP_REG(RK3568_VP2_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3568_VP2_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.dsp_vtotal = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff, 16),
.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1, 15),
.dsp_vs_end = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff, 0),
.vact_st_end = VOP_REG(RK3568_VP2_DSP_VACT_ST_END, 0x1fff1fff, 0),
.vact_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.vs_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
@@ -1167,7 +1178,9 @@ static const struct vop2_video_port_regs rk3588_vop_vp3_regs = {
.post_scl_ctrl = VOP_REG(RK3588_VP3_POST_SCL_CTRL, 0x3, 0),
.htotal_pw = VOP_REG(RK3588_VP3_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3588_VP3_DSP_HACT_ST_END, 0x1fff1fff, 0),
.vtotal_pw = VOP_REG(RK3588_VP3_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.dsp_vtotal = VOP_REG(RK3588_VP3_DSP_VTOTAL_VS_END, 0x1fff, 16),
.sw_dsp_vtotal_imd = VOP_REG(RK3588_VP3_DSP_VTOTAL_VS_END, 0x1, 15),
.dsp_vs_end = VOP_REG(RK3588_VP3_DSP_VTOTAL_VS_END, 0x1fff, 0),
.vact_st_end = VOP_REG(RK3588_VP3_DSP_VACT_ST_END, 0x1fff1fff, 0),
.vact_st_end_f1 = VOP_REG(RK3588_VP3_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.vs_st_end_f1 = VOP_REG(RK3588_VP3_DSP_VS_ST_END_F1, 0x1fff1fff, 0),